From patchwork Thu Feb 13 11:36:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237425 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF240my1z9sNg for ; Thu, 13 Feb 2020 22:40:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729532AbgBMLkk (ORCPT ); Thu, 13 Feb 2020 06:40:40 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:41792 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729544AbgBMLkk (ORCPT ); Thu, 13 Feb 2020 06:40:40 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 6558DA1FB160B780FFFE; Thu, 13 Feb 2020 19:40:37 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:31 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 1/9] PCI: add 32 GT/s decoding in some macros Date: Thu, 13 Feb 2020 19:36:25 +0800 Message-ID: <1581593793-23589-2-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Link speed 32.0 GT/s is supported in PCIe r5.0. Add in macro PCIE_SPEED2STR and PCIE_SPEED2MBS_ENC to correctly decode. This patch is a complementary to commit de76cda215d5 ("PCI: Decode PCIe 32 GT/s link speed"). Signed-off-by: Yicong Yang --- drivers/pci/pci.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 6394e77..f65912e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -294,7 +294,8 @@ void pci_bus_put(struct pci_bus *bus); /* PCIe link information */ #define PCIE_SPEED2STR(speed) \ - ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ + ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \ + (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ @@ -302,7 +303,8 @@ void pci_bus_put(struct pci_bus *bus); /* PCIe speed to Mb/s reduced by encoding overhead */ #define PCIE_SPEED2MBS_ENC(speed) \ - ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ + ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ + (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ From patchwork Thu Feb 13 11:36:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237429 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF2744lsz9s29 for ; Thu, 13 Feb 2020 22:40:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729794AbgBMLkq (ORCPT ); Thu, 13 Feb 2020 06:40:46 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54278 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729855AbgBMLkq (ORCPT ); Thu, 13 Feb 2020 06:40:46 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 837953DDD2D538B1A45C; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:31 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 2/9] PCI: Make pci_bus_speed_strings[] public Date: Thu, 13 Feb 2020 19:36:26 +0800 Message-ID: <1581593793-23589-3-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pci_bus_speed_strings[] in slot.c defines universal speed information. Currently it is only used to decode bus speed in slot.c, while elsewhere use judgement statements repeatly to decode speed information. For example, in PCIE_SPEED2STR and current_link_speed_show() in sysfs. Make it public and move to probe.c so that we can reuse it for decoding speed information even if CONFIG_SYSFS is not set. Add pci_bus_speed_strings_size for boundary check purpose, to avoid acquiring size of an external array by ARRAY_SIZE macro. Link:https://lore.kernel.org/linux-pci/20200205183531.GA229621@google.com/ Signed-off-by: Yicong Yang --- drivers/pci/pci.h | 2 ++ drivers/pci/probe.c | 30 ++++++++++++++++++++++++++++++ drivers/pci/slot.c | 31 +------------------------------ 3 files changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index f65912e..d2e92b0f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -12,6 +12,8 @@ #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ extern const unsigned char pcie_link_speed[]; +extern const char *pci_bus_speed_strings[]; +extern const int pci_bus_speed_strings_size; extern bool pci_early_dump; bool pcie_cap_has_lnkctl(const struct pci_dev *dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 512cb43..4e997e7 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -678,6 +678,36 @@ const unsigned char pcie_link_speed[] = { PCI_SPEED_UNKNOWN /* F */ }; +/* these strings match up with the values in pci_bus_speed */ +const char *pci_bus_speed_strings[] = { + "33 MHz PCI", /* 0x00 */ + "66 MHz PCI", /* 0x01 */ + "66 MHz PCI-X", /* 0x02 */ + "100 MHz PCI-X", /* 0x03 */ + "133 MHz PCI-X", /* 0x04 */ + NULL, /* 0x05 */ + NULL, /* 0x06 */ + NULL, /* 0x07 */ + NULL, /* 0x08 */ + "66 MHz PCI-X 266", /* 0x09 */ + "100 MHz PCI-X 266", /* 0x0a */ + "133 MHz PCI-X 266", /* 0x0b */ + "Unknown AGP", /* 0x0c */ + "1x AGP", /* 0x0d */ + "2x AGP", /* 0x0e */ + "4x AGP", /* 0x0f */ + "8x AGP", /* 0x10 */ + "66 MHz PCI-X 533", /* 0x11 */ + "100 MHz PCI-X 533", /* 0x12 */ + "133 MHz PCI-X 533", /* 0x13 */ + "2.5 GT/s PCIe", /* 0x14 */ + "5.0 GT/s PCIe", /* 0x15 */ + "8.0 GT/s PCIe", /* 0x16 */ + "16.0 GT/s PCIe", /* 0x17 */ + "32.0 GT/s PCIe", /* 0x18 */ +}; +const int pci_bus_speed_strings_size = ARRAY_SIZE(pci_bus_speed_strings); + void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) { bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index ae4aa0e..fb7c172 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -49,40 +49,11 @@ static ssize_t address_read_file(struct pci_slot *slot, char *buf) slot->number); } -/* these strings match up with the values in pci_bus_speed */ -static const char *pci_bus_speed_strings[] = { - "33 MHz PCI", /* 0x00 */ - "66 MHz PCI", /* 0x01 */ - "66 MHz PCI-X", /* 0x02 */ - "100 MHz PCI-X", /* 0x03 */ - "133 MHz PCI-X", /* 0x04 */ - NULL, /* 0x05 */ - NULL, /* 0x06 */ - NULL, /* 0x07 */ - NULL, /* 0x08 */ - "66 MHz PCI-X 266", /* 0x09 */ - "100 MHz PCI-X 266", /* 0x0a */ - "133 MHz PCI-X 266", /* 0x0b */ - "Unknown AGP", /* 0x0c */ - "1x AGP", /* 0x0d */ - "2x AGP", /* 0x0e */ - "4x AGP", /* 0x0f */ - "8x AGP", /* 0x10 */ - "66 MHz PCI-X 533", /* 0x11 */ - "100 MHz PCI-X 533", /* 0x12 */ - "133 MHz PCI-X 533", /* 0x13 */ - "2.5 GT/s PCIe", /* 0x14 */ - "5.0 GT/s PCIe", /* 0x15 */ - "8.0 GT/s PCIe", /* 0x16 */ - "16.0 GT/s PCIe", /* 0x17 */ - "32.0 GT/s PCIe", /* 0x18 */ -}; - static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) { const char *speed_string; - if (speed < ARRAY_SIZE(pci_bus_speed_strings)) + if (speed < pci_bus_speed_strings_size) speed_string = pci_bus_speed_strings[speed]; else speed_string = "Unknown"; From patchwork Thu Feb 13 11:36:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF2F1zGnz9s29 for ; Thu, 13 Feb 2020 22:40:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729854AbgBMLkr (ORCPT ); Thu, 13 Feb 2020 06:40:47 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54318 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729820AbgBMLkr (ORCPT ); Thu, 13 Feb 2020 06:40:47 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8E8DFA3B452107E70216; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:32 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 3/9] PCI: Remove PCIe suffix in pci_bus_speed_strings[] Date: Thu, 13 Feb 2020 19:36:27 +0800 Message-ID: <1581593793-23589-4-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Remove "PCIe" suffix of PCIe speed strings in pci_bus_speed_strings[] array. For example, if we use the array to decode link speed in __pcie_print_link_status, it'll lead to redundancy like: - nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8 GT/s x4 link) + nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5 GT/s PCIe x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8 GT/s PCIe x4 link) The patch introduces changes in sysfs when display bus speed of certain slot from cur_bus_speed/max_bus_speed in /sys/bus/pci/slots/*. It may looks like: -/sys/bus/pci/slots/0/cur_bus_speed: 8 GT/s PCIe +/sys/bus/pci/slots/0/cur_bus_speed: 8 GT/s The following patch will compensate and display slot bus speed with "PCIe" suffix as before. [1] https://lore.kernel.org/linux-pci/20200114224909.GA19633@google.com [2] https://lore.kernel.org/linux-pci/20200205183531.GA229621@google.com Signed-off-by: Yicong Yang --- drivers/pci/probe.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4e997e7..6ce47d8 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -700,11 +700,11 @@ const char *pci_bus_speed_strings[] = { "66 MHz PCI-X 533", /* 0x11 */ "100 MHz PCI-X 533", /* 0x12 */ "133 MHz PCI-X 533", /* 0x13 */ - "2.5 GT/s PCIe", /* 0x14 */ - "5.0 GT/s PCIe", /* 0x15 */ - "8.0 GT/s PCIe", /* 0x16 */ - "16.0 GT/s PCIe", /* 0x17 */ - "32.0 GT/s PCIe", /* 0x18 */ + "2.5 GT/s", /* 0x14 */ + "5.0 GT/s", /* 0x15 */ + "8.0 GT/s", /* 0x16 */ + "16.0 GT/s", /* 0x17 */ + "32.0 GT/s", /* 0x18 */ }; const int pci_bus_speed_strings_size = ARRAY_SIZE(pci_bus_speed_strings); From patchwork Thu Feb 13 11:36:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF2G23jnz9sNg for ; Thu, 13 Feb 2020 22:40:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729893AbgBMLku (ORCPT ); Thu, 13 Feb 2020 06:40:50 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54320 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729820AbgBMLku (ORCPT ); Thu, 13 Feb 2020 06:40:50 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 91E3B4B0A746F56FE97B; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:32 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 4/9] PCI: Add comments for link speed info arrays Date: Thu, 13 Feb 2020 19:36:28 +0800 Message-ID: <1581593793-23589-5-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add comments for pcix_bus_speed[] and pcie_link_speed[] arrays. Indicating the capabilities which the information from. Signed-off-by: Yicong Yang --- drivers/pci/probe.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6ce47d8..b97f969 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -640,6 +640,10 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge) } EXPORT_SYMBOL(pci_free_host_bridge); +/* + * these indices represent secondary bus mode and + * frequency from PCI_X_SSTATUS_FREQ + */ static const unsigned char pcix_bus_speed[] = { PCI_SPEED_UNKNOWN, /* 0 */ PCI_SPEED_66MHz_PCIX, /* 1 */ @@ -659,6 +663,10 @@ static const unsigned char pcix_bus_speed[] = { PCI_SPEED_133MHz_PCIX_533 /* F */ }; +/* + * these indices represent PCIe link speed from + * PCI_EXP_LNKCAP, PCI_EXP_LNKSTA, PCI_EXP_LNKCAP2 + */ const unsigned char pcie_link_speed[] = { PCI_SPEED_UNKNOWN, /* 0 */ PCIE_SPEED_2_5GT, /* 1 */ From patchwork Thu Feb 13 11:36:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237430 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF281Tdbz9sP7 for ; Thu, 13 Feb 2020 22:40:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729855AbgBMLkq (ORCPT ); Thu, 13 Feb 2020 06:40:46 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54304 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729721AbgBMLkp (ORCPT ); Thu, 13 Feb 2020 06:40:45 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8B06A3A43107FF3DE178; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:33 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 5/9] PCI: Refactor and rename PCIE_SPEED2STR macro Date: Thu, 13 Feb 2020 19:36:29 +0800 Message-ID: <1581593793-23589-6-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use pci_bus_speed_strings[] array to refactor PCIE_SPEED2STR macro. Rename it with PCI_SPEED2STR as it can also be used to decode non-PCIe speeds with pci_bus_speed_strings[]. Signed-off-by: Yicong Yang --- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.c | 6 +++--- drivers/pci/pci.h | 10 +++------- 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 13f766d..f4eafbc 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -156,7 +156,7 @@ static ssize_t max_link_speed_show(struct device *dev, { struct pci_dev *pdev = to_pci_dev(dev); - return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev))); + return sprintf(buf, "%s\n", PCI_SPEED2STR(pcie_get_speed_cap(pdev))); } static DEVICE_ATTR_RO(max_link_speed); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d828ca8..e8d3c39 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5872,14 +5872,14 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose) if (bw_avail >= bw_cap && verbose) pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", bw_cap / 1000, bw_cap % 1000, - PCIE_SPEED2STR(speed_cap), width_cap); + PCI_SPEED2STR(speed_cap), width_cap); else if (bw_avail < bw_cap) pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", bw_avail / 1000, bw_avail % 1000, - PCIE_SPEED2STR(speed), width, + PCI_SPEED2STR(speed), width, limiting_dev ? pci_name(limiting_dev) : "", bw_cap / 1000, bw_cap % 1000, - PCIE_SPEED2STR(speed_cap), width_cap); + PCI_SPEED2STR(speed_cap), width_cap); } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index d2e92b0f..ba6b2cb 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -295,13 +295,9 @@ struct pci_bus *pci_bus_get(struct pci_bus *bus); void pci_bus_put(struct pci_bus *bus); /* PCIe link information */ -#define PCIE_SPEED2STR(speed) \ - ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \ - (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ - (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ - (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ - (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ - "Unknown speed") +#define PCI_SPEED2STR(speed) \ + ((speed) < pci_bus_speed_strings_size ? \ + pci_bus_speed_strings[speed] : "Unknown speed") /* PCIe speed to Mb/s reduced by encoding overhead */ #define PCIE_SPEED2MBS_ENC(speed) \ From patchwork Thu Feb 13 11:36:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237431 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF286dKLz9sPJ for ; Thu, 13 Feb 2020 22:40:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729721AbgBMLkq (ORCPT ); Thu, 13 Feb 2020 06:40:46 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54322 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729854AbgBMLkq (ORCPT ); Thu, 13 Feb 2020 06:40:46 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9519322483D089902326; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:33 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 6/9] PCI: Refactor bus_speed_read() with PCI_SPEED2STR macro Date: Thu, 13 Feb 2020 19:36:30 +0800 Message-ID: <1581593793-23589-7-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use PCI_SPEED2STR macro to replace judgement statment in bus_speed_read() function. Signed-off-by: Yicong Yang --- drivers/pci/slot.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index fb7c172..1c7e83f2 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -51,14 +51,7 @@ static ssize_t address_read_file(struct pci_slot *slot, char *buf) static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) { - const char *speed_string; - - if (speed < pci_bus_speed_strings_size) - speed_string = pci_bus_speed_strings[speed]; - else - speed_string = "Unknown"; - - return sprintf(buf, "%s\n", speed_string); + return sprintf(buf, "%s\n", PCI_SPEED2STR(speed)); } static ssize_t max_speed_read_file(struct pci_slot *slot, char *buf) From patchwork Thu Feb 13 11:36:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237427 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF2614gQz9sPJ for ; Thu, 13 Feb 2020 22:40:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729674AbgBMLko (ORCPT ); Thu, 13 Feb 2020 06:40:44 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54262 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729544AbgBMLko (ORCPT ); Thu, 13 Feb 2020 06:40:44 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 79CFB50A2F46B9348ACF; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:33 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 7/9] PCI: Add PCIe suffix when display PCIe slot bus speed Date: Thu, 13 Feb 2020 19:36:31 +0800 Message-ID: <1581593793-23589-8-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org "PCIe" suffix of PCIe speed strings in pci_bus_speed_strings[] is removed in previous patch. Add "PCIe" suffix when display PCIe slot bus speed to userspace like before. Signed-off-by: Yicong Yang --- drivers/pci/slot.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.8.1 diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index 1c7e83f2..871d598 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -51,7 +51,10 @@ static ssize_t address_read_file(struct pci_slot *slot, char *buf) static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) { - return sprintf(buf, "%s\n", PCI_SPEED2STR(speed)); + if (speed <= PCI_SPEED_133MHz_PCIX_533) + return sprintf(buf, "%s\n", PCI_SPEED2STR(speed)); + + return sprintf(buf, "%s PCIe\n", PCI_SPEED2STR(speed)); } static ssize_t max_speed_read_file(struct pci_slot *slot, char *buf) From patchwork Thu Feb 13 11:36:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237428 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF266rNWz9sNg for ; Thu, 13 Feb 2020 22:40:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729544AbgBMLko (ORCPT ); Thu, 13 Feb 2020 06:40:44 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54276 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729721AbgBMLko (ORCPT ); Thu, 13 Feb 2020 06:40:44 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 878741F46946CF4475D2; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:33 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 8/9] PCI: Add PCIE_LNKCAP2_SLS2SPEED macro Date: Thu, 13 Feb 2020 19:36:32 +0800 Message-ID: <1581593793-23589-9-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIE_LNKCAP2_SLS2SPEED macro for transforming raw link cap 2 value to link speed. Use it in pcie_get_speed_cap() to replace judgement statements. Then we don't need to touch the functions when new link speed comes. Signed-off-by: Yicong Yang --- drivers/pci/pci.c | 17 ++++------------- drivers/pci/pci.h | 9 +++++++++ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e8d3c39..759b555 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5784,19 +5784,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) * where only 2.5 GT/s and 5.0 GT/s speeds were defined. */ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); - if (lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) - return PCIE_SPEED_32_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - return PCI_SPEED_UNKNOWN; - } + + /* PCIe r3.0-compliant */ + if (lnkcap2) + return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index ba6b2cb..7651749 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -299,6 +299,15 @@ void pci_bus_put(struct pci_bus *bus); ((speed) < pci_bus_speed_strings_size ? \ pci_bus_speed_strings[speed] : "Unknown speed") +/* PCIe link information from Link Capabilities 2 */ +#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ + ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ + (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ + (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ + (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ + (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ + PCI_SPEED_UNKNOWN) + /* PCIe speed to Mb/s reduced by encoding overhead */ #define PCIE_SPEED2MBS_ENC(speed) \ ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ From patchwork Thu Feb 13 11:36:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1237426 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48JF252sxXz9sP7 for ; Thu, 13 Feb 2020 22:40:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729772AbgBMLko (ORCPT ); Thu, 13 Feb 2020 06:40:44 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:54256 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729674AbgBMLko (ORCPT ); Thu, 13 Feb 2020 06:40:44 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 75AA6BFC30F132898F69; Thu, 13 Feb 2020 19:40:42 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 19:40:34 +0800 From: Yicong Yang To: , CC: , Subject: [PATCH v3 9/9] PCI: Reduce redundancy in current_link_speed_show() Date: Thu, 13 Feb 2020 19:36:33 +0800 Message-ID: <1581593793-23589-10-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> References: <1581593793-23589-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Remove switch-case statements in current_link_speed_show(). Use pcie_link_speed[] array to get link speed and PCI_SPEED2STR macro to get link speed string. Signed-off-by: Yicong Yang --- drivers/pci/pci-sysfs.c | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index f4eafbc..eaece10 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -175,33 +175,15 @@ static ssize_t current_link_speed_show(struct device *dev, struct pci_dev *pci_dev = to_pci_dev(dev); u16 linkstat; int err; - const char *speed; + enum pci_bus_speed speed; err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); if (err) return -EINVAL; - switch (linkstat & PCI_EXP_LNKSTA_CLS) { - case PCI_EXP_LNKSTA_CLS_32_0GB: - speed = "32 GT/s"; - break; - case PCI_EXP_LNKSTA_CLS_16_0GB: - speed = "16 GT/s"; - break; - case PCI_EXP_LNKSTA_CLS_8_0GB: - speed = "8 GT/s"; - break; - case PCI_EXP_LNKSTA_CLS_5_0GB: - speed = "5 GT/s"; - break; - case PCI_EXP_LNKSTA_CLS_2_5GB: - speed = "2.5 GT/s"; - break; - default: - speed = "Unknown speed"; - } + speed = pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS]; - return sprintf(buf, "%s\n", speed); + return sprintf(buf, "%s\n", PCI_SPEED2STR(speed)); } static DEVICE_ATTR_RO(current_link_speed);