From patchwork Mon Feb 3 16:51:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 1232922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48BDPs3zfhz9sT0 for ; Tue, 4 Feb 2020 03:52:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728902AbgBCQwA (ORCPT ); Mon, 3 Feb 2020 11:52:00 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:55826 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728074AbgBCQwA (ORCPT ); Mon, 3 Feb 2020 11:52:00 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B4E312C0FADCF0E9617C; Tue, 4 Feb 2020 00:51:55 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.202.226.55) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.439.0; Tue, 4 Feb 2020 00:51:45 +0800 From: Shiju Jose To: , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [PATCH v3 1/2] ACPI: APEI: Add support to notify the vendor specific HW errors Date: Mon, 3 Feb 2020 16:51:21 +0000 Message-ID: <20200203165122.17748-2-shiju.jose@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20200203165122.17748-1-shiju.jose@huawei.com> References: <20200203165122.17748-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.55] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Presently APEI does not support reporting the vendor specific HW errors, received in the vendor defined table entries, to the vendor drivers for any recovery. This patch adds the support to register and unregister the error handling function for the vendor specific HW errors and notify the registered kernel driver. Signed-off-by: Shiju Jose --- drivers/acpi/apei/ghes.c | 116 +++++++++++++++++++++++++++++++++++++++++++++-- include/acpi/ghes.h | 56 +++++++++++++++++++++++ 2 files changed, 167 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 103acbb..69e18d7 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -490,6 +490,109 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata) #endif } +struct ghes_event_notify { + struct list_head list; + struct rcu_head rcu_head; + guid_t sec_type; /* guid of the error record */ + ghes_event_handler_t event_handler; /* event handler function */ + void *data; /* handler driver's private data if any */ +}; + +/* List to store the registered event handling functions */ +static DEFINE_MUTEX(ghes_event_notify_mutex); +static LIST_HEAD(ghes_event_handler_list); + +/** + * ghes_register_event_handler - register an event handling + * function for the non-fatal HW errors. + * @sec_type: sec_type of the corresponding CPER to be notified. + * @event_handler: pointer to the error handling function. + * @data: handler driver's private data. + * + * return 0 : SUCCESS, non-zero : FAIL + */ +int ghes_register_event_handler(guid_t sec_type, + ghes_event_handler_t event_handler, + void *data) +{ + struct ghes_event_notify *event_notify; + + event_notify = kzalloc(sizeof(*event_notify), GFP_KERNEL); + if (!event_notify) + return -ENOMEM; + + event_notify->event_handler = event_handler; + guid_copy(&event_notify->sec_type, &sec_type); + event_notify->data = data; + + mutex_lock(&ghes_event_notify_mutex); + list_add_rcu(&event_notify->list, &ghes_event_handler_list); + mutex_unlock(&ghes_event_notify_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(ghes_register_event_handler); + +/** + * ghes_unregister_event_handler - unregister the previously + * registered event handling function. + * @sec_type: sec_type of the corresponding CPER. + * @data: driver specific data to distinguish devices. + */ +void ghes_unregister_event_handler(guid_t sec_type, void *data) +{ + struct ghes_event_notify *event_notify; + bool found = false; + + mutex_lock(&ghes_event_notify_mutex); + rcu_read_lock(); + list_for_each_entry_rcu(event_notify, + &ghes_event_handler_list, list) { + if (guid_equal(&event_notify->sec_type, &sec_type)) { + if (data != event_notify->data) + continue; + list_del_rcu(&event_notify->list); + found = true; + break; + } + } + rcu_read_unlock(); + mutex_unlock(&ghes_event_notify_mutex); + + if (!found) { + pr_err("Tried to unregister a GHES event handler that has not been registered\n"); + return; + } + + synchronize_rcu(); + kfree(event_notify); +} +EXPORT_SYMBOL_GPL(ghes_unregister_event_handler); + +static int ghes_handle_non_standard_event(guid_t *sec_type, + struct acpi_hest_generic_data *gdata, int sev) +{ + struct ghes_event_notify *event_notify; + bool found = false; + int ret; + + rcu_read_lock(); + list_for_each_entry_rcu(event_notify, + &ghes_event_handler_list, list) { + if (guid_equal(&event_notify->sec_type, sec_type)) { + ret = event_notify->event_handler(gdata, sev, + event_notify->data); + if (!ret) + continue; + found = true; + break; + } + } + rcu_read_unlock(); + + return found; +} + static void ghes_do_proc(struct ghes *ghes, const struct acpi_hest_generic_status *estatus) { @@ -525,11 +628,14 @@ static void ghes_do_proc(struct ghes *ghes, log_arm_hw_error(err); } else { - void *err = acpi_hest_get_payload(gdata); - - log_non_standard_event(sec_type, fru_id, fru_text, - sec_sev, err, - gdata->error_data_length); + if (!ghes_handle_non_standard_event(sec_type, gdata, + sev)) { + void *err = acpi_hest_get_payload(gdata); + + log_non_standard_event(sec_type, fru_id, + fru_text, sec_sev, err, + gdata->error_data_length); + } } } } diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index e3f1cdd..e3387cf 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -50,6 +50,62 @@ enum { GHES_SEV_PANIC = 0x3, }; +enum { + GHES_EVENT_NONE = 0x0, + GHES_EVENT_HANDLED = 0x1, +}; + +/** + * typedef ghes_event_handler_t - event handling function + * for the non-fatal HW errors. + * + * @gdata: acpi_hest_generic_data. + * @sev: error severity of the entire error event defined in the + * ACPI spec table generic error status block. + * @data: handler driver's private data. + * + * Return : GHES_EVENT_NONE - event not handled, GHES_EVENT_HANDLED - handled. + * + * The error handling function is responsible for logging error and + * this function would be called in the interrupt context. + */ +typedef int (*ghes_event_handler_t)(struct acpi_hest_generic_data *gdata, + int sev, void *data); + +#ifdef CONFIG_ACPI_APEI_GHES +/** + * ghes_register_event_handler - register an event handling + * function for the non-fatal HW errors. + * @sec_type: sec_type of the corresponding CPER to be notified. + * @event_handler: pointer to the event handling function. + * @data: handler driver's private data. + * + * Return : 0 - SUCCESS, non-zero - FAIL. + */ +int ghes_register_event_handler(guid_t sec_type, + ghes_event_handler_t event_handler, + void *data); + +/** + * ghes_unregister_event_handler - unregister the previously + * registered event handling function. + * @sec_type: sec_type of the corresponding CPER. + * @data: driver specific data to distinguish devices. + */ +void ghes_unregister_event_handler(guid_t sec_typei, void *data); +#else +static inline int ghes_register_event_handler(guid_t sec_type, + ghes_event_handler_t event_handler, + void *data) +{ + return -ENODEV; +} + +static inline void ghes_unregister_event_handler(guid_t sec_type, void *data) +{ +} +#endif + int ghes_estatus_pool_init(int num_ghes); /* From drivers/edac/ghes_edac.c */ From patchwork Mon Feb 3 16:51:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 1232923 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48BDPy3NpHz9sT0 for ; Tue, 4 Feb 2020 03:52:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729087AbgBCQwF (ORCPT ); Mon, 3 Feb 2020 11:52:05 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:9684 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728074AbgBCQwE (ORCPT ); Mon, 3 Feb 2020 11:52:04 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BE8B34B40E20B6A5A9BF; Tue, 4 Feb 2020 00:52:00 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.202.226.55) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.439.0; Tue, 4 Feb 2020 00:51:49 +0800 From: Shiju Jose To: , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [PATCH v3 2/2] PCI: HIP: Add handling of HiSilicon HIP PCIe controller's errors Date: Mon, 3 Feb 2020 16:51:22 +0000 Message-ID: <20200203165122.17748-3-shiju.jose@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20200203165122.17748-1-shiju.jose@huawei.com> References: <20200203165122.17748-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.55] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Yicong Yang The HiSilicon HIP PCIe controller is capable of handling errors on root port and perform port reset separately at each root port. This patch add error handling driver for HIP PCIe controller to log and report recoverable errors. Perform root port reset and restore link status after the recovery. Following are some of the PCIe controller's recoverable errors 1. completion transmission timeout error. 2. CRS retry counter over the threshold error. 3. ECC 2 bit errors 4. AXI bresponse/rresponse errors etc. Signed-off-by: Yicong Yang Signed-off-by: Shiju Jose Reported-by: kbuild test robot Reported-by: Dan Carpenter --- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-hisi-error.c | 336 +++++++++++++++++++++++++++++++ 3 files changed, 345 insertions(+) create mode 100644 drivers/pci/controller/pcie-hisi-error.c --- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-hisi-error.c | 334 +++++++++++++++++++++++++++++++ 3 files changed, 343 insertions(+) create mode 100644 drivers/pci/controller/pcie-hisi-error.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index c77069c..5dad1ca 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -260,6 +260,14 @@ config PCI_HYPERV_INTERFACE The Hyper-V PCI Interface is a helper driver allows other drivers to have a common interface with the Hyper-V PCI frontend driver. +config PCIE_HISI_ERR + depends on ARM64 || COMPILE_TEST + depends on ACPI + bool "HiSilicon HIP PCIe controller error handling driver" + help + Say Y here if you want error handling support + for the PCIe controller's errors on HiSilicon HIP SoCs + source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/cadence/Kconfig" endmenu diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index 3d4f597..2d1565f 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o +obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pcie-hisi-error.c b/drivers/pci/controller/pcie-hisi-error.c new file mode 100644 index 0000000..5b33a63 --- /dev/null +++ b/drivers/pci/controller/pcie-hisi-error.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for handling the PCIe controller's errors on + * HiSilicon HIP SoCs. + * + * Copyright (c) 2018-2019 HiSilicon Limited. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +#define HISI_PCIE_ERR_RECOVER_RING_SIZE 16 +#define HISI_PCIE_ERR_INFO_SIZE 1024 + +/* HISI PCIe controller's error definitions */ +#define HISI_PCIE_ERR_MISC_REGS 33 + +#define HISI_PCIE_SUB_MODULE_ID_AP 0 +#define HISI_PCIE_SUB_MODULE_ID_TL 1 +#define HISI_PCIE_SUB_MODULE_ID_MAC 2 +#define HISI_PCIE_SUB_MODULE_ID_DL 3 +#define HISI_PCIE_SUB_MODULE_ID_SDI 4 + +#define HISI_PCIE_LOCAL_VALID_VERSION BIT(0) +#define HISI_PCIE_LOCAL_VALID_SOC_ID BIT(1) +#define HISI_PCIE_LOCAL_VALID_SOCKET_ID BIT(2) +#define HISI_PCIE_LOCAL_VALID_NIMBUS_ID BIT(3) +#define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4) +#define HISI_PCIE_LOCAL_VALID_CORE_ID BIT(5) +#define HISI_PCIE_LOCAL_VALID_PORT_ID BIT(6) +#define HISI_PCIE_LOCAL_VALID_ERR_TYPE BIT(7) +#define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY BIT(8) +#define HISI_PCIE_LOCAL_VALID_ERR_MISC 9 + +#define HISI_ERR_SEV_RECOVERABLE 0 +#define HISI_ERR_SEV_FATAL 1 +#define HISI_ERR_SEV_CORRECTED 2 +#define HISI_ERR_SEV_NONE 3 + +static guid_t hisi_pcie_sec_type = GUID_INIT(0xB2889FC9, 0xE7D7, 0x4F9D, + 0xA8, 0x67, 0xAF, 0x42, 0xE9, 0x8B, 0xE7, 0x72); + +#define HISI_PCIE_CORE_ID(v) ((v) >> 3) +#define HISI_PCIE_PORT_ID(core, v) (((v) >> 1) + ((core) << 3)) +#define HISI_PCIE_CORE_PORT_ID(v) (((v) % 8) << 1) + +struct hisi_pcie_err_data { + u64 val_bits; + u8 version; + u8 soc_id; + u8 socket_id; + u8 nimbus_id; + u8 sub_module_id; + u8 core_id; + u8 port_id; + u8 err_severity; + u16 err_type; + u8 reserv[2]; + u32 err_misc[HISI_PCIE_ERR_MISC_REGS]; +}; + +struct hisi_pcie_err_info { + struct hisi_pcie_err_data err_data; + struct platform_device *pdev; +}; + +static char *hisi_pcie_sub_module_name(u8 id) +{ + switch (id) { + case HISI_PCIE_SUB_MODULE_ID_AP: return "AP Layer"; + case HISI_PCIE_SUB_MODULE_ID_TL: return "TL Layer"; + case HISI_PCIE_SUB_MODULE_ID_MAC: return "MAC Layer"; + case HISI_PCIE_SUB_MODULE_ID_DL: return "DL Layer"; + case HISI_PCIE_SUB_MODULE_ID_SDI: return "SDI Layer"; + } + + return "unknown"; +} + +static char *hisi_pcie_err_severity(u8 err_sev) +{ + switch (err_sev) { + case HISI_ERR_SEV_RECOVERABLE: return "recoverable"; + case HISI_ERR_SEV_FATAL: return "fatal"; + case HISI_ERR_SEV_CORRECTED: return "corrected"; + case HISI_ERR_SEV_NONE: return "none"; + } + + return "unknown"; +} + +static int hisi_pcie_port_reset(struct platform_device *pdev, + u32 chip_id, u32 port_id) +{ + struct device *dev = &pdev->dev; + acpi_handle handle = ACPI_HANDLE(dev); + union acpi_object arg[3]; + struct acpi_object_list arg_list; + acpi_status s; + unsigned long long data = 0; + + arg[0].type = ACPI_TYPE_INTEGER; + arg[0].integer.value = chip_id; + arg[1].type = ACPI_TYPE_INTEGER; + arg[1].integer.value = HISI_PCIE_CORE_ID(port_id); + arg[2].type = ACPI_TYPE_INTEGER; + arg[2].integer.value = HISI_PCIE_CORE_PORT_ID(port_id); + + arg_list.count = 3; + arg_list.pointer = arg; + + /* Call the ACPI handle to reset root port */ + s = acpi_evaluate_integer(handle, "RST", &arg_list, &data); + if (ACPI_FAILURE(s)) { + dev_err(dev, "No RST method\n"); + return -EIO; + } + + if (data) { + dev_err(dev, "Failed to Reset\n"); + return -EIO; + } + + return 0; +} + +static int hisi_pcie_port_do_recovery(struct platform_device *dev, + u32 chip_id, u32 port_id) +{ + acpi_status s; + struct device *device = &dev->dev; + acpi_handle root_handle = ACPI_HANDLE(device); + struct acpi_pci_root *pci_root; + struct pci_bus *root_bus; + struct pci_dev *pdev; + u32 domain, busnr, devfn; + + s = acpi_get_parent(root_handle, &root_handle); + if (ACPI_FAILURE(s)) + return -ENODEV; + pci_root = acpi_pci_find_root(root_handle); + if (!pci_root) + return -ENODEV; + root_bus = pci_root->bus; + domain = pci_root->segment; + + busnr = root_bus->number; + devfn = PCI_DEVFN(port_id, 0); + pdev = pci_get_domain_bus_and_slot(domain, busnr, devfn); + if (!pdev) { + dev_info(device, "Fail to get root port %04x:%02x:%02x.%d device\n", + domain, busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + return -ENODEV; + } + + pci_stop_and_remove_bus_device_locked(pdev); + pci_dev_put(pdev); + + if (hisi_pcie_port_reset(dev, chip_id, port_id)) + return -EIO; + + /* + * The initialization time of subordinate devices after + * hot reset is no more than 1s, which is required by + * the PCI spec v5.0 sec 6.6.1. The time will shorten + * if Readiness Notifications mechanisms are used. But + * wait 1s here to adapt any conditions. + */ + ssleep(1UL); + + /* add root port and downstream devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(root_bus); + pci_unlock_rescan_remove(); + + return 0; +} + +static void hisi_pcie_handle_one_error(const struct hisi_pcie_err_data *err, + struct platform_device *pdev) +{ + char buf[HISI_PCIE_ERR_INFO_SIZE]; + char *p = buf, *end = buf + sizeof(buf); + struct device *dev = &pdev->dev; + u32 i; + int rc; + + if (err->val_bits == 0) { + dev_warn(dev, "%s: no valid error information\n", __func__); + return; + } + + /* Logging */ + p += snprintf(p, end - p, "[ Table version=%d ", err->version); + if (err->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID) + p += snprintf(p, end - p, "SOC ID=%d ", err->soc_id); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID) + p += snprintf(p, end - p, "socket ID=%d ", err->socket_id); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID) + p += snprintf(p, end - p, "nimbus ID=%d ", err->nimbus_id); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID) + p += snprintf(p, end - p, "sub module=%s ", + hisi_pcie_sub_module_name(err->sub_module_id)); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID) + p += snprintf(p, end - p, "core ID=core%d ", err->core_id); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID) + p += snprintf(p, end - p, "port ID=port%d ", err->port_id); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY) + p += snprintf(p, end - p, "error severity=%s ", + hisi_pcie_err_severity(err->err_severity)); + + if (err->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE) + p += snprintf(p, end - p, "error type=0x%x ", err->err_type); + + p += snprintf(p, end - p, "]\n"); + dev_info(dev, "\nHISI : HIP : PCIe controller error\n"); + dev_info(dev, "%s\n", buf); + + dev_info(dev, "Reg Dump:\n"); + for (i = 0; i < HISI_PCIE_ERR_MISC_REGS; i++) { + if (err->val_bits & BIT(HISI_PCIE_LOCAL_VALID_ERR_MISC + i)) + dev_info(dev, + "ERR_MISC_%d=0x%x\n", i, err->err_misc[i]); + } + + /* Recovery for the PCIe controller's errors */ + if (err->err_severity == HISI_ERR_SEV_RECOVERABLE) { + /* try reset PCI port for the error recovery */ + rc = hisi_pcie_port_do_recovery(pdev, err->socket_id, + HISI_PCIE_PORT_ID(err->core_id, err->port_id)); + if (rc) { + dev_info(dev, "fail to do hisi pcie port reset\n"); + return; + } + } +} + +static DEFINE_KFIFO(hisi_pcie_err_recover_ring, struct hisi_pcie_err_info, + HISI_PCIE_ERR_RECOVER_RING_SIZE); +static DEFINE_SPINLOCK(hisi_pcie_err_recover_ring_lock); + +static void hisi_pcie_err_recover_work_func(struct work_struct *work) +{ + struct hisi_pcie_err_info pcie_err_entry; + + while (kfifo_get(&hisi_pcie_err_recover_ring, &pcie_err_entry)) { + hisi_pcie_handle_one_error(&pcie_err_entry.err_data, + pcie_err_entry.pdev); + } +} + +static DECLARE_WORK(hisi_pcie_err_recover_work, + hisi_pcie_err_recover_work_func); + +static int hisi_pcie_error_handle(struct acpi_hest_generic_data *gdata, + int sev, void *data) +{ + const struct hisi_pcie_err_data *err_data = + acpi_hest_get_payload(gdata); + struct hisi_pcie_err_info err_info; + struct platform_device *pdev = data; + struct device *dev = &pdev->dev; + u8 socket; + + if (device_property_read_u8(dev, "socket", &socket)) + return GHES_EVENT_NONE; + + if (err_data->socket_id != socket) + return GHES_EVENT_NONE; + + memcpy(&err_info.err_data, err_data, sizeof(*err_data)); + err_info.pdev = pdev; + + if (kfifo_in_spinlocked(&hisi_pcie_err_recover_ring, &err_info, 1, + &hisi_pcie_err_recover_ring_lock)) + schedule_work(&hisi_pcie_err_recover_work); + else + dev_warn(dev, "queue full when recovering PCIe controller's error\n"); + + return GHES_EVENT_HANDLED; +} + +static int hisi_pcie_err_handler_probe(struct platform_device *pdev) +{ + int ret; + + ret = ghes_register_event_handler(hisi_pcie_sec_type, + hisi_pcie_error_handle, pdev); + if (ret) { + dev_err(&pdev->dev, "%s : ghes_register_event_handler fail\n", + __func__); + return ret; + } + + return 0; +} + +static int hisi_pcie_err_handler_remove(struct platform_device *pdev) +{ + ghes_unregister_event_handler(hisi_pcie_sec_type, pdev); + + return 0; +} + +static const struct acpi_device_id hisi_pcie_acpi_match[] = { + { "HISI0361", 0 }, + { } +}; + +static struct platform_driver hisi_pcie_err_handler_driver = { + .driver = { + .name = "hisi-pcie-err-handler", + .acpi_match_table = hisi_pcie_acpi_match, + }, + .probe = hisi_pcie_err_handler_probe, + .remove = hisi_pcie_err_handler_remove, +}; +module_platform_driver(hisi_pcie_err_handler_driver); + +MODULE_DESCRIPTION("HiSilicon HIP PCIe controller's error handling driver"); +MODULE_LICENSE("GPL v2");