From patchwork Tue Sep 5 10:26:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 810072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-461477-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="UwstCGwr"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xmjYw5cvMz9s3w for ; Tue, 5 Sep 2017 20:26:44 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=eSb0yTcR3T60W6PvF9YDh4boMOgqfHns2WHixjyM2iHDdk WK4ZzrRLhIs14INVECgJaFAkhyn8M1BIfsO3/+cEb28yiwHIJh/5TRtTJSOV92/O 1YNyDNVJZktRkLHIR0QapZD27tuWfNDnOKFM0c4GOF/5fCWnJMROw8qdhLJIk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=R7ZR1SOLvm7DnRxntUgxcq0+9Ms=; b=UwstCGwrASC5kV8yjDRe slXLH7LBaZBQgKV0IyXiV0xglUjIH7AWknjz5iHwrchAC9fTptSEx5wHT5Ql2UIy es5IGGiGxiUU5BUqbo2crGxyHbxIki9lfvEFw590j0K9nEdcdkIWSXqU/2I91+Vm fz31u3IpRrsUJIy5+gPllso= Received: (qmail 94156 invoked by alias); 5 Sep 2017 10:26:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 94141 invoked by uid 89); 5 Sep 2017 10:26:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-spam-relays-external:209.85.217.194, H*RU:209.85.217.194, hello! X-HELO: mail-ua0-f194.google.com Received: from mail-ua0-f194.google.com (HELO mail-ua0-f194.google.com) (209.85.217.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 05 Sep 2017 10:26:30 +0000 Received: by mail-ua0-f194.google.com with SMTP id q29so1090027uaf.4 for ; Tue, 05 Sep 2017 03:26:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=fybR4YVG7f8mXxqwE2UmhDeHNAk1dlkKf2EHJnfu/b8=; b=KFcBSSy8j2McgH5kshqvltv8cVrHlvOWo1RjlPzSAyabv7EI82LQnUN09EruUBcrIS rlMcHF4toLNVG16+WwIxylnAzNzn9BMoTvGN/fnypCXMOcZG4R9ZOHMqN3Hf4pzlsmQX 6pYdHZ30olnEf2/Dc/jfVPHOsjFXvBrJIp4CnaPhen0Gu+wJt98XO2aeLDFElRDpIN2s g5c66T1A2wBuxxILC/D/vB2AkM9QijejiefZP3h/UVgh6fGWhar4MK/zKSi+QAJbWx8N js0ebH+2JA1dmUN2h49gwwg4/YZyIkZxIjEJrIlXmLbYxAI8WyfuoyQzIjU7UP+E/T12 Pe3w== X-Gm-Message-State: AHPjjUj9R8bbF3dJaJF+XOH1apIo1A9cY9d5Klyr4f4rYXr/cSFncnUE J5qhnSiEE5AgP8TPBzj0fTb8o0pp82n0 X-Google-Smtp-Source: ADKCNb7tCoAAZNkdWYSzXMuZWluMookFAicZHD14dcXrJqWgbSQDYJ+qcorBUuu9O0/ViEUIJ2WDadbsWxxwD3k8kBk= X-Received: by 10.176.69.243 with SMTP id u106mr2295646uau.22.1504607188723; Tue, 05 Sep 2017 03:26:28 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.55.28 with HTTP; Tue, 5 Sep 2017 03:26:28 -0700 (PDT) From: Uros Bizjak Date: Tue, 5 Sep 2017 12:26:28 +0200 Message-ID: Subject: [PATCH, middle-end]: Introduce memory_blockage named insn pattern To: "gcc-patches@gcc.gnu.org" Hello! This patch allows to emit memory_blockage pattern instead of default asm volatile as a memory blockage. This patch is needed, so targets (e.g. x86) can define and emit more optimal memory blockage pseudo insn. And let's call scheduler memory barriers a "memory blockage" pseudo insn, not "memory barrier" which should describe real instruction. 2017-09-05 Uros Bizjak * optabs.c (expand_memory_blockage): New function. (expand_asm_memory_barrier): Rename ... (expand_asm_memory_blockage): ... to this. (expand_mem_thread_fence): Call expand_memory_blockage instead of expand_asm_memory_barrier. (expand_mem_singnal_fence): Ditto. (expand_atomic_load): Ditto. (expand_atomic_store): Ditto. * doc/md.texi (Standard Pattern Names For Generation): Document memory_blockage instruction pattern. Bootstrapped on x86_64-linux-gnu, regression test (with additional x86 patch that fixes recent optimization regression with FP atomic loads) is in progress. OK for mainline? Uros. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 14aab9474bc2..df4dc8ccd0e1 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -6734,6 +6734,13 @@ scheduler and other passes from moving instructions and using register equivalences across the boundary defined by the blockage insn. This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM. +@cindex @code{memmory_blockage} instruction pattern +@item @samp{memory_blockage} +This pattern defines a pseudo insn that prevents the instruction +scheduler and other passes from moving instructions accessing memory +across the boundary defined by the blockage insn. This instruction +needs to read and write volatile BLKmode memory. + @cindex @code{memory_barrier} instruction pattern @item @samp{memory_barrier} If the target memory model is not fully synchronous, then this pattern diff --git a/gcc/optabs.c b/gcc/optabs.c index b65707080eee..c3b1bc848bf7 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -6276,10 +6276,10 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval, return true; } -/* Generate asm volatile("" : : : "memory") as the memory barrier. */ +/* Generate asm volatile("" : : : "memory") as the memory blockage. */ static void -expand_asm_memory_barrier (void) +expand_asm_memory_blockage (void) { rtx asm_op, clob; @@ -6295,6 +6295,18 @@ expand_asm_memory_barrier (void) emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, asm_op, clob))); } +/* Do not schedule instructions accessing memory across this point. */ + +static void +expand_memory_blockage (void) +{ +#ifdef HAVE_memory_blockage + emit_insn (gen_memory_blockage ()); +#else + expand_asm_memory_blockage (); +#endif +} + /* This routine will either emit the mem_thread_fence pattern or issue a sync_synchronize to generate a fence for memory model MEMMODEL. */ @@ -6306,14 +6318,14 @@ expand_mem_thread_fence (enum memmodel model) if (targetm.have_mem_thread_fence ()) { emit_insn (targetm.gen_mem_thread_fence (GEN_INT (model))); - expand_asm_memory_barrier (); + expand_memory_blockage (); } else if (targetm.have_memory_barrier ()) emit_insn (targetm.gen_memory_barrier ()); else if (synchronize_libfunc != NULL_RTX) emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode); else - expand_asm_memory_barrier (); + expand_memory_blockage (); } /* Emit a signal fence with given memory model. */ @@ -6324,7 +6336,7 @@ expand_mem_signal_fence (enum memmodel model) /* No machine barrier is required to implement a signal fence, but a compiler memory barrier must be issued, except for relaxed MM. */ if (!is_mm_relaxed (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); } /* This function expands the atomic load operation: @@ -6346,7 +6358,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model) struct expand_operand ops[3]; rtx_insn *last = get_last_insn (); if (is_mm_seq_cst (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); create_output_operand (&ops[0], target, mode); create_fixed_operand (&ops[1], mem); @@ -6354,7 +6366,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model) if (maybe_expand_insn (icode, 3, ops)) { if (!is_mm_relaxed (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); return ops[0].value; } delete_insns_since (last); @@ -6404,14 +6416,14 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release) { rtx_insn *last = get_last_insn (); if (!is_mm_relaxed (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); create_fixed_operand (&ops[0], mem); create_input_operand (&ops[1], val, mode); create_integer_operand (&ops[2], model); if (maybe_expand_insn (icode, 3, ops)) { if (is_mm_seq_cst (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); return const0_rtx; } delete_insns_since (last);