From patchwork Fri Jan 10 11:50:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1221011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vLtn3sqTz9sR1 for ; Fri, 10 Jan 2020 22:52:01 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47vLtn2CrDzDqdv for ; Fri, 10 Jan 2020 22:52:01 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47vLsZ3rzQzDqdS for ; Fri, 10 Jan 2020 22:50:57 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00ABmZ52030574 for ; Fri, 10 Jan 2020 06:50:55 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xeregrj90-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 10 Jan 2020 06:50:55 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 10 Jan 2020 11:50:53 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 10 Jan 2020 11:50:51 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00ABomnW52166812 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 10 Jan 2020 11:50:48 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA41DAE057; Fri, 10 Jan 2020 11:50:47 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2A3FFAE04D; Fri, 10 Jan 2020 11:50:46 +0000 (GMT) Received: from pratiks-thinkpad.in.ibm.com (unknown [9.124.31.88]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 10 Jan 2020 11:50:45 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, oohall@gmail.com, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com, psampat@linux.ibm.com Date: Fri, 10 Jan 2020 17:20:40 +0530 X-Mailer: git-send-email 2.24.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20011011-4275-0000-0000-000003966C66 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011011-4276-0000-0000-000038AA5E74 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-10_01:2020-01-10, 2020-01-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 adultscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001100101 Subject: [Skiboot] [RESEND PATCH v2 1/4] Self Save: Introducing Support for SPR Self Save X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Prem Shanker Jha The commit is a merger of commits that makes the following changes: 1. Commit fixes some issues with code found during integration test - replacement of addi with xor instruction during self save API. - fixing instruction generation for MFMSR during self save - data struct updates in STOP API - error RC updates for hcode image build - HOMER parser updates. - removed self save support for URMOR and HRMOR - code changes for compilation with OPAL - populating CME Image header with unsecure HOMER address. Key_Cronus_Test=PM_REGRESS Change-Id: I7cedcc466267c4245255d8d75c01ed695e316720 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66580 Tested-by: FSP CI Jenkins Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Cronus HW CI Tested-by: Hostboot CI Reviewed-by: Gregory S. Still Reviewed-by: RAHUL BATRA Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66587 Reviewed-by: Christian R. Geddes Signed-off-by: Prem Shanker Jha Signed-off-by: Akshay Adiga Signed-off-by: Pratik Rajesh Sampat 2. The commit also incorporates changes that make STOP API project agnostic changes include defining wrapper functions which call legacy API. It also adds duplicate enum members which start with prefix PROC instead of P9. Key_Cronus_Test=PM_REGRESS Change-Id: If87970f3e8cf9b507f33eb1be249e03eb3836a5e RTC: 201128 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71307 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: Cronus HW CI Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Gregory S. Still Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71314 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell Signed-off-by: Prem Shanker Jha Signed-off-by: Pratik Rajesh Sampat --- include/p9_stop_api.H | 79 +- libpore/p9_cpu_reg_restore_instruction.H | 1 + libpore/p9_stop_api.C | 954 +++++++++++++---------- libpore/p9_stop_api.H | 115 ++- libpore/p9_stop_data_struct.H | 4 +- libpore/p9_stop_util.H | 7 +- 6 files changed, 718 insertions(+), 442 deletions(-) diff --git a/include/p9_stop_api.H b/include/p9_stop_api.H index 79abd000..9d3bc1e5 100644 --- a/include/p9_stop_api.H +++ b/include/p9_stop_api.H @@ -63,6 +63,26 @@ typedef enum P9_STOP_SPR_PMCR = 884, // core register P9_STOP_SPR_HID = 1008, // core register P9_STOP_SPR_MSR = 2000, // thread register + + //enum members which are project agnostic + PROC_STOP_SPR_DAWR = 180, // thread register + PROC_STOP_SPR_CIABR = 187, // thread register + PROC_STOP_SPR_DAWRX = 188, // thread register + PROC_STOP_SPR_HSPRG0 = 304, // thread register + PROC_STOP_SPR_HRMOR = 313, // core register + PROC_STOP_SPR_LPCR = 318, // thread register + PROC_STOP_SPR_HMEER = 337, // core register + PROC_STOP_SPR_PTCR = 464, // core register + PROC_STOP_SPR_USPRG0 = 496, // thread register + PROC_STOP_SPR_USPRG1 = 497, // thread register + PROC_STOP_SPR_URMOR = 505, // core register + PROC_STOP_SPR_SMFCTRL = 511, // thread register + PROC_STOP_SPR_LDBAR = 850, // thread register + PROC_STOP_SPR_PSSCR = 855, // thread register + PROC_STOP_SPR_PMCR = 884, // core register + PROC_STOP_SPR_HID = 1008, // core register + PROC_STOP_SPR_MSR = 2000, // thread register + } CpuReg_t; /** @@ -85,6 +105,8 @@ typedef enum STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED = 12, STOP_SAVE_INVALID_FUSED_CORE_STATUS = 13, STOP_SAVE_FAIL = 14, // for internal failure within firmware. + STOP_SAVE_SPR_ENTRY_MISSING = 15, + STOP_SAVE_SPR_BIT_POS_RESERVE = 16, } StopReturnCode_t; /** @@ -101,7 +123,20 @@ typedef enum P9_STOP_SCOM_RESET = 6, P9_STOP_SCOM_OR_APPEND = 7, P9_STOP_SCOM_AND_APPEND = 8, - P9_STOP_SCOM_OP_MAX = 9 + P9_STOP_SCOM_OP_MAX = 9, + + //enum members which are project agnostic + PROC_STOP_SCOM_OP_MIN = 0, + PROC_STOP_SCOM_APPEND = 1, + PROC_STOP_SCOM_REPLACE = 2, + PROC_STOP_SCOM_OR = 3, + PROC_STOP_SCOM_AND = 4, + PROC_STOP_SCOM_NOOP = 5, + PROC_STOP_SCOM_RESET = 6, + PROC_STOP_SCOM_OR_APPEND = 7, + PROC_STOP_SCOM_AND_APPEND = 8, + PROC_STOP_SCOM_OP_MAX = 9, + } ScomOperation_t; /** @@ -114,9 +149,49 @@ typedef enum P9_STOP_SECTION_EQ_SCOM = 2, P9_STOP_SECTION_L2 = 3, P9_STOP_SECTION_L3 = 4, - P9_STOP_SECTION_MAX = 5 + P9_STOP_SECTION_MAX = 5, + + //enum members which are project agnostic + PROC_STOP_SECTION_MIN = 0, + PROC_STOP_SECTION_CORE_SCOM = 1, + PROC_STOP_SECTION_EQ_SCOM = 2, + PROC_STOP_SECTION_L2 = 3, + PROC_STOP_SECTION_L3 = 4, + PROC_STOP_SECTION_MAX = 5, + } ScomSection_t; + + +/** + * @brief List of major incompatibilities between API version. + * @note STOP APIs assumes a specific HOMER layout, certain + * level of CME-SGPE hcode and certain version of self-save restore + * binary. A mismatch can break STOP function. + */ + +/** + * @brief Summarizes bit position allocated to SPRs in save bit mask vector. + */ +typedef enum +{ + BIT_POS_CIABR = 0, + BIT_POS_DAWR = 1, + BIT_POS_DAWRX = 2, + BIT_POS_HSPRG0 = 3, + BIT_POS_LDBAR = 4, + BIT_POS_LPCR = 5, + BIT_POS_PSSCR = 6, + BIT_POS_MSR = 7, + BIT_POS_HID = 21, + BIT_POS_HMEER = 22, + BIT_POS_PMCR = 23, + BIT_POS_PTCR = 24, + BIT_POS_SMFCTRL = 28, + BIT_POS_USPRG0 = 29, + BIT_POS_USPRG1 = 30, +} SprBitPositionList_t; + #ifdef __cplusplus extern "C" { #endif diff --git a/libpore/p9_cpu_reg_restore_instruction.H b/libpore/p9_cpu_reg_restore_instruction.H index dd4358a8..27603b23 100644 --- a/libpore/p9_cpu_reg_restore_instruction.H +++ b/libpore/p9_cpu_reg_restore_instruction.H @@ -68,6 +68,7 @@ enum MFSPR_CONST = 339, BLR_INST = 0x4e800020, MTSPR_BASE_OPCODE = 0x7c0003a6, + MFSPR_BASE_OPCODE = 0x7c0002a6, ATTN_OPCODE = 0x00000200, OPCODE_18 = 18, SELF_SAVE_FUNC_ADD = 0x2300, diff --git a/libpore/p9_stop_api.C b/libpore/p9_stop_api.C index 33aaf788..2d9bb549 100644 --- a/libpore/p9_stop_api.C +++ b/libpore/p9_stop_api.C @@ -54,33 +54,33 @@ namespace stopImageSection const StopSprReg_t g_sprRegister[] = { - { P9_STOP_SPR_CIABR, true, 0 }, - { P9_STOP_SPR_DAWR, true, 1 }, - { P9_STOP_SPR_DAWRX, true, 2 }, - { P9_STOP_SPR_HSPRG0, true, 3 }, - { P9_STOP_SPR_LDBAR, true, 4, }, - { P9_STOP_SPR_LPCR, true, 5 }, - { P9_STOP_SPR_PSSCR, true, 6 }, - { P9_STOP_SPR_MSR, true, 7 }, - { P9_STOP_SPR_HRMOR, false, 20 }, - { P9_STOP_SPR_HID, false, 21 }, - { P9_STOP_SPR_HMEER, false, 22 }, - { P9_STOP_SPR_PMCR, false, 23 }, - { P9_STOP_SPR_PTCR, false, 24 }, - { P9_STOP_SPR_SMFCTRL, true, 28 }, - { P9_STOP_SPR_USPRG0, true, 29 }, - { P9_STOP_SPR_USPRG1, true, 30 }, - { P9_STOP_SPR_URMOR, false, 31 }, + { P9_STOP_SPR_CIABR, true, 0 }, + { P9_STOP_SPR_DAWR, true, 1 }, + { P9_STOP_SPR_DAWRX, true, 2 }, + { P9_STOP_SPR_HSPRG0, true, 3 }, + { P9_STOP_SPR_LDBAR, true, 4, }, + { P9_STOP_SPR_LPCR, true, 5 }, + { P9_STOP_SPR_PSSCR, true, 6 }, + { P9_STOP_SPR_MSR, true, 7 }, + { P9_STOP_SPR_HRMOR, false, 255 }, + { P9_STOP_SPR_HID, false, 21 }, + { P9_STOP_SPR_HMEER, false, 22 }, + { P9_STOP_SPR_PMCR, false, 23 }, + { P9_STOP_SPR_PTCR, false, 24 }, + { P9_STOP_SPR_SMFCTRL, true, 28 }, + { P9_STOP_SPR_USPRG0, true, 29 }, + { P9_STOP_SPR_USPRG1, true, 30 }, + { P9_STOP_SPR_URMOR, false, 255 }, }; -const uint32_t MAX_SPR_SUPPORTED = 17; +const uint32_t MAX_SPR_SUPPORTED = 17; const uint32_t LEGACY_CORE_SCOM_SUPPORTED = 15; const uint32_t LEGACY_QUAD_SCOM_SUPPORTED = 63; //----------------------------------------------------------------------------- /** - * @brief vaildated input arguments passed to p9_stop_save_cpureg_control. + * @brief validated input arguments passed to p9_stop_save_cpureg_control. * @param[in] i_pImage point to start of HOMER * @param[in] i_coreId id of the core * @param[in] i_threadId id of the thread @@ -255,7 +255,7 @@ STATIC uint32_t getOriInstruction( const uint16_t i_Rs, const uint16_t i_Ra, */ STATIC uint32_t genKeyForSprLookup( const CpuReg_t i_regId ) { - return getOriInstruction( 0, 0, (uint16_t) i_regId ); + return getOriInstruction( 24, 0, (uint16_t) i_regId ); } //----------------------------------------------------------------------------- @@ -330,7 +330,7 @@ STATIC uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) */ STATIC uint32_t getMfmsrInstruction( const uint16_t i_Rt ) { - uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | (MFMSR_CONST)); + uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | ((MFMSR_CONST)<< 1)); return SWIZZLE_4_BYTE(mfmsrInstOpcode); } @@ -361,8 +361,13 @@ STATIC uint32_t getRldicrInstruction( const uint16_t i_Ra, const uint16_t i_Rs, STATIC uint32_t getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_sprNum ) { - uint32_t mfsprInstOpcode = 0; - mfsprInstOpcode = (( OPCODE_31 << 26 ) | ( i_Rt << 21 ) | ( i_sprNum << 11 ) | ( MFSPR_CONST << 1 )); + uint32_t mfsprInstOpcode = 0; + uint32_t temp = (( i_sprNum & 0x03FF ) << 11); + mfsprInstOpcode = (uint8_t)i_Rt << 21; + mfsprInstOpcode |= (( temp & 0x0000F800 ) << 5); + mfsprInstOpcode |= (( temp & 0x001F0000 ) >> 5); + mfsprInstOpcode |= MFSPR_BASE_OPCODE; + return SWIZZLE_4_BYTE(mfsprInstOpcode); } @@ -615,14 +620,14 @@ STATIC StopReturnCode_t getSprRegIndexAdjustment( const uint32_t i_saveMaskPos, do { - if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_19 )) || + if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_20 )) || (( i_saveMaskPos >= SPR_BIT_POS_25 ) && ( i_saveMaskPos <= SPR_BIT_POS_27 )) ) { l_rc = STOP_SAVE_SPR_BIT_POS_RESERVE; break; } - if( (i_saveMaskPos > SPR_BIT_POS_19) && (i_saveMaskPos < SPR_BIT_POS_25 ) ) + if( (i_saveMaskPos > SPR_BIT_POS_20) && (i_saveMaskPos < SPR_BIT_POS_25) ) { *i_sprAdjIndex = 12; } @@ -646,138 +651,9 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage, const uint64_t i_regData, const uint64_t i_pir ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; // procedure return code - HomerSection_t* chipHomer = NULL; - SmfHomerSection_t* smfChipHomer = NULL; - - do - { - uint32_t threadId = 0; - uint32_t coreId = 0; - uint32_t lookUpKey = 0; - void* pSprEntryLocation = NULL; // an offset w.r.t. to start of image - void* pThreadLocation = NULL; - bool threadScopeReg = false; - uint8_t l_urmorFix = false; - uint64_t l_sprValue = 0; - uint8_t l_selfRestVer = 0; - - MY_INF(">> p9_stop_save_cpureg" ); - - l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); - - if( l_rc ) - { - MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016llx", - i_pir); - break; - } - - MY_INF( " PIR 0x%016llx coreId %d threadid %d " - " registerId %d", i_pir, coreId, - threadId, i_regId ); - - // First of all let us validate all input arguments. - l_rc = validateSprImageInputs( i_pImage, - i_regId, - coreId, - &threadId, - &threadScopeReg ); - - if( l_rc ) - { - // Error: bad argument traces out error code - MY_ERR("Bad input argument rc %d", l_rc ); - - break; - } - - l_urmorFix = *(uint8_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + CPMR_URMOR_FIX_BYTE); - l_selfRestVer = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); - - if( l_selfRestVer ) - { - smfChipHomer = ( SmfHomerSection_t*)i_pImage; - - if( threadScopeReg ) - { - pThreadLocation = - &(smfChipHomer->iv_coreThreadRestore[coreId].iv_threadRestoreArea[threadId][0]); - } - else - { - pThreadLocation = - &(smfChipHomer->iv_coreThreadRestore[coreId].iv_coreRestoreArea[0]); - } - } - else //Old fips or OPAL release that doesn't support SMF - { - chipHomer = (HomerSection_t*)i_pImage; - - if( threadScopeReg ) - { - pThreadLocation = - &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_threadArea[0]); - } - else - { - pThreadLocation = - &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_coreArea[0]); - } - } - - if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) || - ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) ) - { - // table for given core id doesn't exit. It needs to be - // defined. - pSprEntryLocation = pThreadLocation; - } - else - { - // an SPR restore section for given core already exists - lookUpKey = genKeyForSprLookup( i_regId ); - l_rc = lookUpSprInImage( (uint32_t*)pThreadLocation, - lookUpKey, - threadScopeReg, - &pSprEntryLocation, - l_selfRestVer ); - } - - if( l_rc ) - { - MY_ERR("Invalid or corrupt SPR entry. CoreId 0x%08x threadId ", - "0x%08x regId 0x%08x lookUpKey 0x%08x pThreadLocation 0x%08x" - , coreId, threadId, i_regId, lookUpKey, pThreadLocation ); - break; - } - - if( ( P9_STOP_SPR_URMOR == i_regId ) && ( l_urmorFix ) ) - { - l_sprValue = i_regData - URMOR_CORRECTION; - } - else - { - l_sprValue = i_regData; - } - - l_rc = updateSprEntryInImage( (uint32_t*) pSprEntryLocation, - i_regId, - l_sprValue, - UPDATE_SPR_ENTRY ); - - if( l_rc ) - { - MY_ERR( " Failed to update the SPR entry of PIR 0x%08x reg" - "0x%08x", i_pir, i_regId ); - break; - } - - } - while(0); + MY_INF(">> p9_stop_save_cpureg" ); - MY_INF("<< p9_stop_save_cpureg" ); - return l_rc; + return proc_stop_save_cpureg( i_pImage, i_regId, i_regData, i_pir ); } //----------------------------------------------------------------------------- @@ -1003,103 +879,334 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, const ScomOperation_t i_operation, const ScomSection_t i_section ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - uint32_t entryLimit = 0; - uint8_t chipletId = 0; - uint32_t nopInst = 0; - uint32_t index = 0; - uint32_t imageVer = 0; - uint32_t entrySwzHeader = 0; - uint32_t l_maxScomRestoreEntry = 0; - ScomEntry_t* pScomEntry = NULL; - ScomEntry_t* pEntryLocation = NULL; - ScomEntry_t* pNopLocation = NULL; - ScomEntry_t* pEditScomHeader = NULL; - StopCacheSection_t* pStopCacheScomStart = NULL; - ScomEntry_t* pTableEndLocationtable = NULL; - uint32_t swizzleAddr; - uint64_t swizzleData; - uint32_t swizzleAttn; - uint32_t swizzleBlr = SWIZZLE_4_BYTE(BLR_INST); - bool cacheEntry = true; - MY_INF(">> p9_stop_save_scom"); - //Reads SGPE image version info from QPMR Header in HOMER - //For backward compatibility, for base version of SGPE Hcode, - //STOP API retains default behavior but adds version specific - //details in each entry in later versions. - imageVer = *(uint32_t*)((uint8_t*)i_pImage + QPMR_HOMER_OFFSET + QPMR_BUILD_VER_BYTE); - imageVer = SWIZZLE_4_BYTE(imageVer); - + return proc_stop_save_scom( i_pImage, i_scomAddress, + i_scomData, i_operation, i_section ); +} - do - { - chipletId = i_scomAddress >> 24; - chipletId = chipletId & 0x3F; +//----------------------------------------------------------------------------- - l_rc = validateScomImageInputs( i_pImage, i_scomAddress, chipletId, i_operation, i_section ); +/** + * @brief searches a self save entry of an SPR in self-save segment. + * @param[in] i_sprBitPos bit position associated with SPR in save mask vector. + * @param[in] l_pSprSaveStart start location of SPR save segment + * @param[in] i_searchLength length of SPR save segment + * @param[in] i_pSaveSprLoc start location of save entry for a given SPR. + * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. + */ +STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart, + uint32_t i_searchLength, uint32_t** i_pSaveSprLoc ) +{ + int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2); + uint32_t l_oriInst = getOriInstruction( 0, 0, i_sprBitPos ); + StopReturnCode_t l_rc = STOP_SAVE_FAIL; - if( l_rc ) + while( l_saveWordLength > 0 ) + { + if( l_oriInst == *l_pSprSaveStart ) { - MY_ERR( "invalid argument: aborting"); + *i_pSaveSprLoc = l_pSprSaveStart; + l_rc = STOP_SAVE_SUCCESS; break; } - if( chipletId >= CORE_CHIPLET_ID_MIN ) - { - // chiplet is core. So, let us find the start address of SCOM area - // pertaining to a core in STOP image. - l_maxScomRestoreEntry = - *(uint32_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + CPMR_MAX_SCOM_REST_PER_CORE_BYTE); - pScomEntry = CORE_ID_SCOM_START(i_pImage, chipletId ) - cacheEntry = false; + l_pSprSaveStart++; + l_saveWordLength--; + } - if( !l_maxScomRestoreEntry ) - { - //Old HB and new STOP API case. Retain legacy Number - l_maxScomRestoreEntry = SWIZZLE_4_BYTE(LEGACY_CORE_SCOM_SUPPORTED); - } - } - else - { - l_maxScomRestoreEntry = - *(uint32_t*)((uint8_t*)i_pImage + QPMR_HOMER_OFFSET + QPMR_QUAD_MAX_SCOM_ENTRY_BYTE); + return l_rc; +} - if( !l_maxScomRestoreEntry ) - { - // Incase of a bad HOMER header initialization, fall back on legacy number. - l_maxScomRestoreEntry = SWIZZLE_4_BYTE(LEGACY_QUAD_SCOM_SUPPORTED); - } - // chiplet is a cache. let us find start address of cache section - // associated with given chiplet. A cache section associated with - // given chiplet is split in to L2, L3 and EQ area. - pStopCacheScomStart = CACHE_SECTN_START(i_pImage, - chipletId); - } +//----------------------------------------------------------------------------- - l_maxScomRestoreEntry = SWIZZLE_4_BYTE(l_maxScomRestoreEntry); +/** + * @brief searches a self save entry of an SPR in self-save segment. + * @param[in] i_pSaveReg start of editable location of a SPR save entry. + * @param[in] i_sprNum Id of the SPR for which entry needs to be edited. + * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. + */ +STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - if(( !pStopCacheScomStart ) && ( !pScomEntry) ) + do + { + if( !i_pSaveReg ) { - //Error invalid pointer to SCOM entry in cache or core section - //of STOP image. - MY_ERR("invalid start location for chiplet %d", - chipletId ); + l_rc = STOP_SAVE_FAIL; + MY_ERR( "Failed to update self save area for SPR 0x%04x", i_sprNum ); break; } - switch( i_section ) + if( P9_STOP_SPR_MSR == i_sprNum ) { - case P9_STOP_SECTION_EQ_SCOM: - pScomEntry = pStopCacheScomStart->nonCacheArea; - entryLimit = MAX_EQ_SCOM_ENTRIES; - break; + *i_pSaveReg = getMfmsrInstruction( 1 ); + } + else + { + *i_pSaveReg = getMfsprInstruction( 1, i_sprNum ); + } - case P9_STOP_SECTION_L2: - pScomEntry = pStopCacheScomStart->l2CacheArea; - entryLimit = MAX_L2_SCOM_ENTRIES; - break; + i_pSaveReg++; + + *i_pSaveReg = getBranchLinkRegInstruction( ); + } + while(0); + + return l_rc; +} + +//----------------------------------------------------------------------------- + +StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ) +{ + MY_INF( ">> p9_stop_save_cpureg_control" ); + + return proc_stop_save_cpureg_control( i_pImage, i_pir, i_saveRegVector ); +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t p9_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +{ + MY_INF( ">> p9_stop_init_cpureg" ); + + return proc_stop_init_cpureg( i_pImage, i_corePos ); +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) +{ + MY_INF( ">> p9_stop_init_self_save" ); + + return proc_stop_init_self_save( i_pImage, i_corePos ); +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +{ + + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t* l_pRestoreStart = NULL; + void* l_pTempLoc = NULL; + SmfHomerSection_t* l_pHomer = NULL; + uint32_t l_threadPos = 0; + uint32_t l_lookUpKey = 0; + uint32_t l_sprIndex = 0; + uint8_t l_selfRestVer = 0; + + MY_INF( ">> proc_stop_init_cpureg" ); + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + if( i_corePos > MAX_CORE_ID_SUPPORTED ) + { + l_rc = STOP_SAVE_ARG_INVALID_CORE; + break; + } + + l_pHomer = ( SmfHomerSection_t * ) i_pImage; + l_selfRestVer = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); + + for( l_sprIndex = 0; l_sprIndex < MAX_SPR_SUPPORTED; l_sprIndex++ ) + { + //Check if a given SPR needs to be self-saved each time on STOP entry + + l_lookUpKey = genKeyForSprLookup( ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId ); + + if( g_sprRegister[l_sprIndex].iv_isThreadScope ) + { + for( l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; l_threadPos++ ) + { + l_pRestoreStart = + (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_threadRestoreArea[l_threadPos][0]; + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister[l_sprIndex].iv_isThreadScope, + &l_pTempLoc, + l_selfRestVer ); + + if( l_rc ) + { + MY_ERR( "Thread SPR lookup failed in p9_stop_init_cpureg SPR %d Core %d Thread %d Index %d", + g_sprRegister[l_sprIndex].iv_sprId, i_corePos, l_threadPos, l_sprIndex ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, + ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, + 0x00, + INIT_SPR_REGION ); + + if( l_rc ) + { + MY_ERR( "Thread SPR region init failed. Core %d SPR Id %d", + i_corePos, g_sprRegister[l_sprIndex].iv_sprId ); + break; + } + + }//end for thread + + if( l_rc ) + { + break; + } + + }//end if SPR threadscope + else + { + l_pRestoreStart = (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_coreRestoreArea[0]; + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister[l_sprIndex].iv_isThreadScope, + &l_pTempLoc, l_selfRestVer ); + + if( l_rc ) + { + MY_ERR( "Core SPR lookup failed in p9_stop_init_cpureg" ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, + ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, + 0x00, + INIT_SPR_REGION ); + + if( l_rc ) + { + MY_ERR( "Core SPR region init failed. Core %d SPR Id %d SPR Index %d", + i_corePos, g_sprRegister[l_sprIndex].iv_sprId, l_sprIndex ); + break; + } + + }// end else + + }// end for l_sprIndex + + } + while(0); + + MY_INF( "<< proc_stop_init_cpureg" ); + + return l_rc; +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const ScomOperation_t i_operation, + const ScomSection_t i_section ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t entryLimit = 0; + uint8_t chipletId = 0; + uint32_t nopInst = 0; + uint32_t index = 0; + uint32_t imageVer = 0; + uint32_t entrySwzHeader = 0; + uint32_t l_maxScomRestoreEntry = 0; + ScomEntry_t* pScomEntry = NULL; + ScomEntry_t* pEntryLocation = NULL; + ScomEntry_t* pNopLocation = NULL; + ScomEntry_t* pEditScomHeader = NULL; + StopCacheSection_t* pStopCacheScomStart = NULL; + ScomEntry_t* pTableEndLocationtable = NULL; + uint32_t swizzleAddr; + uint64_t swizzleData; + uint32_t swizzleAttn; + uint32_t swizzleBlr = SWIZZLE_4_BYTE(BLR_INST); + bool cacheEntry = true; + + MY_INF( ">> proc_stop_save_scom" ); + + //Reads SGPE image version info from QPMR Header in HOMER + //For backward compatibility, for base version of SGPE Hcode, + //STOP API retains default behavior but adds version specific + //details in each entry in later versions. + imageVer = *(uint32_t*)((uint8_t*)i_pImage + QPMR_HOMER_OFFSET + QPMR_BUILD_VER_BYTE); + imageVer = SWIZZLE_4_BYTE(imageVer); + + + do + { + chipletId = i_scomAddress >> 24; + chipletId = chipletId & 0x3F; + + l_rc = validateScomImageInputs( i_pImage, i_scomAddress, chipletId, i_operation, i_section ); + + if( l_rc ) + { + MY_ERR( "invalid argument: aborting"); + break; + } + + if( chipletId >= CORE_CHIPLET_ID_MIN ) + { + // chiplet is core. So, let us find the start address of SCOM area + // pertaining to a core in STOP image. + l_maxScomRestoreEntry = + *(uint32_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + CPMR_MAX_SCOM_REST_PER_CORE_BYTE); + pScomEntry = CORE_ID_SCOM_START(i_pImage, chipletId ) + cacheEntry = false; + + if( !l_maxScomRestoreEntry ) + { + //Old HB and new STOP API case. Retain legacy Number + l_maxScomRestoreEntry = SWIZZLE_4_BYTE(LEGACY_CORE_SCOM_SUPPORTED); + } + } + else + { + l_maxScomRestoreEntry = + *(uint32_t*)((uint8_t*)i_pImage + QPMR_HOMER_OFFSET + QPMR_QUAD_MAX_SCOM_ENTRY_BYTE); + + if( !l_maxScomRestoreEntry ) + { + // Incase of a bad HOMER header initialization, fall back on legacy number. + l_maxScomRestoreEntry = SWIZZLE_4_BYTE(LEGACY_QUAD_SCOM_SUPPORTED); + } + // chiplet is a cache. let us find start address of cache section + // associated with given chiplet. A cache section associated with + // given chiplet is split in to L2, L3 and EQ area. + pStopCacheScomStart = CACHE_SECTN_START(i_pImage, + chipletId); + } + + l_maxScomRestoreEntry = SWIZZLE_4_BYTE(l_maxScomRestoreEntry); + + if(( !pStopCacheScomStart ) && ( !pScomEntry) ) + { + //Error invalid pointer to SCOM entry in cache or core section + //of STOP image. + MY_ERR("invalid start location for chiplet %d", + chipletId ); + break; + } + + switch( i_section ) + { + case P9_STOP_SECTION_EQ_SCOM: + pScomEntry = pStopCacheScomStart->nonCacheArea; + entryLimit = MAX_EQ_SCOM_ENTRIES; + break; + + case P9_STOP_SECTION_L2: + pScomEntry = pStopCacheScomStart->l2CacheArea; + entryLimit = MAX_L2_SCOM_ENTRIES; + break; case P9_STOP_SECTION_L3: pScomEntry = pStopCacheScomStart->l3CacheArea; @@ -1274,131 +1381,60 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, if( NULL == pEntryLocation ) { editAppend = pTableEndLocationtable; - } - else - { - editAppend = pEntryLocation; - - if( P9_STOP_SCOM_OR_APPEND == i_operation ) - { - tempOperation = P9_STOP_SCOM_OR; - } - else - { - tempOperation = P9_STOP_SCOM_AND; - } - } - - l_rc = editScomEntry( swizzleAddr, - swizzleData, - editAppend, - tempOperation ); - - pEditScomHeader = editAppend; - } - break; - - default: - l_rc = STOP_SAVE_SCOM_INVALID_OPERATION; - break; - } - } - while(0); - - if( l_rc ) - { - MY_ERR("SCOM image operation 0x%08x failed for chiplet 0x%08x addr" - "0x%08x", i_operation, chipletId , - i_scomAddress ); - } - else - { - //Update SCOM Restore entry with version and memory layout - //info - updateEntryHeader( pEditScomHeader, imageVer, l_maxScomRestoreEntry ); - } - - MY_INF("<< p9_stop_save_scom"); - return l_rc; -} - -//----------------------------------------------------------------------------- - -/** - * @brief searches a self save entry of an SPR in self-save segment. - * @param[in] i_sprBitPos bit position associated with SPR in save mask vector. - * @param[in] l_pSprSaveStart start location of SPR save segment - * @param[in] i_searchLength length of SPR save segment - * @param[in] i_pSaveSprLoc start location of save entry for a given SPR. - * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. - */ -STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart, - uint32_t i_searchLength, uint32_t** i_pSaveSprLoc ) -{ - int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2); - uint32_t l_oriInst = getOriInstruction( 0, 0, i_sprBitPos ); - StopReturnCode_t l_rc = STOP_SAVE_FAIL; - - while( l_saveWordLength > 0 ) - { - if( l_oriInst == *l_pSprSaveStart ) - { - *i_pSaveSprLoc = l_pSprSaveStart; - l_rc = STOP_SAVE_SUCCESS; - break; - } - - l_pSprSaveStart++; - l_saveWordLength--; - } - - return l_rc; -} - -//----------------------------------------------------------------------------- - -/** - * @brief searches a self save entry of an SPR in self-save segment. - * @param[in] i_pSaveReg start of editable location of a SPR save entry. - * @param[in] i_sprNum Id of the SPR for which entry needs to be edited. - * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. - */ -STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) -{ - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - - do - { - if( !i_pSaveReg ) - { - l_rc = STOP_SAVE_FAIL; - MY_ERR( "Failed to update self save area for SPR 0x%04x", i_sprNum ); - break; - } + } + else + { + editAppend = pEntryLocation; - if( P9_STOP_SPR_MSR == i_sprNum ) - { - *i_pSaveReg = getMfmsrInstruction( 1 ); - } - else - { - *i_pSaveReg = getMfsprInstruction( 1, i_sprNum ); - } + if( P9_STOP_SCOM_OR_APPEND == i_operation ) + { + tempOperation = P9_STOP_SCOM_OR; + } + else + { + tempOperation = P9_STOP_SCOM_AND; + } + } - i_pSaveReg++; + l_rc = editScomEntry( swizzleAddr, + swizzleData, + editAppend, + tempOperation ); - *i_pSaveReg = getBranchLinkRegInstruction( ); + pEditScomHeader = editAppend; + } + break; + + default: + l_rc = STOP_SAVE_SCOM_INVALID_OPERATION; + break; + } } while(0); + if( l_rc ) + { + MY_ERR("SCOM image operation 0x%08x failed for chiplet 0x%08x addr" + "0x%08x", i_operation, chipletId , + i_scomAddress ); + } + else + { + //Update SCOM Restore entry with version and memory layout + //info + updateEntryHeader( pEditScomHeader, imageVer, l_maxScomRestoreEntry ); + } + + MY_INF( "<< proc_stop_save_scom" ); + return l_rc; } -//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------------------------------- -StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, - const uint64_t i_pir, - const uint32_t i_saveRegVector ) +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ) { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; uint32_t l_coreId = 0; @@ -1411,8 +1447,10 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, uint32_t* l_pRestoreStart = NULL; uint32_t* l_pSprSave = NULL; void* l_pTempLoc = NULL; + uint32_t * l_pTempWord = NULL; SmfHomerSection_t* l_pHomer = NULL; uint8_t l_selfRestVer = 0; + MY_INF(">> proc_stop_save_cpureg_control" ); do { @@ -1440,6 +1478,11 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, { l_sprPos = g_sprRegister[l_sprIndex].iv_saveMaskPos; + if( l_sprPos > MAX_SPR_BIT_POS ) + { + continue; + } + //Check if a given SPR needs to be self-saved each time on STOP entry if( i_saveRegVector & ( TEST_BIT_PATTERN >> l_sprPos ) ) @@ -1493,139 +1536,187 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, //update specific instructions of self save region to enable saving for SPR l_rc = updateSelfSaveEntry( l_pSprSave, g_sprRegister[l_sprIndex].iv_sprId ); + if( l_rc ) + { + MY_ERR( "Failed to update self save instructions for 0x%08x", + (uint32_t) g_sprRegister[l_sprIndex].iv_sprId ); + } + + if( l_pTempLoc ) + { + l_pTempWord = (uint32_t *)l_pTempLoc; + l_pTempWord++; + *l_pTempWord = getXorInstruction( 0, 0, 0 ); + } + }// end if( i_saveRegVector..) }// end for } while(0); + MY_INF("<< proc_stop_save_cpureg_control" ); + return l_rc; + } //----------------------------------------------------------------------------------------------------- -StopReturnCode_t p9_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - uint32_t* l_pRestoreStart = NULL; - void* l_pTempLoc = NULL; - SmfHomerSection_t* l_pHomer = NULL; - uint32_t l_threadPos = 0; - uint32_t l_lookUpKey = 0; - uint32_t l_sprIndex = 0; - uint8_t l_selfRestVer = 0; - MY_INF( ">> p9_stop_init_cpureg" ); + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; // procedure return code + HomerSection_t* chipHomer = NULL; + SmfHomerSection_t* smfChipHomer = NULL; + + MY_INF(">> proc_stop_save_cpureg" ); do { - if( !i_pImage ) + uint32_t threadId = 0; + uint32_t coreId = 0; + uint32_t lookUpKey = 0; + void* pSprEntryLocation = NULL; // an offset w.r.t. to start of image + void* pThreadLocation = NULL; + bool threadScopeReg = false; + uint8_t l_urmorFix = false; + uint64_t l_sprValue = 0; + uint8_t l_selfRestVer = 0; + + + l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); + + if( l_rc ) { - l_rc = STOP_SAVE_ARG_INVALID_IMG; + MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016llx", + i_pir); break; } - if( i_corePos > MAX_CORE_ID_SUPPORTED ) + MY_INF( " PIR 0x%016llx coreId %d threadid %d " + " registerId %d", i_pir, coreId, + threadId, i_regId ); + + // First of all let us validate all input arguments. + l_rc = validateSprImageInputs( i_pImage, + i_regId, + coreId, + &threadId, + &threadScopeReg ); + + if( l_rc ) { - l_rc = STOP_SAVE_ARG_INVALID_CORE; + // Error: bad argument traces out error code + MY_ERR("Bad input argument rc %d", l_rc ); + break; } - l_pHomer = ( SmfHomerSection_t * ) i_pImage; + l_urmorFix = *(uint8_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + CPMR_URMOR_FIX_BYTE); l_selfRestVer = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); - for( l_sprIndex = 0; l_sprIndex < MAX_SPR_SUPPORTED; l_sprIndex++ ) + if( l_selfRestVer ) { - //Check if a given SPR needs to be self-saved each time on STOP entry - - l_lookUpKey = genKeyForSprLookup( ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId ); + smfChipHomer = ( SmfHomerSection_t*)i_pImage; - if( g_sprRegister[l_sprIndex].iv_isThreadScope ) + if( threadScopeReg ) { - for( l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; l_threadPos++ ) - { - l_pRestoreStart = - (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_threadRestoreArea[l_threadPos][0]; - - l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, - g_sprRegister[l_sprIndex].iv_isThreadScope, - &l_pTempLoc, - l_selfRestVer ); - - if( l_rc ) - { - MY_ERR( "Thread SPR lookup failed in p9_stop_init_cpureg SPR %d Core %d Thread %d Index %d", - g_sprRegister[l_sprIndex].iv_sprId, i_corePos, l_threadPos, l_sprIndex ); - break; - } - - l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, - ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, - 0x00, - INIT_SPR_REGION ); - - if( l_rc ) - { - MY_ERR( "Thread SPR region init failed. Core %d SPR Id %d", - i_corePos, g_sprRegister[l_sprIndex].iv_sprId ); - break; - } - - }//end for thread - - if( l_rc ) - { - break; - } - - }//end if SPR threadscope + pThreadLocation = + &(smfChipHomer->iv_coreThreadRestore[coreId].iv_threadRestoreArea[threadId][0]); + } else { - l_pRestoreStart = (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_coreRestoreArea[0]; + pThreadLocation = + &(smfChipHomer->iv_coreThreadRestore[coreId].iv_coreRestoreArea[0]); + } + } + else //Old fips or OPAL release that doesn't support SMF + { + chipHomer = (HomerSection_t*)i_pImage; - l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, - g_sprRegister[l_sprIndex].iv_isThreadScope, - &l_pTempLoc, l_selfRestVer ); + if( threadScopeReg ) + { + pThreadLocation = + &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_threadArea[0]); + } + else + { + pThreadLocation = + &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_coreArea[0]); + } + } - if( l_rc ) - { - MY_ERR( "Core SPR lookup failed in p9_stop_init_cpureg" ); - break; - } + if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) || + ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) ) + { + // table for given core id doesn't exit. It needs to be + // defined. + pSprEntryLocation = pThreadLocation; + } + else + { + // an SPR restore section for given core already exists + lookUpKey = genKeyForSprLookup( i_regId ); + l_rc = lookUpSprInImage( (uint32_t*)pThreadLocation, + lookUpKey, + threadScopeReg, + &pSprEntryLocation, + l_selfRestVer ); + } - l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, - ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, - 0x00, - INIT_SPR_REGION ); + if( l_rc ) + { + MY_ERR("Invalid or corrupt SPR entry. CoreId 0x%08x threadId ", + "0x%08x regId 0x%08x lookUpKey 0x%08x pThreadLocation 0x%08x" + , coreId, threadId, i_regId, lookUpKey, pThreadLocation ); + break; + } - if( l_rc ) - { - MY_ERR( "Core SPR region init failed. Core %d SPR Id %d SPR Index %d", - i_corePos, g_sprRegister[l_sprIndex].iv_sprId, l_sprIndex ); - break; - } + if( ( P9_STOP_SPR_URMOR == i_regId ) && ( l_urmorFix ) ) + { + l_sprValue = i_regData - URMOR_CORRECTION; + } + else + { + l_sprValue = i_regData; + } - }// end else + l_rc = updateSprEntryInImage( (uint32_t*) pSprEntryLocation, + i_regId, + l_sprValue, + UPDATE_SPR_ENTRY ); - }// end for l_sprIndex + if( l_rc ) + { + MY_ERR( " Failed to update the SPR entry of PIR 0x%08x reg" + "0x%08x", i_pir, i_regId ); + break; + } } while(0); - MY_INF( "<< p9_stop_init_cpureg" ); + MY_INF("<< proc_stop_save_cpureg" ); + return l_rc; } //----------------------------------------------------------------------------------------------------- -StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) { + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; uint32_t* l_pSaveStart = NULL; SmfHomerSection_t * l_pHomer = NULL; uint32_t l_threadPos = 0; uint32_t l_sprBitPos = 0; uint32_t l_sprIndexAdj = 0; - MY_INF( ">> p9_stop_init_self_save" ); + + MY_INF(">> proc_stop_init_self_save" ); do { @@ -1732,7 +1823,8 @@ StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i } while(0); - MY_INF( "<< p9_stop_init_self_save" ); + MY_INF("<< proc_stop_init_self_save" ); + return l_rc; } diff --git a/libpore/p9_stop_api.H b/libpore/p9_stop_api.H index 17caedb3..3f6420ff 100644 --- a/libpore/p9_stop_api.H +++ b/libpore/p9_stop_api.H @@ -70,6 +70,26 @@ typedef enum P9_STOP_SPR_PMCR = 884, // core register P9_STOP_SPR_HID = 1008, // core register P9_STOP_SPR_MSR = 2000, // thread register + + //enum members which are project agnostic + PROC_STOP_SPR_DAWR = 180, // thread register + PROC_STOP_SPR_CIABR = 187, // thread register + PROC_STOP_SPR_DAWRX = 188, // thread register + PROC_STOP_SPR_HSPRG0 = 304, // thread register + PROC_STOP_SPR_HRMOR = 313, // core register + PROC_STOP_SPR_LPCR = 318, // thread register + PROC_STOP_SPR_HMEER = 337, // core register + PROC_STOP_SPR_PTCR = 464, // core register + PROC_STOP_SPR_USPRG0 = 496, // thread register + PROC_STOP_SPR_USPRG1 = 497, // thread register + PROC_STOP_SPR_URMOR = 505, // core register + PROC_STOP_SPR_SMFCTRL = 511, // thread register + PROC_STOP_SPR_LDBAR = 850, // thread register + PROC_STOP_SPR_PSSCR = 855, // thread register + PROC_STOP_SPR_PMCR = 884, // core register + PROC_STOP_SPR_HID = 1008, // core register + PROC_STOP_SPR_MSR = 2000, // thread register + } CpuReg_t; /** @@ -110,7 +130,20 @@ typedef enum P9_STOP_SCOM_RESET = 6, P9_STOP_SCOM_OR_APPEND = 7, P9_STOP_SCOM_AND_APPEND = 8, - P9_STOP_SCOM_OP_MAX = 9 + P9_STOP_SCOM_OP_MAX = 9, + + //enum members which are project agnostic + PROC_STOP_SCOM_OP_MIN = 0, + PROC_STOP_SCOM_APPEND = 1, + PROC_STOP_SCOM_REPLACE = 2, + PROC_STOP_SCOM_OR = 3, + PROC_STOP_SCOM_AND = 4, + PROC_STOP_SCOM_NOOP = 5, + PROC_STOP_SCOM_RESET = 6, + PROC_STOP_SCOM_OR_APPEND = 7, + PROC_STOP_SCOM_AND_APPEND = 8, + PROC_STOP_SCOM_OP_MAX = 9, + } ScomOperation_t; /** @@ -123,7 +156,15 @@ typedef enum P9_STOP_SECTION_EQ_SCOM = 2, P9_STOP_SECTION_L2 = 3, P9_STOP_SECTION_L3 = 4, - P9_STOP_SECTION_MAX = 5 + P9_STOP_SECTION_MAX = 5, + + //enum members which are project agnostic + PROC_STOP_SECTION_MIN = 0, + PROC_STOP_SECTION_CORE_SCOM = 1, + PROC_STOP_SECTION_EQ_SCOM = 2, + PROC_STOP_SECTION_L2 = 3, + PROC_STOP_SECTION_L3 = 4, + PROC_STOP_SECTION_MAX = 5, } ScomSection_t; /** @@ -148,7 +189,6 @@ typedef enum BIT_POS_LPCR = 5, BIT_POS_PSSCR = 6, BIT_POS_MSR = 7, - BIT_POS_HRMOR = 20, BIT_POS_HID = 21, BIT_POS_HMEER = 22, BIT_POS_PMCR = 23, @@ -156,7 +196,6 @@ typedef enum BIT_POS_SMFCTRL = 28, BIT_POS_USPRG0 = 29, BIT_POS_USPRG1 = 30, - BIT_POS_URMOR = 31, } SprBitPositionList_t; @@ -229,13 +268,79 @@ p9_stop_save_cpureg_control( void* i_pImage, const uint64_t i_pir, * @brief initializes self-save region with specific instruction. * @param[in] i_pImage start address of homer image of P9 chip. * @param[in] i_corePos physical core's relative position within processor chip. - * @return STOP_SAVE_SUCCESS SUCCESS if self-save is initialized successfully, + * @return STOP_SAVE_SUCCESS if self-save is initialized successfully, * error code otherwise. * @note API is intended only for use case of HOMER build. There is no explicit * effort to support any other use case. */ StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); +/** + * @brief creates SCOM restore entry for a given scom adress in HOMER. + * @param i_pImage points to start address of HOMER image. + * @param i_scomAddress address associated with SCOM restore entry. + * @param i_scomData data associated with SCOM restore entry. + * @param i_operation operation type requested for API. + * @param i_section section of HOMER in which restore entry needs to be created. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for creating SCOM restore entry in HOMER. It is agnostic to + * generation of POWER processor. + */ + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const ScomOperation_t i_operation, + const ScomSection_t i_section ); + +/** + * @brief initializes self save restore region of HOMER. + * @param[in] i_pImage points to base of HOMER image. + * @param[in] i_corePos position of the physical core. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for initializing self restore region in HOMER. It is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ); + +/** + * @brief enables self save for a given set of SPRs + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_pir PIR value associated with core and thread. + * @param[in] i_saveRegVector bit vector representing the SPRs that needs to be self saved. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ); + +/** + * @brief creates an SPR restore entry in HOMER + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_pir PIR value associated with core and thread. + * @param[in] i_saveRegVector bit vector representing the SPRs that needs to be self saved. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ); + +/** + * @brief initializes self-save region with specific instruction. + * @param[in] i_pImage start address of homer image. + * @param[in] i_corePos physical core's relative position within processor chip. + * @return STOP_SAVE_SUCCESS if self-save is initialized successfully, + * error code otherwise. + * @note API is project agnostic and is intended only for use case of HOMER build. + * There is no explicit effort to support any other use case. + */ +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); + #ifdef __cplusplus } // extern "C" }; // namespace stopImageSection ends diff --git a/libpore/p9_stop_data_struct.H b/libpore/p9_stop_data_struct.H index 1e9721e0..4e73aab5 100644 --- a/libpore/p9_stop_data_struct.H +++ b/libpore/p9_stop_data_struct.H @@ -67,9 +67,9 @@ enum SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), MAX_THREAD_LEVEL_SPRS = 11, MAX_CORE_LEVEL_SPRS = 6, - MAX_SPR_BIT_POS = 31, + MAX_SPR_BIT_POS = 30, SPR_BIT_POS_8 = 8, - SPR_BIT_POS_19 = 19, + SPR_BIT_POS_20 = 20, SPR_BIT_POS_25 = 25, SPR_BIT_POS_27 = 27, }; diff --git a/libpore/p9_stop_util.H b/libpore/p9_stop_util.H index 3266fdef..79b4e959 100644 --- a/libpore/p9_stop_util.H +++ b/libpore/p9_stop_util.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -95,7 +95,10 @@ typedef struct uint64_t cpmrMagicWord; uint32_t buildDate; uint32_t version; - uint8_t reserve1[7]; + uint8_t reserve1[4]; + uint8_t selfRestoreVer; + uint8_t stopApiVer; + uint8_t urmorFix; uint8_t fusedModeStatus; uint32_t cmeImgOffset; uint32_t cmeImgLength; From patchwork Fri Jan 10 11:50:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1221013 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vLvp31jlz9sR1 for ; Fri, 10 Jan 2020 22:52:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47vLvp1x5nzDqdb for ; Fri, 10 Jan 2020 22:52:54 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47vLsc6VCLzDqdW for ; Fri, 10 Jan 2020 22:51:00 +1100 (AEDT) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00ABlwcs016454 for ; Fri, 10 Jan 2020 06:50:57 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2xe0smax1x-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 10 Jan 2020 06:50:57 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 10 Jan 2020 11:50:55 -0000 Received: from b06cxnps4076.portsmouth.uk.ibm.com (9.149.109.198) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 10 Jan 2020 11:50:53 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00ABonF049283220 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 10 Jan 2020 11:50:49 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B4173AE065; Fri, 10 Jan 2020 11:50:49 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3C3EDAE045; Fri, 10 Jan 2020 11:50:48 +0000 (GMT) Received: from pratiks-thinkpad.in.ibm.com (unknown [9.124.31.88]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 10 Jan 2020 11:50:48 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, oohall@gmail.com, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com, psampat@linux.ibm.com Date: Fri, 10 Jan 2020 17:20:41 +0530 X-Mailer: git-send-email 2.24.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20011011-4275-0000-0000-000003966C68 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011011-4276-0000-0000-000038AA5E76 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-10_01:2020-01-10, 2020-01-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001100101 Subject: [Skiboot] [RESEND PATCH v2 2/4] Self save API integration X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The commit makes the self save API available outside the firmware by defining an OPAL wrapper. This wrapper has a similar interface to that of self restore and expects the cpu pir, SPR number, minus the value of that SPR to be passed in its paramters and returns OPAL_SUCCESS on success. Signed-off-by: Pratik Rajesh Sampat --- doc/opal-api/opal-slw-self-save-reg-176.rst | 33 ++++++++ hw/slw.c | 89 +++++++++++++++++++++ include/opal-api.h | 3 +- include/p9_stop_api.H | 17 ++++ include/skiboot.h | 3 + 5 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 doc/opal-api/opal-slw-self-save-reg-176.rst diff --git a/doc/opal-api/opal-slw-self-save-reg-176.rst b/doc/opal-api/opal-slw-self-save-reg-176.rst new file mode 100644 index 00000000..6a4e1a5f --- /dev/null +++ b/doc/opal-api/opal-slw-self-save-reg-176.rst @@ -0,0 +1,33 @@ +.. OPAL_SLW_SELF_SAVE_REG: + +OPAL_SLW_SELF_SAVE_REG +====================== + +.. code-block:: c + + #define OPAL_SLW_SELF_SAVE_REG 176 + + int64_t opal_slw_self_save_reg(uint64_t cpu_pir, uint64_t sprn); + +:ref:`OPAL_SLW_SELF_SAVE_REG` is used to inform low-level firmware to save +the current contents of the SPR before entering a state of loss and +also restore the content back on waking up from a deep stop state. + +Parameters +---------- + +``uint64_t cpu_pir`` + This parameter specifies the pir of the cpu for which the call is being made. +``uint64_t sprn`` + This parameter specifies the spr number as mentioned in p9_stop_api.H for + Power9 and p8_pore_table_gen_api.H for Power8. + +Returns +------- + +:ref:`OPAL_UNSUPPORTED` + If spr restore is not supported by pore engine. +:ref:`OPAL_PARAMETER` + Invalid handle for the pir/chip +:ref:`OPAL_SUCCESS` + On success \ No newline at end of file diff --git a/hw/slw.c b/hw/slw.c index 566a1128..14dbce47 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -35,6 +35,43 @@ static bool slw_current_le = false; enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; +/** + * The struct and SPR list is partially consistent with libpore/p9_stop_api.c + */ +/** + * @brief summarizes attributes associated with a SPR register. + */ +typedef struct +{ + uint32_t iv_sprId; + bool iv_isThreadScope; + uint32_t iv_saveMaskPos; + +} StopSprReg_t; + +/** + * @brief a true in the table below means register is of scope thread + * whereas a false meanse register is of scope core. + * The number is the bit position on a uint32_t mask + */ + +static const StopSprReg_t g_sprRegister[] = +{ + { P9_STOP_SPR_DAWR, true, 1 }, + { P9_STOP_SPR_HSPRG0, true, 3 }, + { P9_STOP_SPR_LDBAR, true, 4, }, + { P9_STOP_SPR_LPCR, true, 5 }, + { P9_STOP_SPR_PSSCR, true, 6 }, + { P9_STOP_SPR_MSR, true, 7 }, + { P9_STOP_SPR_HRMOR, false, 255 }, + { P9_STOP_SPR_HID, false, 21 }, + { P9_STOP_SPR_HMEER, false, 22 }, + { P9_STOP_SPR_PMCR, false, 23 }, + { P9_STOP_SPR_PTCR, false, 24 }, +}; + +static const uint32_t MAX_SPR_SUPPORTED = ARRAY_SIZE(g_sprRegister); + DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, OPAL_NA); @@ -1446,6 +1483,58 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) opal_call(OPAL_SLW_SET_REG, opal_slw_set_reg, 3); +int64_t opal_slw_self_save_reg(uint64_t cpu_pir, uint64_t sprn) +{ + struct cpu_thread * c = find_cpu_by_pir(cpu_pir); + struct proc_chip * chip; + int rc; + int index; + uint32_t save_reg_vector = 0; + + if (!c) { + prlog(PR_DEBUG, "SLW: Unknown thread with pir %x\n", + (u32) cpu_pir); + return OPAL_PARAMETER; + } + + chip = get_chip(c->chip_id); + if (!chip) { + prlog(PR_DEBUG, "SLW: Unknown chip for thread with pir %x\n", + (u32) cpu_pir); + return OPAL_PARAMETER; + } + if (proc_gen != proc_gen_p9 || !has_deep_states) { + prlog(PR_DEBUG, "SLW: Does not support deep states\n"); + return OPAL_UNSUPPORTED; + } + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: wakeup_engine in bad state=%d chip=%x\n", + wakeup_engine_state, chip->id); + return OPAL_INTERNAL_ERROR; + } + for (index = 0; index < MAX_SPR_SUPPORTED; ++index) { + if (sprn == (CpuReg_t) g_sprRegister[index].iv_sprId) { + save_reg_vector = PPC_BIT32( + g_sprRegister[index].iv_saveMaskPos); + break; + } + } + if (save_reg_vector == 0) + return OPAL_INTERNAL_ERROR; + rc = p9_stop_save_cpureg_control((void *) chip->homer_base, + cpu_pir, save_reg_vector); + + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to save vector %x for CPU %x\n", + save_reg_vector, c->pir); + return OPAL_INTERNAL_ERROR; + } + return OPAL_SUCCESS; +} +opal_call(OPAL_SLW_SELF_SAVE_REG, opal_slw_self_save_reg, 2); + void slw_init(void) { struct proc_chip *chip; diff --git a/include/opal-api.h b/include/opal-api.h index d92ecf54..af2c2476 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -227,7 +227,8 @@ #define OPAL_SECVAR_ENQUEUE_UPDATE 178 #define OPAL_PHB_SET_OPTION 179 #define OPAL_PHB_GET_OPTION 180 -#define OPAL_LAST 180 +#define OPAL_SLW_SELF_SAVE_REG 181 +#define OPAL_LAST 181 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ diff --git a/include/p9_stop_api.H b/include/p9_stop_api.H index 9d3bc1e5..c304f70f 100644 --- a/include/p9_stop_api.H +++ b/include/p9_stop_api.H @@ -34,6 +34,8 @@ /// /// @file p9_stop_api.H /// @brief describes STOP API which create/manipulate STOP image. +/// This header need not be consistent, however is a subset of the +/// libpore/p9_stop_api.H counterpart /// // *HWP HW Owner : Greg Still // *HWP FW Owner : Prem Shanker Jha @@ -58,6 +60,7 @@ typedef enum P9_STOP_SPR_HRMOR = 313, // core register P9_STOP_SPR_LPCR = 318, // thread register P9_STOP_SPR_HMEER = 337, // core register + P9_STOP_SPR_PTCR = 464, // core register P9_STOP_SPR_LDBAR = 850, // thread register P9_STOP_SPR_PSSCR = 855, // thread register P9_STOP_SPR_PMCR = 884, // core register @@ -230,6 +233,20 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, const ScomOperation_t i_operation, const ScomSection_t i_section ); +/** + * @brief Facilitates self save and restore of a list of SPRs of a thread. + * @param[in] i_pImage points to the start of HOMER image of P9 chip. + * @param[in] i_pir PIR associated with thread + * @param[in] i_saveRegVector bit vector representing SPRs that needs to be restored. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note SPR save vector is a bit vector. For each SPR supported, + * there is an associated bit position in the bit vector.Refer + * to definition of SprBitPositionList_t to determine bit position + * associated with a particular SPR. + */ +StopReturnCode_t +p9_stop_save_cpureg_control( void* i_pImage, const uint64_t i_pir, + const uint32_t i_saveRegVector ); #ifdef __cplusplus } // extern "C" }; // namespace stopImageSection ends diff --git a/include/skiboot.h b/include/skiboot.h index e9d57dec..1ed8464e 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -306,6 +306,9 @@ extern void nx_p9_rng_late_init(void); /* SLW reinit function for switching core settings */ extern int64_t slw_reinit(uint64_t flags); +/* Self save SPR before entering the stop state */ +extern int64_t opal_slw_self_save_reg(uint64_t cpu_pir, uint64_t sprn); + /* Patch SPR in SLW image */ extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); From patchwork Fri Jan 10 11:50:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1221012 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vLvS6vxtz9sR1 for ; Fri, 10 Jan 2020 22:52:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47vLvS3hZbzDqfH for ; Fri, 10 Jan 2020 22:52:36 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47vLsc2QBGzDqdS for ; Fri, 10 Jan 2020 22:50:59 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00ABluAU006880 for ; Fri, 10 Jan 2020 06:50:56 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xereh0k7s-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 10 Jan 2020 06:50:56 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 10 Jan 2020 11:50:54 -0000 Received: from b06avi18626390.portsmouth.uk.ibm.com (9.149.26.192) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 10 Jan 2020 11:50:54 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00ABo3jl39911910 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 10 Jan 2020 11:50:03 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 87846AE051; Fri, 10 Jan 2020 11:50:51 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 106B1AE04D; Fri, 10 Jan 2020 11:50:50 +0000 (GMT) Received: from pratiks-thinkpad.in.ibm.com (unknown [9.124.31.88]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 10 Jan 2020 11:50:49 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, oohall@gmail.com, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com, psampat@linux.ibm.com Date: Fri, 10 Jan 2020 17:20:42 +0530 X-Mailer: git-send-email 2.24.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20011011-4275-0000-0000-000003966C69 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011011-4276-0000-0000-000038AA5E77 Message-Id: <0847fe000c57a307940ef8db5c04f6107a8f82f7.1578655107.git.psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-10_01:2020-01-10, 2020-01-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=2 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001100101 Subject: [Skiboot] [RESEND PATCH v2 3/4] Advertise the self-save and self-restore attributes in the device tree X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Support for self save and self restore interface is advertised in the device tree, along with the list of SPRs it supports for each. The Special Purpose Register identification is encoded in a 2048 bitmask structure, where each bit signifies the identification key of that SPR which is consistent with that of the POWER architecture set for that register. Signed-off-by: Pratik Rajesh Sampat --- hw/slw.c | 82 +++++++++++++++++++++++++++++++++ include/skiboot.h | 1 + libpore/p8_pore_table_gen_api.H | 1 + 3 files changed, 84 insertions(+) diff --git a/hw/slw.c b/hw/slw.c index 14dbce47..ebb70729 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -23,12 +23,15 @@ #include #include #include +#include #include #include #include static uint32_t slw_saved_reset[0x100]; +#define MAX_RESET_PATCH_SIZE 64 +#define SPR_BITMAP_LENGTH 2048 static bool slw_current_le = false; @@ -750,6 +753,84 @@ static void slw_late_init_p9(struct proc_chip *chip) } } +/* Add device tree properties to determine self-save | restore */ +void add_cpu_self_save_properties() +{ + int i; + struct dt_node *self_restore, *self_save, *power_mgt; + bitmap_t *self_restore_map, *self_save_map; + + const uint64_t self_restore_regs[] = { + P8_SPR_HRMOR, + P8_SPR_HMEER, + P8_SPR_PMICR, + P8_SPR_PMCR, + P8_SPR_HID0, + P8_SPR_HID1, + P8_SPR_HID4, + P8_SPR_HID5, + P8_SPR_HSPRG0, + P8_SPR_LPCR, + P8_SPR_PSSCR, + P8_MSR_MSR + }; + + const uint64_t self_save_regs[] = { + P9_STOP_SPR_DAWR, + P9_STOP_SPR_HSPRG0, + P9_STOP_SPR_LDBAR, + P9_STOP_SPR_LPCR, + P9_STOP_SPR_PSSCR, + P9_STOP_SPR_MSR, + P9_STOP_SPR_HRMOR, + P9_STOP_SPR_HMEER, + P9_STOP_SPR_PMCR, + P9_STOP_SPR_PTCR + }; + + self_save_map = zalloc(BITMAP_BYTES(SPR_BITMAP_LENGTH)); + self_restore_map = zalloc(BITMAP_BYTES(SPR_BITMAP_LENGTH)); + + for (i = 0; i < ARRAY_SIZE(self_save_regs); i++) + bitmap_set_bit(*self_save_map, self_save_regs[i]); + + for (i = 0; i < ARRAY_SIZE(self_restore_regs); i++) + bitmap_set_bit(*self_restore_map, self_restore_regs[i]); + + power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt"); + if (!power_mgt) { + prerror("OCC: dt node /ibm,opal/power-mgt not found\n"); + goto bail; + } + + self_restore = dt_new(power_mgt, "self-restore"); + if (!self_restore) { + prerror("OCC: Failed to create self restore node"); + goto bail; + } + dt_add_property_string(self_restore, "status", "enabled"); + + dt_add_property(self_restore, "sprn-bitmask", *self_restore_map, + SPR_BITMAP_LENGTH / 8); + + self_save = dt_new(power_mgt, "self-save"); + if (!self_save) { + prerror("OCC: Failed to create self save node"); + goto bail; + } + if (proc_gen == proc_gen_p9) { + dt_add_property_string(self_save, "status", "enabled"); + + dt_add_property(self_save, "sprn-bitmask", *self_save_map, + SPR_BITMAP_LENGTH / 8); + } else { + dt_add_property_string(self_save, "status", "disabled"); + } +bail: + free(self_save_map); + free(self_restore_map); +} + /* Add device tree properties to describe idle states */ void add_cpu_idle_state_properties(void) { @@ -1563,4 +1644,5 @@ void slw_init(void) } } add_cpu_idle_state_properties(); + add_cpu_self_save_properties(); } diff --git a/include/skiboot.h b/include/skiboot.h index 1ed8464e..43ee9c75 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -209,6 +209,7 @@ extern void early_uart_init(void); extern void homer_init(void); extern void slw_init(void); extern void add_cpu_idle_state_properties(void); +extern void add_cpu_self_save_properties(void); extern void lpc_rtc_init(void); /* flash support */ diff --git a/libpore/p8_pore_table_gen_api.H b/libpore/p8_pore_table_gen_api.H index 63081ca5..d72fee90 100644 --- a/libpore/p8_pore_table_gen_api.H +++ b/libpore/p8_pore_table_gen_api.H @@ -233,6 +233,7 @@ enum { P8_SPR_HRMOR = 313, P8_SPR_HMEER = 337, P8_SPR_PMICR = 852, + P8_SPR_PSSCR = 855, P8_SPR_PMCR = 884, P8_SPR_HID0 = 1008, P8_SPR_HID1 = 1009, From patchwork Fri Jan 10 11:50:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1221014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vLwD145nz9sR1 for ; Fri, 10 Jan 2020 22:53:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47vLwC6sNfzDqdj for ; Fri, 10 Jan 2020 22:53:15 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47vLsh6XX0zDqdS for ; Fri, 10 Jan 2020 22:51:04 +1100 (AEDT) Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00ABlnWV052908 for ; Fri, 10 Jan 2020 06:51:02 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xee3ercum-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 10 Jan 2020 06:51:02 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 10 Jan 2020 11:50:59 -0000 Received: from b06cxnps4074.portsmouth.uk.ibm.com (9.149.109.196) by e06smtp04.uk.ibm.com (192.168.101.134) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 10 Jan 2020 11:50:56 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 00ABorCP55705756 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 10 Jan 2020 11:50:53 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 524E5AE04D; Fri, 10 Jan 2020 11:50:53 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF31CAE055; Fri, 10 Jan 2020 11:50:51 +0000 (GMT) Received: from pratiks-thinkpad.in.ibm.com (unknown [9.124.31.88]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 10 Jan 2020 11:50:51 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, oohall@gmail.com, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com, psampat@linux.ibm.com Date: Fri, 10 Jan 2020 17:20:43 +0530 X-Mailer: git-send-email 2.24.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20011011-0016-0000-0000-000002DC35F9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20011011-0017-0000-0000-0000333EB896 Message-Id: <20d5bf7cb26aac139de740f2d8698e9eb89638ec.1578655107.git.psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-10_01:2020-01-10, 2020-01-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001100101 Subject: [Skiboot] [RESEND PATCH v2 4/4] API to verify the STOP API and image compatibility X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Prem Shanker Jha Commit defines a new API primarily intended for OPAL to determine cpu register save API's compatibility with HOMER layout and self save restore. It can help OPAL determine if version of API integrated with OPAL is different from hostboot. This is used in the context of identifying support for self save in the firmware. In the case the version of the firmware is older then we simply cut support for the feature in the device tree rather than catching the failure when the call is made. Change-Id: Ic0de45a336cfb8b6b6096a10ac1cd3ffbaa44fc0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77612 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Gregory S Still Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77614 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell Signed-off-by: Pratik Rajesh Sampat Co-authored-by: Prem Shanker Jha Co-authored-by: Pratik Rajesh Sampat --- hw/slw.c | 22 ++++++++- include/p9_stop_api.H | 26 ++++++++++ libpore/p9_cpu_reg_restore_instruction.H | 5 +- libpore/p9_hcd_memmap_base.H | 7 +++ libpore/p9_stop_api.C | 60 +++++++++++++++++++++++- libpore/p9_stop_api.H | 26 +++++++++- 6 files changed, 140 insertions(+), 6 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index ebb70729..38b8be1b 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -756,9 +756,12 @@ static void slw_late_init_p9(struct proc_chip *chip) /* Add device tree properties to determine self-save | restore */ void add_cpu_self_save_properties() { - int i; + int i, rc; + bool self_save_supported = true; struct dt_node *self_restore, *self_save, *power_mgt; bitmap_t *self_restore_map, *self_save_map; + uint64_t compVector = -1; + struct proc_chip *chip; const uint64_t self_restore_regs[] = { P8_SPR_HRMOR, @@ -791,6 +794,21 @@ void add_cpu_self_save_properties() self_save_map = zalloc(BITMAP_BYTES(SPR_BITMAP_LENGTH)); self_restore_map = zalloc(BITMAP_BYTES(SPR_BITMAP_LENGTH)); + chip = next_chip(NULL); + assert(chip); + rc = proc_stop_api_discover_capability((void *) chip->homer_base, + &compVector); + if (rc == STOP_SAVE_ARG_INVALID_IMG) { + prlog(PR_DEBUG, "HOMER BASE INVALID\n"); + goto bail; + } else if (rc == STOP_SAVE_API_IMG_INCOMPATIBLE) { + prlog(PR_DEBUG, "STOP API running incompatible versions\n"); + if ((compVector & SELF_RESTORE_VER_MISMATCH) == 0) { + prlog(PR_DEBUG, "Self-save API unsupported\n"); + self_save_supported = false; + } + } + for (i = 0; i < ARRAY_SIZE(self_save_regs); i++) bitmap_set_bit(*self_save_map, self_save_regs[i]); @@ -818,7 +836,7 @@ void add_cpu_self_save_properties() prerror("OCC: Failed to create self save node"); goto bail; } - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p9 && self_save_supported) { dt_add_property_string(self_save, "status", "enabled"); dt_add_property(self_save, "sprn-bitmask", *self_save_map, diff --git a/include/p9_stop_api.H b/include/p9_stop_api.H index c304f70f..09ce3dc1 100644 --- a/include/p9_stop_api.H +++ b/include/p9_stop_api.H @@ -110,6 +110,7 @@ typedef enum STOP_SAVE_FAIL = 14, // for internal failure within firmware. STOP_SAVE_SPR_ENTRY_MISSING = 15, STOP_SAVE_SPR_BIT_POS_RESERVE = 16, + STOP_SAVE_API_IMG_INCOMPATIBLE = 18, } StopReturnCode_t; /** @@ -164,6 +165,14 @@ typedef enum } ScomSection_t; +/** + * @brief versions pertaining relvant to STOP API. + */ +typedef enum +{ + STOP_API_VER = 0x00, + STOP_API_VER_CONTROL = 0x02, +} VersionList_t; /** @@ -195,6 +204,14 @@ typedef enum BIT_POS_USPRG1 = 30, } SprBitPositionList_t; +typedef enum +{ + SMF_SUPPORT_MISSING_IN_HOMER = 0x01, + SELF_SUPPORT_MISSING_FOR_LE_HYP = 0x02, + IPL_RUNTIME_CPU_SAVE_VER_MISMATCH = 0x04, + SELF_RESTORE_VER_MISMATCH = 0x08, +} VersionIncompList_t; + #ifdef __cplusplus extern "C" { #endif @@ -247,6 +264,15 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, const uint64_t i_pir, const uint32_t i_saveRegVector ); + +/** + * @brief verifies if API is compatible of current HOMER image. + * @param[in] i_pImage points to the start of HOMER image of P9 chip. + * @param[out] o_inCompVector list of incompatibilities found. + * @return STOP_SAVE_SUCCESS if if API succeeds, error code otherwise. + */ +StopReturnCode_t proc_stop_api_discover_capability( void* const i_pImage, uint64_t* o_inCompVector ); + #ifdef __cplusplus } // extern "C" }; // namespace stopImageSection ends diff --git a/libpore/p9_cpu_reg_restore_instruction.H b/libpore/p9_cpu_reg_restore_instruction.H index 27603b23..b92d439b 100644 --- a/libpore/p9_cpu_reg_restore_instruction.H +++ b/libpore/p9_cpu_reg_restore_instruction.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -76,7 +76,8 @@ enum SKIP_SPR_REST_INST = 0x4800001c, //b . +0x01c MFLR_R30 = 0x7fc802a6, SKIP_SPR_SELF_SAVE = 0x3bff0020, //addi r31 r31, 0x20 - MTLR_INST = 0x7fc803a6 //mtlr r30 + MTLR_INST = 0x7fc803a6, //mtlr r30 + BRANCH_BE_INST = 0x48000020, }; #ifdef __cplusplus diff --git a/libpore/p9_hcd_memmap_base.H b/libpore/p9_hcd_memmap_base.H index 000fafef..ddb56728 100644 --- a/libpore/p9_hcd_memmap_base.H +++ b/libpore/p9_hcd_memmap_base.H @@ -444,6 +444,13 @@ HCD_CONST(CME_QUAD_PSTATE_SIZE, HALF_KB) HCD_CONST(CME_REGION_SIZE, (64 * ONE_KB)) + +// HOMER compatibility + +HCD_CONST(STOP_API_CPU_SAVE_VER, 0x02) +HCD_CONST(SELF_SAVE_RESTORE_VER, 0x02) +HCD_CONST(SMF_SUPPORT_SIGNATURE_OFFSET, 0x1300) +HCD_CONST(SMF_SELF_SIGNATURE, (0x5f534d46)) // Debug HCD_CONST(CPMR_TRACE_REGION_OFFSET, (512 * ONE_KB)) diff --git a/libpore/p9_stop_api.C b/libpore/p9_stop_api.C index 2d9bb549..74341cff 100644 --- a/libpore/p9_stop_api.C +++ b/libpore/p9_stop_api.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1828,6 +1828,64 @@ StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t return l_rc; } +StopReturnCode_t proc_stop_api_discover_capability( void* const i_pImage, uint64_t * o_inCompVector ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint64_t l_incompVector = 0; + uint32_t l_tempWord = 0; + *o_inCompVector = 0; + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + l_tempWord = + *(uint32_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + SMF_SUPPORT_SIGNATURE_OFFSET); + + if( l_tempWord != SWIZZLE_4_BYTE(SMF_SELF_SIGNATURE) ) + { + l_incompVector |= SMF_SUPPORT_MISSING_IN_HOMER; + } + + l_tempWord = *(uint32_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_HEADER_SIZE ); + + if( l_tempWord != SWIZZLE_4_BYTE(BRANCH_BE_INST) ) + { + l_incompVector |= SELF_SUPPORT_MISSING_FOR_LE_HYP; + } + + l_tempWord = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); + + prlog(PR_EMERG, "SLW: self save ltemp: 0x%x\n", l_tempWord); + if( l_tempWord < SELF_SAVE_RESTORE_VER ) + { + l_incompVector |= SELF_RESTORE_VER_MISMATCH; + } + + l_tempWord = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_STOP_API_VER_BYTE ); + + if( l_tempWord < STOP_API_CPU_SAVE_VER ) + { + l_incompVector |= IPL_RUNTIME_CPU_SAVE_VER_MISMATCH; + } + + prlog(PR_EMERG, "SLW: Comp: 0x%llx\n", l_incompVector); + *o_inCompVector = l_incompVector; + + if( l_incompVector ) + { + l_rc = STOP_SAVE_API_IMG_INCOMPATIBLE; + } + + }while(0); + + return l_rc; +} + #ifdef __cplusplus } //namespace stopImageSection ends diff --git a/libpore/p9_stop_api.H b/libpore/p9_stop_api.H index 3f6420ff..983a3845 100644 --- a/libpore/p9_stop_api.H +++ b/libpore/p9_stop_api.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -114,6 +114,7 @@ typedef enum STOP_SAVE_FAIL = 14, // for internal failure within firmware. STOP_SAVE_SPR_ENTRY_MISSING = 15, STOP_SAVE_SPR_BIT_POS_RESERVE = 16, + STOP_SAVE_API_IMG_INCOMPATIBLE = 18, } StopReturnCode_t; /** @@ -198,6 +199,21 @@ typedef enum BIT_POS_USPRG1 = 30, } SprBitPositionList_t; +/** + * @brief List of major incompatibilities between API version. + * @note STOP APIs assumes a specific HOMER layout, certain + * level of CME-SGPE hcode and certain version of self-save restore + * binary. A mismatch can break STOP function. + */ + +typedef enum +{ + SMF_SUPPORT_MISSING_IN_HOMER = 0x01, + SELF_SUPPORT_MISSING_FOR_LE_HYP = 0x02, + IPL_RUNTIME_CPU_SAVE_VER_MISMATCH = 0x04, + SELF_RESTORE_VER_MISMATCH = 0x08, +} VersionIncompList_t; + #ifdef __cplusplus extern "C" { @@ -341,6 +357,14 @@ StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, */ StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); +/** + * @brief verifies if API is compatible of current HOMER image. + * @param[in] i_pImage points to the start of HOMER image of P9 chip. + * @param[out] o_inCompVector list of incompatibilities found. + * @return STOP_SAVE_SUCCESS if if API succeeds, error code otherwise. + */ +StopReturnCode_t proc_stop_api_discover_capability( void* const i_pImage, uint64_t* o_inCompVector ); + #ifdef __cplusplus } // extern "C" }; // namespace stopImageSection ends