From patchwork Sat Jan 4 01:19:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mauro Condarelli X-Patchwork-Id: 1217528 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mclink.it Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47qcnq1qbJz9sPn for ; Sat, 4 Jan 2020 21:04:47 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DF89A816FC; Sat, 4 Jan 2020 11:04:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=mclink.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 0CAC9816FD; Sat, 4 Jan 2020 11:04:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from relaygw3-4.mclink.it (relaygw3-4.mclink.it [213.21.178.143]) by phobos.denx.de (Postfix) with ESMTP id 5A8C28004A for ; Sat, 4 Jan 2020 11:04:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=mclink.it Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=mc5686@mclink.it Received: from [172.24.30.41] (HELO smtpoutgw1.mclink.it) by relaygw3-4.mclink.it (CommuniGate Pro SMTP 6.0.6) with ESMTP id 160371085 for u-boot@lists.denx.de; Sat, 04 Jan 2020 02:19:38 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2BbBgCl5w9e//jaMU8NWRwBAjgBBAQBDgEHAYFMhESECZEog26GAI9hgWcJAQEBAQEBAQEBNwEBhk84EwIQAQEFAQEBAQEFBIwOAQEEJARXFBMDAQIrAlEODQYCAQGDHgGCUgWQQpp/dX8zhU+DM4EtEIE2AYxxgUGBESeHOAQgA4Mkgl4EgT8BAQGUc2ENl3QBBgKBXlmDYZIzBhuCRod9kBeMYp5bgXqBQIEegU5QJViMQwMXjiRzjHUBgkIBAQ Received: from host248-218-dynamic.49-79-r.retail.telecomitalia.it (HELO [192.168.7.118]) ([79.49.218.248]) by smtpoutgw1.mclink.it with ESMTP; 04 Jan 2020 02:19:37 +0100 To: U-Boot Mailing List From: Mauro Condarelli Subject: SPI NOR stops working if I put Env in MMC Message-ID: <352f8b26-64e2-b075-1fa1-6667df84e0fc@mclink.it> Date: Sat, 4 Jan 2020 02:19:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.1 MIME-Version: 1.0 Content-Language: en-US X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean Hi, I'm facing a strange problem that took quite a while to analyze. I'm porting U-Boot to a new board and thus some problem is expected. I am also trying to configure U-Boot in a useful (for my purposes) way. I decided to switch Environment storage from SPI NOR to SD card (in a file in FAT partition. Before switch I had both SPI NOR (MTD) and MMC working. > U-Boot 2020.01-rc5-00074-g57fe7de5a3-dirty (Jan 04 2020 - 01:38:21 +0100) > > CPU:   MT7628 Rev 1.2 - Boot from XTAL (3-Byte SPI Addr) > Model: VoCore2 > DRAM:  128 MiB > MMC:   mmc@10130000: 0 > Loading Environment from SPI Flash... SF: Detected gd25q128 with page > size 256 Bytes, erase size 4 KiB, total 16 MiB > OK > In:    uart2@e00 > Out:   uart2@e00 > Err:   uart2@e00 > Model: VoCore2 > => mtd list > List of MTD devices: > * nor0 >   - type: NOR flash >   - block size: 0x1000 bytes >   - min I/O: 0x1 bytes >   - 0x000000000000-0x000001000000 : "nor0" >       - 0x000000000000-0x000000050000 : "u-boot" >       - 0x000000050000-0x000000300000 : "kernel" >       - 0x000000300000-0x000000ffe000 : "squash" >       - 0x000000ffe000-0x000000fff000 : "env" >       - 0x000000fff000-0x000001000000 : "factory" > => mmc part > > Partition Map for MMC device 0  --   Partition Type: DOS > > Part    Start Sector    Num Sectors    UUID        Type >   1    2048          262144        f31c8249-01    0c >   2    264192        4194304       f31c8249-02    83 >   3    4458496       327680        f31c8249-03    83 >   4    4786176       10737664      f31c8249-04    05 Extd >   5    4788224       2097152       f31c8249-05    83 >   6    6887424       2097152       f31c8249-06    83 > => I made a minimal change in configuration: > mcon@cinderella:/tmp/u-boot$ git diff > diff --git a/configs/vocore_vocore2_defconfig > b/configs/vocore_vocore2_defconfig > index ad1b580431..ece98beea0 100644 > --- a/configs/vocore_vocore2_defconfig > +++ b/configs/vocore_vocore2_defconfig > @@ -1,8 +1,6 @@ >  CONFIG_MIPS=y >  CONFIG_SYS_TEXT_BASE=0x80010000 >  CONFIG_ENV_SIZE=0x00001000 > -CONFIG_ENV_OFFSET=0x00FFE000 > -CONFIG_ENV_SECT_SIZE=0x00001000 >  CONFIG_ARCH_MTMIPS=y >  CONFIG_BOARD_VOCORE2=y >  CONFIG_MIPS_BOOT_FDT=y > @@ -37,8 +35,9 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" >  CONFIG_MTDPARTS_DEFAULT="spi0.0:320k(u-boot),2752k(kernel),13304k(filesystem),4k(env),-(factory)" >  # CONFIG_ISO_PARTITION is not set >  CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" > -CONFIG_ENV_IS_IN_SPI_FLASH=y > -CONFIG_ENV_ADDR=0x00FFE000 > +CONFIG_ENV_IS_IN_FAT=y > +CONFIG_ENV_FAT_INTERFACE="mmc" > +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" >  # CONFIG_NET is not set >  # CONFIG_DM_DEVICE_REMOVE is not set >  CONFIG_BLK=y > mcon@cinderella:/tmp/u-boot$ ... but it seems very destructive for spi: > U-Boot 2020.01-rc5-00074-g0cac9383d7-dirty (Jan 04 2020 - 01:55:34 +0100) > > CPU:   MT7628 Rev 1.2 - Boot from XTAL (3-Byte SPI Addr) > Model: VoCore2 > DRAM:  128 MiB > MMC:   mmc@10130000: 0 > Loading Environment from FAT... OK > In:    uart2@e00 > Out:   uart2@e00 > Err:   uart2@e00 > Model: VoCore2 > => mmc part > > Partition Map for MMC device 0  --   Partition Type: DOS > > Part    Start Sector    Num Sectors    UUID        Type >   1    2048          262144        f31c8249-01    0c >   2    264192        4194304       f31c8249-02    83 >   3    4458496       327680        f31c8249-03    83 >   4    4786176       10737664      f31c8249-04    05 Extd >   5    4788224       2097152       f31c8249-05    83 >   6    6887424       2097152       f31c8249-06    83 > => mtd list > Could not find a valid device for spi0.0 > List of MTD devices: > No MTD device found > => I assume some initialization is not done, but I would like some help to debug this as I did *not* change anything in SPI (aside from setting it in .dts). OTOH I had to change a bit MMC handling, but that shouldn't be relevant, or is it? I attach my complete patch against a fairly recent commit (it was "master" a few hours ago). The patch is to the working ENV_IS_IN_SPI_FLASH version. Changes for "not working" with ENV_IS_IN_FAT are above. Please advise. Thanks in Advance Mauro From 43e2aa1dd77221e10479a4352a50332942beeb38 Mon Sep 17 00:00:00 2001 From: Mauro Condarelli Date: Sat, 4 Jan 2020 00:31:54 +0100 Subject: [PATCH] Port to VoCore2 board. Signed-off-by: Mauro Condarelli --- arch/mips/dts/Makefile | 1 + arch/mips/dts/mt7628a.dtsi | 18 +++++- arch/mips/dts/vocore_vocore2.dts | 83 ++++++++++++++++++++++++++++ arch/mips/mach-mtmips/Kconfig | 9 +++ board/vocore/vocore2/Kconfig | 11 ++++ board/vocore/vocore2/Makefile | 2 + board/vocore/vocore2/board.c | 35 ++++++++++++ configs/vocore_vocore2_defconfig | 70 +++++++++++++++++++++++ drivers/clk/Kconfig | 8 +++ drivers/clk/Makefile | 1 + drivers/clk/clk-mtmips-cg.c | 63 +++++++++++++++++++++ drivers/phy/Kconfig | 2 + include/configs/vocore2.h | 43 ++++++++++++++ include/dt-bindings/clk/mt7628-clk.h | 31 +++++++++++ 14 files changed, 376 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/vocore_vocore2.dts create mode 100644 board/vocore/vocore2/Kconfig create mode 100644 board/vocore/vocore2/Makefile create mode 100644 board/vocore/vocore2/board.c create mode 100644 configs/vocore_vocore2_defconfig create mode 100644 drivers/clk/clk-mtmips-cg.c create mode 100644 include/configs/vocore2.h create mode 100644 include/dt-bindings/clk/mt7628-clk.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index c9d75596f2..5ece224511 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 76a80c8952..4c26ee7ffc 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -61,6 +61,12 @@ u-boot,dm-pre-reloc; }; + clkgate: clkgate@0x30 { + reg = <0x30 0x4>; + compatible = "mediatek,mtmips-clk-gate"; + #clock-cells = <1>; + }; + rstctrl: rstctrl@0x34 { reg = <0x34 0x4>; compatible = "mediatek,mtmips-reset"; @@ -397,9 +403,19 @@ builtin-cd = <1>; r_smpl = <1>; - clocks = <&clk48m>, <&clkctrl CLK_SDXC>; + interrupt-parent = <&intc>; + interrupts = <14>; + + clocks = <&clk48m>, <&clk48m>; clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd_iot_mode>; + pinctrl-1 = <&sd_iot_mode>; + + vmmc-supply = <&clk48m>; + vqmmc-supply = <&clk48m>; + resets = <&rstctrl MT7628_SDXC_RST>; status = "disabled"; diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts new file mode 100644 index 0000000000..87c5552710 --- /dev/null +++ b/arch/mips/dts/vocore_vocore2.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Mauro Condarelli + */ + +/dts-v1/; +#include "mt7628a.dtsi" + +/ { + compatible = "vocore,vocore2", "ralink,mt7628a-soc"; + model = "VoCore2"; + + aliases { + serial0 = &uart2; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS2,115200 root=/dev/mtdblock4 rootfstype=squashfs USE=SD"; + stdout-path = &uart2; + }; +}; + +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + nor0: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + spi-max-frequency = <10000000>; + reg = <0x0>; + m25p,chunked-io = <32>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x50000>; + }; + partition@50000 { + label = "kernel"; + reg = <0x50000 0x2b0000>; + }; + partition@300000 { + label = "filesystem"; + reg = <0x300000 0xcfe000>; + }; + partition@ffe000 { + label = "env"; + reg = <0xffe000 0x001000>; + }; + eeprom: partition@fff000 { + label = "factory"; + reg = <0xfff000 0x001000>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; + +&mmc { + status = "okay"; +}; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index c8dcf19c0d..57dfaebaec 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -43,6 +43,14 @@ config BOARD_LINKIT_SMART_7688 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a MT7688 (PCIe). +config BOARD_VOCORE2 + bool "VoCore2" + depends on SOC_MT7628 + select SUPPORTS_BOOT_RAM + help + VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM + and 16 MiB of flash (SPI). + endchoice choice @@ -134,5 +142,6 @@ config SUPPORTS_BOOT_RAM source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" +source "board/vocore/vocore2/Kconfig" endmenu diff --git a/board/vocore/vocore2/Kconfig b/board/vocore/vocore2/Kconfig new file mode 100644 index 0000000000..9178c3ab32 --- /dev/null +++ b/board/vocore/vocore2/Kconfig @@ -0,0 +1,11 @@ +if BOARD_VOCORE2 +config SYS_BOARD + default "vocore2" + +config SYS_VENDOR + default "vocore" + +config SYS_CONFIG_NAME + default "vocore2" + +endif diff --git a/board/vocore/vocore2/Makefile b/board/vocore/vocore2/Makefile new file mode 100644 index 0000000000..4b162318c2 --- /dev/null +++ b/board/vocore/vocore2/Makefile @@ -0,0 +1,2 @@ + +obj-y := board.o diff --git a/board/vocore/vocore2/board.c b/board/vocore/vocore2/board.c new file mode 100644 index 0000000000..279b1a710b --- /dev/null +++ b/board/vocore/vocore2/board.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Mauro Condarelli + * + * Note: this is largely copied from: + * board/seeed/linkit_smart_7688/board.c + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include + +#define MT76XX_GPIO1_MODE 0x10000060 + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ + void __iomem *gpio_mode; + + /* Select UART2 mode instead of GPIO mode (default) */ + gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100); + clrbits_le32(gpio_mode, GENMASK(27, 26)); +} + +int board_early_init_f(void) +{ + /* + * The pin muxing of UART2 also needs to be done, if debug uart + * is not enabled. So we need to call this function here as well. + */ + board_debug_uart_init(); + + return 0; +} diff --git a/configs/vocore_vocore2_defconfig b/configs/vocore_vocore2_defconfig new file mode 100644 index 0000000000..ad1b580431 --- /dev/null +++ b/configs/vocore_vocore2_defconfig @@ -0,0 +1,70 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ENV_SIZE=0x00001000 +CONFIG_ENV_OFFSET=0x00FFE000 +CONFIG_ENV_SECT_SIZE=0x00001000 +CONFIG_ARCH_MTMIPS=y +CONFIG_BOARD_VOCORE2=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BOOT_GET_KBD=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_BOOTARGS=y +CONFIG_LOGLEVEL=8 +CONFIG_VERSION_VARIABLE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_AUTOBOOT is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPIO=y +CONFIG_RANDOM_UUID=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="spi0.0:320k(u-boot),2752k(kernel),13304k(filesystem),4k(env),-(factory)" +# CONFIG_ISO_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x00FFE000 +# CONFIG_NET is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BLK=y +# CONFIG_INPUT is not set +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MTD=y +# CONFIG_DM_ETH is not set +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=3 +CONFIG_SPI=y +CONFIG_MT7621_SPI=y +CONFIG_SYSRESET_SYSCON=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_LZMA=y +CONFIG_LZO=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 16d4237f89..fbe6ae86d6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -176,4 +176,12 @@ config SANDBOX_CLK_CCF Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver. +config CLK_MTMIPS_GATE + bool "Enable clock gating driver for MediaTek MIPS platform" + depends on CLK && ARCH_MTMIPS + default y + help + Enable clock gating driver for MediaTek MIPS platform. + This driver supports only clock enable and disable. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 06131edb9f..585335be25 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk-mtmips-cg.c b/drivers/clk/clk-mtmips-cg.c new file mode 100644 index 0000000000..0221d95aed --- /dev/null +++ b/drivers/clk/clk-mtmips-cg.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao + */ + +#include +#include +#include +#include + +struct mtmips_clk_gate_priv { + void __iomem *base; +}; + +static int mtmips_clk_gate_enable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + setbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +static int mtmips_clk_gate_disable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + clrbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mtmips_clk_gate_ops = { + .enable = mtmips_clk_gate_enable, + .disable = mtmips_clk_gate_disable, +}; + +static int mtmips_clk_gate_probe(struct udevice *dev) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_clk_gate_ids[] = { + { .compatible = "mediatek,mtmips-clk-gate" }, + { } +}; + +U_BOOT_DRIVER(mtmips_clk_gate) = { + .name = "mtmips-clk-gate", + .id = UCLASS_CLK, + .of_match = mtmips_clk_gate_ids, + .probe = mtmips_clk_gate_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv), + .ops = &mtmips_clk_gate_ops, +}; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a72f34f0d4..d9acda2c6a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -201,6 +201,8 @@ config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY depends on SOC_MT7628 + select CLK + select DM_RESET help Support the USB PHY in MT76x8 SoCs diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h new file mode 100644 index 0000000000..4653f4f569 --- /dev/null +++ b/include/configs/vocore2.h @@ -0,0 +1,43 @@ +#ifndef __VOCORE2_CONFIG_H__ +#define __VOCORE2_CONFIG_H__ + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#ifdef CONFIG_BOOT_RAM +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } +#define CONFIG_BAUDRATE 115200 + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ +#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#endif + +#endif//__VOCORE2_CONFIG_H__ diff --git a/include/dt-bindings/clk/mt7628-clk.h b/include/dt-bindings/clk/mt7628-clk.h new file mode 100644 index 0000000000..6784d6e50b --- /dev/null +++ b/include/dt-bindings/clk/mt7628-clk.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +#define MT7628_PWM_CLK 31 +#define MT7628_SDXC_CLK 30 +#define MT7628_CRYPTO_CLK 29 +#define MT7628_MIPS_CNT_CLK 28 +#define MT7628_PCIE_CLK 26 +#define MT7628_UPHY_CLK 25 +#define MT7628_ETH_CLK 23 +#define MT7628_UART2_CLK 20 +#define MT7628_UART1_CLK 19 +#define MT7628_SPI_CLK 18 +#define MT7628_I2S_CLK 17 +#define MT7628_I2C_CLK 16 +#define MT7628_GDMA_CLK 14 +#define MT7628_PIO_CLK 13 +#define MT7628_UART0_CLK 12 +#define MT7628_PCM_CLK 11 +#define MT7628_MC_CLK 10 +#define MT7628_INT_CLK 9 +#define MT7628_TIMER_CLK 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ -- 2.25.0.rc0