From patchwork Sat Nov 25 12:01:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 841230 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykWs61ldHz9s7f for ; Sat, 25 Nov 2017 23:02:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751129AbdKYMCd (ORCPT ); Sat, 25 Nov 2017 07:02:33 -0500 Received: from foss.arm.com ([217.140.101.70]:53532 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751305AbdKYMCc (ORCPT ); Sat, 25 Nov 2017 07:02:32 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 795E11596; Sat, 25 Nov 2017 04:02:32 -0800 (PST) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 70A933F236; Sat, 25 Nov 2017 04:02:30 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: Linus Walleij , Rob Herring , Chris Obbard , Mark Rutland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 1/2] arm64: dts: allwinner: H5: remove redundant MMC0 card detect pin Date: Sat, 25 Nov 2017 12:01:59 +0000 Message-Id: <20171125120200.23294-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171125120200.23294-1-andre.przywara@arm.com> References: <20171125120200.23294-1-andre.przywara@arm.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org PF6 is mostly used as the CD pin for the microSD slot on H5 based boards. So far we were referencing this pin twice: once using the mmc0_cd_pin phandle, and then again directly as a GPIO via the pinctrl phandle. This will cause problems if the pinctrl driver enables strict mode, as the second request will fail now, leading to a driver init failure. Remove the redundant pin reference via the mmc0_cd_pin phandle. Signed-off-by: Andre Przywara Reported-by: Chris Obbard --- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts index 7c028af58f47..ea1101293892 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -135,7 +135,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 6eb8092d8e57..f1447003ea3c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -127,7 +127,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index a0ca925175aa..9e51d3a5f4e6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -161,7 +161,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index b47790650144..0f25c4a6f15d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -168,7 +168,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts index b6b7a561df8c..69ac04516ddb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts @@ -68,7 +68,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; From patchwork Sat Nov 25 12:02:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 841231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykWs82M2zz9s7f for ; Sat, 25 Nov 2017 23:02:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751508AbdKYMCf (ORCPT ); Sat, 25 Nov 2017 07:02:35 -0500 Received: from foss.arm.com ([217.140.101.70]:53544 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751305AbdKYMCf (ORCPT ); Sat, 25 Nov 2017 07:02:35 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C50A31610; Sat, 25 Nov 2017 04:02:34 -0800 (PST) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC05B3F236; Sat, 25 Nov 2017 04:02:32 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: Linus Walleij , Rob Herring , Chris Obbard , Mark Rutland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 2/2] pinctrl: sunxi: Disable strict mode for H5 driver Date: Sat, 25 Nov 2017 12:02:00 +0000 Message-Id: <20171125120200.23294-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171125120200.23294-1-andre.przywara@arm.com> References: <20171125120200.23294-1-andre.przywara@arm.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org All of the H5 boards in the kernel reference the MMC0 CD pin twice in their DT, so strict mode will make the MMC driver fail to load. To keep existing DTs working, disable strict mode in the H5 driver. Signed-off-by: Andre Przywara Reported-by: Chris Obbard Acked-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c index 97b48336f84a..a78d7b922ef4 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -535,14 +535,16 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = { .pins = sun50i_h5_pins, .npins = ARRAY_SIZE(sun50i_h5_pins), .irq_banks = 2, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { .pins = sun50i_h5_pins, .npins = ARRAY_SIZE(sun50i_h5_pins), .irq_banks = 3, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)