From patchwork Sat Nov 25 10:00:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Glisse X-Patchwork-Id: 841215 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-467892-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="bOgP7ztW"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ykT8h60dnz9s7F for ; Sat, 25 Nov 2017 21:00:49 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=lX2sXQnsqcYh23QUCys+wP/vzL9WNeGI/1SneCfhbimeMAlBpX0cO SgQ81ml9x2/IAqsWtLHRkgEx9xrqyjpGUtR+rPm0TAtDOm3fLcYoSxU+nzx2KPx8 5e1GLwexo53s7EPxZoFdrzqUm/NCCn7iN0k7QkDTpeuQJZhsyyZqtA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=jZB4RWBKkb65bAqx4X2S9FL/16M=; b=bOgP7ztWIxPIqXdDZEr/ WO4kjYo6RavVHAwCIi7fZnJl7DUqkL9xrxunVtwHg9aMD3KAUOCYsHSvomgRAy9O v+aJdOmgZ+VFo1pzuAIZCTfBAWlYqhPhWazlFIsHOe18MeavaiBdAvHrjABej3Ym LDLJf/bDzyJz1aFcur+/U5M= Received: (qmail 39756 invoked by alias); 25 Nov 2017 10:00:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 39671 invoked by uid 89); 25 Nov 2017 10:00:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KB_WAM_FROM_NAME_SINGLEWORD, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=globally, UD:avx2intrin.h, avx2intrin.h, avx2intrinh X-HELO: mail3-relais-sop.national.inria.fr Received: from mail3-relais-sop.national.inria.fr (HELO mail3-relais-sop.national.inria.fr) (192.134.164.104) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 25 Nov 2017 10:00:14 +0000 Received: from ip-4.net-89-2-164.rev.numericable.fr (HELO stedding) ([89.2.164.4]) by mail3-relais-sop.national.inria.fr with ESMTP/TLS/DHE-RSA-AES256-SHA; 25 Nov 2017 11:00:11 +0100 Date: Sat, 25 Nov 2017 11:00:07 +0100 (CET) From: Marc Glisse To: gcc-patches@gcc.gnu.org Subject: [i386] Mask generation in avx2intrin.h Message-ID: User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Hello, the way full masks are generated currently in avx2intrin.h is questionable: opaque for the inline functions, weird/wrong for the macros. It is possible we may want to add code so the constant mask with all ones may be generated with vxorpd+vcmpeqpd instead of loading it from memory, but that looks like something that should be decided globally, not in each instruction that uses it. Bootstrap+regtest on x86_64-pc-linux-gnu (skylake). 2017-11-27 Marc Glisse PR target/80885 * config/i386/avx2intrin.h (_mm_i32gather_pd): Rewrite mask generation. (_mm256_i32gather_pd): Likewise. (_mm_i64gather_pd): Likewise. (_mm256_i64gather_pd): Likewise. (_mm_i32gather_ps): Likewise. (_mm256_i32gather_ps): Likewise. (_mm_i64gather_ps): Likewise. (_mm256_i64gather_ps): Likewise. Index: gcc/config/i386/avx2intrin.h =================================================================== --- gcc/config/i386/avx2intrin.h (revision 255140) +++ gcc/config/i386/avx2intrin.h (working copy) @@ -1241,22 +1241,21 @@ __attribute__ ((__gnu_inline__, __always _mm_srlv_epi64 (__m128i __X, __m128i __Y) { return (__m128i) __builtin_ia32_psrlv2di ((__v2di)__X, (__v2di)__Y); } #ifdef __OPTIMIZE__ extern __inline __m128d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_i32gather_pd (double const *__base, __m128i __index, const int __scale) { - __v2df __zero = _mm_setzero_pd (); - __v2df __mask = _mm_cmpeq_pd (__zero, __zero); + __v2df __mask = (__v2df)_mm_set1_epi64x (-1); return (__m128d) __builtin_ia32_gathersiv2df (_mm_undefined_pd (), __base, (__v4si)__index, __mask, __scale); } extern __inline __m128d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1267,22 +1266,21 @@ _mm_mask_i32gather_pd (__m128d __src, do __base, (__v4si)__index, (__v2df)__mask, __scale); } extern __inline __m256d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i32gather_pd (double const *__base, __m128i __index, const int __scale) { - __v4df __zero = _mm256_setzero_pd (); - __v4df __mask = _mm256_cmp_pd (__zero, __zero, _CMP_EQ_OQ); + __v4df __mask = (__v4df)_mm256_set1_epi64x (-1); return (__m256d) __builtin_ia32_gathersiv4df (_mm256_undefined_pd (), __base, (__v4si)__index, __mask, __scale); } extern __inline __m256d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1294,21 +1292,21 @@ _mm256_mask_i32gather_pd (__m256d __src, (__v4si)__index, (__v4df)__mask, __scale); } extern __inline __m128d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_i64gather_pd (double const *__base, __m128i __index, const int __scale) { __v2df __src = _mm_setzero_pd (); - __v2df __mask = _mm_cmpeq_pd (__src, __src); + __v2df __mask = (__v2df)_mm_set1_epi64x (-1); return (__m128d) __builtin_ia32_gatherdiv2df (__src, __base, (__v2di)__index, __mask, __scale); } extern __inline __m128d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1320,21 +1318,21 @@ _mm_mask_i64gather_pd (__m128d __src, do (__v2di)__index, (__v2df)__mask, __scale); } extern __inline __m256d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i64gather_pd (double const *__base, __m256i __index, const int __scale) { __v4df __src = _mm256_setzero_pd (); - __v4df __mask = _mm256_cmp_pd (__src, __src, _CMP_EQ_OQ); + __v4df __mask = (__v4df)_mm256_set1_epi64x (-1); return (__m256d) __builtin_ia32_gatherdiv4df (__src, __base, (__v4di)__index, __mask, __scale); } extern __inline __m256d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1346,21 +1344,21 @@ _mm256_mask_i64gather_pd (__m256d __src, (__v4di)__index, (__v4df)__mask, __scale); } extern __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_i32gather_ps (float const *__base, __m128i __index, const int __scale) { __v4sf __src = _mm_setzero_ps (); - __v4sf __mask = _mm_cmpeq_ps (__src, __src); + __v4sf __mask = (__v4sf)_mm_set1_epi64x (-1); return (__m128) __builtin_ia32_gathersiv4sf (__src, __base, (__v4si)__index, __mask, __scale); } extern __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1372,21 +1370,21 @@ _mm_mask_i32gather_ps (__m128 __src, flo (__v4si)__index, (__v4sf)__mask, __scale); } extern __inline __m256 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i32gather_ps (float const *__base, __m256i __index, const int __scale) { __v8sf __src = _mm256_setzero_ps (); - __v8sf __mask = _mm256_cmp_ps (__src, __src, _CMP_EQ_OQ); + __v8sf __mask = (__v8sf)_mm256_set1_epi64x (-1); return (__m256) __builtin_ia32_gathersiv8sf (__src, __base, (__v8si)__index, __mask, __scale); } extern __inline __m256 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1398,21 +1396,21 @@ _mm256_mask_i32gather_ps (__m256 __src, (__v8si)__index, (__v8sf)__mask, __scale); } extern __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_i64gather_ps (float const *__base, __m128i __index, const int __scale) { __v4sf __src = _mm_setzero_ps (); - __v4sf __mask = _mm_cmpeq_ps (__src, __src); + __v4sf __mask = (__v4sf)_mm_set1_epi64x (-1); return (__m128) __builtin_ia32_gatherdiv4sf (__src, __base, (__v2di)__index, __mask, __scale); } extern __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1424,21 +1422,21 @@ _mm_mask_i64gather_ps (__m128 __src, flo (__v2di)__index, (__v4sf)__mask, __scale); } extern __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_i64gather_ps (float const *__base, __m256i __index, const int __scale) { __v4sf __src = _mm_setzero_ps (); - __v4sf __mask = _mm_cmpeq_ps (__src, __src); + __v4sf __mask = (__v4sf)_mm_set1_epi64x (-1); return (__m128) __builtin_ia32_gatherdiv4sf256 (__src, __base, (__v4di)__index, __mask, __scale); } extern __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) @@ -1665,126 +1663,119 @@ _mm256_mask_i64gather_epi32 (__m128i __s __base, (__v4di)__index, (__v4si)__mask, __scale); } #else /* __OPTIMIZE__ */ #define _mm_i32gather_pd(BASE, INDEX, SCALE) \ (__m128d) __builtin_ia32_gathersiv2df ((__v2df) _mm_setzero_pd (), \ (double const *)BASE, \ (__v4si)(__m128i)INDEX, \ - (__v2df)_mm_set1_pd( \ - (double)(long long int) -1), \ + (__v2df)_mm_set1_epi64x (-1), \ (int)SCALE) #define _mm_mask_i32gather_pd(SRC, BASE, INDEX, MASK, SCALE) \ (__m128d) __builtin_ia32_gathersiv2df ((__v2df)(__m128d)SRC, \ (double const *)BASE, \ (__v4si)(__m128i)INDEX, \ (__v2df)(__m128d)MASK, \ (int)SCALE) #define _mm256_i32gather_pd(BASE, INDEX, SCALE) \ (__m256d) __builtin_ia32_gathersiv4df ((__v4df) _mm256_setzero_pd (), \ (double const *)BASE, \ (__v4si)(__m128i)INDEX, \ - (__v4df)_mm256_set1_pd( \ - (double)(long long int) -1), \ + (__v4df)_mm256_set1_epi64x(-1),\ (int)SCALE) #define _mm256_mask_i32gather_pd(SRC, BASE, INDEX, MASK, SCALE) \ (__m256d) __builtin_ia32_gathersiv4df ((__v4df)(__m256d)SRC, \ (double const *)BASE, \ (__v4si)(__m128i)INDEX, \ (__v4df)(__m256d)MASK, \ (int)SCALE) #define _mm_i64gather_pd(BASE, INDEX, SCALE) \ (__m128d) __builtin_ia32_gatherdiv2df ((__v2df) _mm_setzero_pd (), \ (double const *)BASE, \ (__v2di)(__m128i)INDEX, \ - (__v2df)_mm_set1_pd( \ - (double)(long long int) -1), \ + (__v2df)_mm_set1_epi64x (-1), \ (int)SCALE) #define _mm_mask_i64gather_pd(SRC, BASE, INDEX, MASK, SCALE) \ (__m128d) __builtin_ia32_gatherdiv2df ((__v2df)(__m128d)SRC, \ (double const *)BASE, \ (__v2di)(__m128i)INDEX, \ (__v2df)(__m128d)MASK, \ (int)SCALE) #define _mm256_i64gather_pd(BASE, INDEX, SCALE) \ (__m256d) __builtin_ia32_gatherdiv4df ((__v4df) _mm256_setzero_pd (), \ (double const *)BASE, \ (__v4di)(__m256i)INDEX, \ - (__v4df)_mm256_set1_pd( \ - (double)(long long int) -1), \ + (__v4df)_mm256_set1_epi64x(-1),\ (int)SCALE) #define _mm256_mask_i64gather_pd(SRC, BASE, INDEX, MASK, SCALE) \ (__m256d) __builtin_ia32_gatherdiv4df ((__v4df)(__m256d)SRC, \ (double const *)BASE, \ (__v4di)(__m256i)INDEX, \ (__v4df)(__m256d)MASK, \ (int)SCALE) #define _mm_i32gather_ps(BASE, INDEX, SCALE) \ (__m128) __builtin_ia32_gathersiv4sf ((__v4sf) _mm_setzero_ps (), \ (float const *)BASE, \ (__v4si)(__m128i)INDEX, \ - _mm_set1_ps ((float)(int) -1), \ + (__v4sf)_mm_set1_epi64x (-1), \ (int)SCALE) #define _mm_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE) \ (__m128) __builtin_ia32_gathersiv4sf ((__v4sf)(__m128d)SRC, \ (float const *)BASE, \ (__v4si)(__m128i)INDEX, \ (__v4sf)(__m128d)MASK, \ (int)SCALE) #define _mm256_i32gather_ps(BASE, INDEX, SCALE) \ (__m256) __builtin_ia32_gathersiv8sf ((__v8sf) _mm256_setzero_ps (), \ (float const *)BASE, \ (__v8si)(__m256i)INDEX, \ - (__v8sf)_mm256_set1_ps ( \ - (float)(int) -1), \ + (__v8sf)_mm256_set1_epi64x(-1),\ (int)SCALE) #define _mm256_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE) \ (__m256) __builtin_ia32_gathersiv8sf ((__v8sf)(__m256)SRC, \ (float const *)BASE, \ (__v8si)(__m256i)INDEX, \ (__v8sf)(__m256d)MASK, \ (int)SCALE) #define _mm_i64gather_ps(BASE, INDEX, SCALE) \ (__m128) __builtin_ia32_gatherdiv4sf ((__v4sf) _mm_setzero_pd (), \ (float const *)BASE, \ (__v2di)(__m128i)INDEX, \ - (__v4sf)_mm_set1_ps ( \ - (float)(int) -1), \ + (__v4sf)_mm_set1_epi64x (-1), \ (int)SCALE) #define _mm_mask_i64gather_ps(SRC, BASE, INDEX, MASK, SCALE) \ (__m128) __builtin_ia32_gatherdiv4sf ((__v4sf)(__m128)SRC, \ (float const *)BASE, \ (__v2di)(__m128i)INDEX, \ (__v4sf)(__m128d)MASK, \ (int)SCALE) #define _mm256_i64gather_ps(BASE, INDEX, SCALE) \ (__m128) __builtin_ia32_gatherdiv4sf256 ((__v4sf) _mm_setzero_ps (), \ (float const *)BASE, \ (__v4di)(__m256i)INDEX, \ - (__v4sf)_mm_set1_ps( \ - (float)(int) -1), \ + (__v4sf)_mm_set1_epi64x (-1),\ (int)SCALE) #define _mm256_mask_i64gather_ps(SRC, BASE, INDEX, MASK, SCALE) \ (__m128) __builtin_ia32_gatherdiv4sf256 ((__v4sf)(__m128)SRC, \ (float const *)BASE, \ (__v4di)(__m256i)INDEX, \ (__v4sf)(__m128)MASK, \ (int)SCALE) #define _mm_i32gather_epi64(BASE, INDEX, SCALE) \