From patchwork Thu Dec 19 18:51:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rzuwWUvW"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47f1Fz0HVyz9sSv for ; Fri, 20 Dec 2019 05:52:21 +1100 (AEDT) Received: from localhost ([::1]:46622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0uH-0006zw-BC for incoming@patchwork.ozlabs.org; Thu, 19 Dec 2019 13:52:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39067) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0ta-0006zd-Mx for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tZ-0007PI-IQ for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:34 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:45402) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tZ-0007F6-9M; Thu, 19 Dec 2019 13:51:33 -0500 Received: by mail-wr1-x433.google.com with SMTP id j42so7019940wrj.12; Thu, 19 Dec 2019 10:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=rzuwWUvW7fxrR8Q8rS5X13OM54/eLmN+zTAKxDRco/Oq+BgWmNrUIl1hDDIWXer+Fy L8YnYjYdzu/VREz33h1DmdVp1ZV1AaGR3fO9NBba+UOJNV1pQdpBbqAuC6dumVMl6qZP UlGW6/h5H1PWsw/K4YpyEoRngGgWynIlAal3ptwF+FFioIhDWpw+Nq8o5FPwZrYlr7ar RnhS792N/crlExsgvEPRX4/UKZi+f9ovgG6Jb2hguh3dgpmivk+BHr6KLFHkKHrWyiuZ 1Srq0elLFhgW9+pZ9HOj/JnX1wLx8CeNIT5NUZhw64eSIcTOLtRs4lFRTlIbMI0qA6pc JTTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eIBy99noocVmlwSAa63POWN6vKv6FpnLkLhwBwwq9LM=; b=f8DydsLICYizaAkKFyJFFmJB+Lu4/GBxutH+i2NeRTYCPzGUiatAsi1WtJoFdaSD5W XiiofyIQlmJY3gbourO/156bVSCQlSHWgf1Bh22xgurwjyK0fTWGsej0jcrJWnWRQWZn uyhvtRNEf2iuTXKGMgL6zvTEc8iRuLnegl/1vz0gSgBA3zWdutVo3SZudvvEkq6JPEtS 3L+gI+JuHGI7XkK8PoiDRQ9Z0fqkiUhKYcsh/sJ8fgXd0/4+SyHcmiA/ilJmFOFnFWf8 tnf2KkYiC43kx5jziqrsCbeVd/QXEvhjPOCe2XsMCDg790BTgKE9iMWO/pAzZUwP8q8k AYUQ== X-Gm-Message-State: APjAAAVcnU76KWeiUNlDt/eI6/YzskyYRDTXQZyw5Zxa8GD8mFNLYScB drQWW4G6qaQ0mfN4OpTTZzjB850g X-Google-Smtp-Source: APXvYqznBI30MLzRunuvTH94RbArJIo8XyU1MvwcT9Wtl4G1B96s4+YMJ9L6JV0fFjxe8mEQ6WjUCw== X-Received: by 2002:adf:c746:: with SMTP id b6mr10451458wrh.298.1576781490780; Thu, 19 Dec 2019 10:51:30 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 01/13] hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition Date: Thu, 19 Dec 2019 19:51:15 +0100 Message-Id: <20191219185127.24388-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We have a definition for this magic value '6', use it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 871c95b512..6aceda81ee 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -32,7 +32,7 @@ #define AW_A10_PIT_TIMER_BASE 0x10 #define AW_A10_PIT_TIMER_BASE_END \ - (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT) + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) #define AW_A10_PIT_DEFAULT_CLOCK 0x4 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index aae880f5b3..117e5c7bf8 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -225,7 +225,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status = 0; a10_pit_update_irq(s); - for (i = 0; i < 6; i++) { + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] = 0; s->count[i] = 0; From patchwork Thu Dec 19 18:51:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CiqPXITD"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47f1KM1ps7z9sS9 for ; Fri, 20 Dec 2019 05:55:17 +1100 (AEDT) Received: from localhost ([::1]:46652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0x9-0002Kq-26 for incoming@patchwork.ozlabs.org; Thu, 19 Dec 2019 13:55:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0td-00070O-BU for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tc-0007cs-1E for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:55406) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0ta-0007JT-OD; Thu, 19 Dec 2019 13:51:35 -0500 Received: by mail-wm1-x341.google.com with SMTP id q9so6525516wmj.5; Thu, 19 Dec 2019 10:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fXYp8lEUsOTs8WcsQwwp+b/Rx/W+yTQjD5EmKm5HZkQ=; b=CiqPXITD7Q6zjfjsVt8EFYgzvZiiPThER8xHaLyNLRpa42ZGuYzQ0RWvJzRYg/v564 wbF/PUl806Sb8yrqrkQPrnyYdmh7JEelLgNbMH/TR+EtdcL5E96Mcfh+h9OrIvrjcv8K IAaVUWzFVnImTSfDERTduPXzw0OZCA6y7tNs6+6A7DHnN8/d2FYiOAg6zSC553C7IVeG bXFIhQFAqQ747RPP93c0P+LhUOD3snmkEO81gDtzbDSmowFruBhwzqHhkj1DWMfrQyBU fn+OcjRJz1OKZQfxVnJRVMvtIolHAMjpq+kbdHsrXESFRDaI1o+VoY4TNy0QLXg2UjDe Um9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fXYp8lEUsOTs8WcsQwwp+b/Rx/W+yTQjD5EmKm5HZkQ=; b=kuIDvQ5S7BkonxO0HFl/5gaztqoBEi+BVVM8p2cC2mp8+bBYStKx3S3Q9A2xKa5+Y1 MDhHPSE1GUR+RRcIBJz4wqGLYxhOJJ2Kjhx7bYGSZx3ynuaTgVjOcJn4N71GqkqV/l/f K9XTpSPJ2/+OU8nJZ/n9KJRVgmErdx9rZopklCtmg+eW6C9F2oveSRKl6q7Ym2V03PI3 VwK//mm/3WBa1CIXnx1EZ+tSZfr0GG397f6WQ7ce/84OMXjfCX1WiQs0AkB7lGHZQUKT orYIwjWDmBX6XvyLyMI3kXky6GIQfKK6E3wW3XGv/tA15Mt8adDMkVQNmT5LXSKnGqWe TQXA== X-Gm-Message-State: APjAAAXUQzijNjMiE2FABUbqYWsUeKqUIPO2NgcnKiN9DpiTl/jpr5Ix Y+mKP/Bm5/aQ+1c+ej3grON0COsW X-Google-Smtp-Source: APXvYqyBP+csHZWV31aWT9PUtc9oSAzojq4IR+0YaAAAV132U+rS7oQtg+AaY6Qgehx1lhQ+kKItYg== X-Received: by 2002:a1c:4d03:: with SMTP id o3mr11881092wmh.164.1576781491873; Thu, 19 Dec 2019 10:51:31 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 02/13] hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition Date: Thu, 19 Dec 2019 19:51:16 +0100 Message-Id: <20191219185127.24388-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This controller is able to use up to 6 timers. Later we will reuse part of it to model other similar controllers but with less timers. To simplify the VMSTATE, we'll keep a max of 6 timers. Add a definition for that value. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank --- include/hw/timer/allwinner-a10-pit.h | 14 ++++++++------ hw/timer/allwinner-a10-pit.c | 8 ++++---- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 6aceda81ee..54c40c7db6 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -7,6 +7,8 @@ #define TYPE_AW_A10_PIT "allwinner-A10-timer" #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) +#define AW_PIT_TIMER_MAX 6 + #define AW_A10_PIT_TIMER_NR 6 #define AW_A10_PIT_TIMER_IRQ 0x1 #define AW_A10_PIT_WDOG_IRQ 0x100 @@ -47,17 +49,17 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_A10_PIT_TIMER_NR]; - ptimer_state * timer[AW_A10_PIT_TIMER_NR]; - AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; + qemu_irq irq[AW_PIT_TIMER_MAX]; + ptimer_state * timer[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_A10_PIT_TIMER_NR]; - uint32_t interval[AW_A10_PIT_TIMER_NR]; - uint32_t count[AW_A10_PIT_TIMER_NR]; + uint32_t control[AW_PIT_TIMER_MAX]; + uint32_t interval[AW_PIT_TIMER_MAX]; + uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 117e5c7bf8..b31a0bcd43 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -203,15 +203,15 @@ static const VMStateDescription vmstate_a10_pit = { .fields = (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), + VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 03/13] hw/timer/allwinner: Remove unused definitions Date: Thu, 19 Dec 2019 19:51:17 +0100 Message-Id: <20191219185127.24388-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Keeping unused definition is rather confusing when reviewing. Remove them. Signed-off-by: Philippe Mathieu-Daudé Tested-by: Niek Linnenbank --- include/hw/timer/allwinner-a10-pit.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 54c40c7db6..e4a644add9 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -10,8 +10,6 @@ #define AW_PIT_TIMER_MAX 6 #define AW_A10_PIT_TIMER_NR 6 -#define AW_A10_PIT_TIMER_IRQ 0x1 -#define AW_A10_PIT_WDOG_IRQ 0x100 #define AW_A10_PIT_TIMER_IRQ_EN 0 #define AW_A10_PIT_TIMER_IRQ_ST 0x4 From patchwork Thu Dec 19 18:51:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DOOoXp7w"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47f1Nc3HCZz9sSX for ; Fri, 20 Dec 2019 05:58:08 +1100 (AEDT) Received: from localhost ([::1]:46716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0zt-00065m-Jq for incoming@patchwork.ozlabs.org; Thu, 19 Dec 2019 13:58:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39372) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0td-00070L-BC for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tc-0007cm-0Q for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:37 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53867) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tb-0007Xp-PD; Thu, 19 Dec 2019 13:51:35 -0500 Received: by mail-wm1-x343.google.com with SMTP id m24so6507350wmc.3; Thu, 19 Dec 2019 10:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=DOOoXp7wOhfRVuo831S05oCEi09rbGM+mhvGwoAW9kVI0AW+Oi4238dlMdG1HOQLPi fv1sR8UjxVUOg9aff+Rn+lxEEBAqc4IWv8QwbdkXnkjj1xZMT8iYSKrthF2l7zzOTr+f kSuwqJcEKaudzWgZISsd9EjkoaD+uKrDdGo54li47kwOPP/+gvfVHoNifBXg9VmFaeUm wIqWtyMYSnb/S/bYWWX3fNHNxI1dnDqTD5KQhO61QRvJOZmWmqYvUwrVYoBqSmnmQ/tw Ltilcsgh3Db1J+pjsZg4GO1nShWstMrzDDMz/AbdPwCOLkQgcINIA0f1COTK23QyDxzg mwow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jIg+33KeWZZoVU4KTC1Qs/cBS+U2tDHwXFCUA5+HzbM=; b=g6rH1vb0qUz2V/LctLMY0bRjoukLHEKNrHaJ5/wLhWJ8MuOxvwZ+jhR2yDn3FBFFf9 jZgEDXd69zznrvo4Z8Flrx0xTOhh/dftH8xmWMes3uVprBFqi3AWIz/dMOqpPaqgnax3 +zo4yTfyv9CjtrPS+4ZHBk06kcdo8UPK58ugH2GaEObtn6SaupRLMHthjVKm/h0iS4T7 Eqv2a+6L5J1zM1fjK/bl+kUhWGl2QszMZkr6CQqnQiCS6jU+tzUuX+rm+Tv15uDOhruy dORsHThzVzmBkeA1FjVAV1pgJH5Urbfjat7HYUWGJtnABkXff61myXZj8TsWBDa3wjZr kdHw== X-Gm-Message-State: APjAAAXXO31ZbwhRw2O7PQ2k958YCFObxARqlVSTJdPEnGkvH/cKntAh 22H4gY1KGRjy466RmVvvKAWc3pSm X-Google-Smtp-Source: APXvYqx4/zuBzYIXCe0BcvOfXwN1MN94M8leEwqrgzY3pRbmv0q7FlOQyPpkYLKO5pfpunluWXKUUA== X-Received: by 2002:a1c:4b09:: with SMTP id y9mr12136089wma.103.1576781494368; Thu, 19 Dec 2019 10:51:34 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [PATCH 04/13] hw/timer/allwinner: Move definitions from header to source Date: Thu, 19 Dec 2019 19:51:18 +0100 Message-Id: <20191219185127.24388-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These definitions are only used in the implementation, thus don't need to be exported. Move them in the source file. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 28 -------------------------- hw/timer/allwinner-a10-pit.c | 30 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 28 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index e4a644add9..c28ee5ca47 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -5,37 +5,9 @@ #include "hw/sysbus.h" #define TYPE_AW_A10_PIT "allwinner-A10-timer" -#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) #define AW_PIT_TIMER_MAX 6 -#define AW_A10_PIT_TIMER_NR 6 - -#define AW_A10_PIT_TIMER_IRQ_EN 0 -#define AW_A10_PIT_TIMER_IRQ_ST 0x4 - -#define AW_A10_PIT_TIMER_CONTROL 0x0 -#define AW_A10_PIT_TIMER_EN 0x1 -#define AW_A10_PIT_TIMER_RELOAD 0x2 -#define AW_A10_PIT_TIMER_MODE 0x80 - -#define AW_A10_PIT_TIMER_INTERVAL 0x4 -#define AW_A10_PIT_TIMER_COUNT 0x8 -#define AW_A10_PIT_WDOG_CONTROL 0x90 -#define AW_A10_PIT_WDOG_MODE 0x94 - -#define AW_A10_PIT_COUNT_CTL 0xa0 -#define AW_A10_PIT_COUNT_RL_EN 0x2 -#define AW_A10_PIT_COUNT_CLR_EN 0x1 -#define AW_A10_PIT_COUNT_LO 0xa4 -#define AW_A10_PIT_COUNT_HI 0xa8 - -#define AW_A10_PIT_TIMER_BASE 0x10 -#define AW_A10_PIT_TIMER_BASE_END \ - (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) - -#define AW_A10_PIT_DEFAULT_CLOCK 0x4 - typedef struct AwA10PITState AwA10PITState; typedef struct AwA10TimerContext { diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b31a0bcd43..00f7cc492d 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -24,6 +24,36 @@ #include "qemu/log.h" #include "qemu/module.h" +#define AW_A10_PIT_TIMER_NR 6 + +#define AW_A10_PIT_TIMER_IRQ_EN 0 +#define AW_A10_PIT_TIMER_IRQ_ST 0x4 + +#define AW_A10_PIT_TIMER_CONTROL 0x0 +#define AW_A10_PIT_TIMER_EN 0x1 +#define AW_A10_PIT_TIMER_RELOAD 0x2 +#define AW_A10_PIT_TIMER_MODE 0x80 + +#define AW_A10_PIT_TIMER_INTERVAL 0x4 +#define AW_A10_PIT_TIMER_COUNT 0x8 +#define AW_A10_PIT_WDOG_CONTROL 0x90 +#define AW_A10_PIT_WDOG_MODE 0x94 + +#define AW_A10_PIT_COUNT_CTL 0xa0 +#define AW_A10_PIT_COUNT_RL_EN 0x2 +#define AW_A10_PIT_COUNT_CLR_EN 0x1 +#define AW_A10_PIT_COUNT_LO 0xa4 +#define AW_A10_PIT_COUNT_HI 0xa8 + +#define AW_A10_PIT_TIMER_BASE 0x10 +#define AW_A10_PIT_TIMER_BASE_END \ + (AW_A10_PIT_TIMER_BASE * AW_A10_PIT_TIMER_NR + AW_A10_PIT_TIMER_COUNT) + +#define AW_A10_PIT_DEFAULT_CLOCK 0x4 + +#define AW_A10_PIT(obj) \ + OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) + static void a10_pit_update_irq(AwA10PITState *s) { int i; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 05/13] hw/timer/allwinner: Rename the ptimer field Date: Thu, 19 Dec 2019 19:51:19 +0100 Message-Id: <20191219185127.24388-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We will later use the 'timer' field name to access all the timer related fields. The name is already use, we need to rename first. 'ptimer' is a good name. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 34 ++++++++++++++-------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index c28ee5ca47..a60b9f3031 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -20,7 +20,7 @@ struct AwA10PITState { SysBusDevice parent_obj; /*< public >*/ qemu_irq irq[AW_PIT_TIMER_MAX]; - ptimer_state * timer[AW_PIT_TIMER_MAX]; + ptimer_state * ptimer[AW_PIT_TIMER_MAX]; AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 00f7cc492d..effdf91344 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -83,7 +83,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) case AW_A10_PIT_TIMER_INTERVAL: return s->interval[index]; case AW_A10_PIT_TIMER_COUNT: - s->count[index] = ptimer_get_count(s->timer[index]); + s->count[index] = ptimer_get_count(s->ptimer[index]); return s->count[index]; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -109,7 +109,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) return 0; } -/* Must be called inside a ptimer transaction block for s->timer[index] */ +/* Must be called inside a ptimer transaction block for s->ptimer[index] */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; @@ -119,7 +119,7 @@ static void a10_pit_set_freq(AwA10PITState *s, int index) source_freq = s->clk_freq[source]; if (source_freq) { - ptimer_set_freq(s->timer[index], source_freq / prescaler); + ptimer_set_freq(s->ptimer[index], source_freq / prescaler); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", __func__, source); @@ -148,27 +148,27 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: s->control[index] = value; - ptimer_transaction_begin(s->timer[index]); + ptimer_transaction_begin(s->ptimer[index]); a10_pit_set_freq(s, index); if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { - ptimer_set_count(s->timer[index], s->interval[index]); + ptimer_set_count(s->ptimer[index], s->interval[index]); } if (s->control[index] & AW_A10_PIT_TIMER_EN) { int oneshot = 0; if (s->control[index] & AW_A10_PIT_TIMER_MODE) { oneshot = 1; } - ptimer_run(s->timer[index], oneshot); + ptimer_run(s->ptimer[index], oneshot); } else { - ptimer_stop(s->timer[index]); + ptimer_stop(s->ptimer[index]); } - ptimer_transaction_commit(s->timer[index]); + ptimer_transaction_commit(s->ptimer[index]); break; case AW_A10_PIT_TIMER_INTERVAL: s->interval[index] = value; - ptimer_transaction_begin(s->timer[index]); - ptimer_set_limit(s->timer[index], s->interval[index], 1); - ptimer_transaction_commit(s->timer[index]); + ptimer_transaction_begin(s->ptimer[index]); + ptimer_set_limit(s->ptimer[index], s->interval[index], 1); + ptimer_transaction_commit(s->ptimer[index]); break; case AW_A10_PIT_TIMER_COUNT: s->count[index] = value; @@ -241,7 +241,7 @@ static const VMStateDescription vmstate_a10_pit = { VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_PTIMER_ARRAY(ptimer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; @@ -259,10 +259,10 @@ static void a10_pit_reset(DeviceState *dev) s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] = 0; s->count[i] = 0; - ptimer_transaction_begin(s->timer[i]); - ptimer_stop(s->timer[i]); + ptimer_transaction_begin(s->ptimer[i]); + ptimer_stop(s->ptimer[i]); a10_pit_set_freq(s, i); - ptimer_transaction_commit(s->timer[i]); + ptimer_transaction_commit(s->ptimer[i]); } s->watch_dog_mode = 0; s->watch_dog_control = 0; @@ -280,7 +280,7 @@ static void a10_pit_timer_cb(void *opaque) if (s->control[i] & AW_A10_PIT_TIMER_EN) { s->irq_status |= 1 << i; if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); + ptimer_stop(s->ptimer[i]); s->control[i] &= ~AW_A10_PIT_TIMER_EN; } a10_pit_update_irq(s); @@ -305,7 +305,7 @@ static void a10_pit_init(Object *obj) tc->container = s; tc->index = i; - s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT); + s->ptimer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT); } } From patchwork Thu Dec 19 18:51:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 06/13] hw/timer/allwinner: Rename 'timer_context' as 'timer' Date: Thu, 19 Dec 2019 19:51:20 +0100 Message-Id: <20191219185127.24388-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The previous 'timer' field has been renamed as 'ptimer'. The 'timer_context' can now be simplified as 'timer'. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 2 +- hw/timer/allwinner-a10-pit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index a60b9f3031..b5ac6898fa 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -21,7 +21,7 @@ struct AwA10PITState { /*< public >*/ qemu_irq irq[AW_PIT_TIMER_MAX]; ptimer_state * ptimer[AW_PIT_TIMER_MAX]; - AwA10TimerContext timer_context[AW_PIT_TIMER_MAX]; + AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index effdf91344..44e6eee3a8 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -301,7 +301,7 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - AwA10TimerContext *tc = &s->timer_context[i]; + AwA10TimerContext *tc = &s->timer[i]; tc->container = s; tc->index = i; From patchwork Thu Dec 19 18:51:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213669 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tlF1dLp9"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47f1X42zlDz9sTj for ; Fri, 20 Dec 2019 06:04:36 +1100 (AEDT) Received: from localhost ([::1]:46836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii16A-0005fo-8f for incoming@patchwork.ozlabs.org; Thu, 19 Dec 2019 14:04:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39968) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ii0ti-00078R-GQ for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ii0tg-00083J-Nj for qemu-devel@nongnu.org; Thu, 19 Dec 2019 13:51:42 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52233) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ii0tg-0007yc-F1; Thu, 19 Dec 2019 13:51:40 -0500 Received: by mail-wm1-x343.google.com with SMTP id p9so6523558wmc.2; Thu, 19 Dec 2019 10:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=tlF1dLp9sSYb8LMXVv7K7cDXZlqumuq9LifLg45AsPkz5CeM5+i6LSNjhc8gBBXPDo YsEcvuQ8Zx/AmvldOwOmHna/+YAIB1HQt/zbvalN2mgZNZof0MwB/fK6D99EhA7nowgx 1E6IWPASbpIk38Ci6t+AJRXyg7MuuJwNrDQ3ANnKhifhOH7r3hgihgFScbtwzqDebmsu Yh8PVGvAktM9Ot0bgGIFC4MxZCH/nyUU4fwJpE7+IGLIHX/PbMy+LXqyFD+hovWemJtu LP7BvI8zCl4Ju2l4vZUfsL2uRXassV8+/zdX81E7lTF8Yb0qIo+1Cxs2slS8jDuw9Vzp lasw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ut5YgBRvjV0s9vJYJb1Jm2VxjMe8Smrb/fftQKlotks=; b=l0nyZCRyJ6JkbBfp8AXW56Y5d9CQVflpNOYHa3iG3c5t3AbwsZ6lAA0HEW9fIiubng voFHB12Ou6yeuT4uzhY8t1c6zyejgmIWjlRgydWZfdsebX53/tVYO7siNwKn3Ka01pZR JLOfx2AtTcVUwB8HhOBO/R2iesjb2WfAqDeWyPuOIyi5SbytsyUu7yPFbMmrZBEYJ5El 9nfZLTL9EAcDttU2ZSBU92IpZeM8xt3X/m5S9GVnSduNmnn8Qgw+JXF0s+zMwGgaQ9H5 uluXlsmCo43se1kzDKVCXqk2PUhk3DuJW+D7TnBnfIYWNZRW0W4AbqRZqbd5tmltEskM eOIQ== X-Gm-Message-State: APjAAAUKXEtbDxsitxP1haJHg0GnOm9KrcYn2ZGDggMN2w/5mU/W0ql/ zFV2Cs2wUv0yGdDSnsG/aQn1BMlx X-Google-Smtp-Source: APXvYqwFJu/ocP0dt38fiw9hi6XsBa0pFZ0dZoHv5eBxSfExfizRYD91ZAkeJ4XoRUjOGNkp7kTN1A== X-Received: by 2002:a1c:7215:: with SMTP id n21mr12019344wmc.154.1576781498236; Thu, 19 Dec 2019 10:51:38 -0800 (PST) Received: from x1w.redhat.com (34.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 07/13] hw/timer/allwinner: Move timer specific fields into AwA10TimerContext Date: Thu, 19 Dec 2019 19:51:21 +0100 Message-Id: <20191219185127.24388-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move all the timer-related fields into the same structure. We scrambled the migration structure, so we need to increase the version_id. Signed-off-by: Philippe Mathieu-Daudé --- Before I was using g_new(), now I keep AW_PIT_TIMER_MAX so We might avoid this patch. --- include/hw/timer/allwinner-a10-pit.h | 10 +-- hw/timer/allwinner-a10-pit.c | 99 ++++++++++++++++------------ 2 files changed, 63 insertions(+), 46 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index b5ac6898fa..e0f864a954 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -13,23 +13,23 @@ typedef struct AwA10PITState AwA10PITState; typedef struct AwA10TimerContext { AwA10PITState *container; int index; + ptimer_state *ptimer; + qemu_irq irq; + uint32_t control; + uint32_t interval; + uint32_t count; } AwA10TimerContext; struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq[AW_PIT_TIMER_MAX]; - ptimer_state * ptimer[AW_PIT_TIMER_MAX]; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; uint32_t irq_enable; uint32_t irq_status; - uint32_t control[AW_PIT_TIMER_MAX]; - uint32_t interval[AW_PIT_TIMER_MAX]; - uint32_t count[AW_PIT_TIMER_MAX]; uint32_t watch_dog_mode; uint32_t watch_dog_control; uint32_t count_lo; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 44e6eee3a8..ea92fdda32 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -59,7 +59,8 @@ static void a10_pit_update_irq(AwA10PITState *s) int i; for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); + qemu_set_irq(s->timer[i].irq, + !!(s->irq_status & s->irq_enable & (1 << i))); } } @@ -79,12 +80,12 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) index -= 1; switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: - return s->control[index]; + return s->timer[index].control; case AW_A10_PIT_TIMER_INTERVAL: - return s->interval[index]; + return s->timer[index].interval; case AW_A10_PIT_TIMER_COUNT: - s->count[index] = ptimer_get_count(s->ptimer[index]); - return s->count[index]; + s->timer[index].count = ptimer_get_count(s->timer[index].ptimer); + return s->timer[index].count; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__, (int)offset); @@ -109,17 +110,17 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) return 0; } -/* Must be called inside a ptimer transaction block for s->ptimer[index] */ +/* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ static void a10_pit_set_freq(AwA10PITState *s, int index) { uint32_t prescaler, source, source_freq; - prescaler = 1 << extract32(s->control[index], 4, 3); - source = extract32(s->control[index], 2, 2); + prescaler = 1 << extract32(s->timer[index].control, 4, 3); + source = extract32(s->timer[index].control, 2, 2); source_freq = s->clk_freq[source]; if (source_freq) { - ptimer_set_freq(s->ptimer[index], source_freq / prescaler); + ptimer_set_freq(s->timer[index].ptimer, source_freq / prescaler); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", __func__, source); @@ -147,31 +148,33 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, index -= 1; switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: - s->control[index] = value; - ptimer_transaction_begin(s->ptimer[index]); + s->timer[index].control = value; + ptimer_transaction_begin(s->timer[index].ptimer); a10_pit_set_freq(s, index); - if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { - ptimer_set_count(s->ptimer[index], s->interval[index]); + if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { + ptimer_set_count(s->timer[index].ptimer, + s->timer[index].interval); } - if (s->control[index] & AW_A10_PIT_TIMER_EN) { + if (s->timer[index].control & AW_A10_PIT_TIMER_EN) { int oneshot = 0; - if (s->control[index] & AW_A10_PIT_TIMER_MODE) { + if (s->timer[index].control & AW_A10_PIT_TIMER_MODE) { oneshot = 1; } - ptimer_run(s->ptimer[index], oneshot); + ptimer_run(s->timer[index].ptimer, oneshot); } else { - ptimer_stop(s->ptimer[index]); + ptimer_stop(s->timer[index].ptimer); } - ptimer_transaction_commit(s->ptimer[index]); + ptimer_transaction_commit(s->timer[index].ptimer); break; case AW_A10_PIT_TIMER_INTERVAL: - s->interval[index] = value; - ptimer_transaction_begin(s->ptimer[index]); - ptimer_set_limit(s->ptimer[index], s->interval[index], 1); - ptimer_transaction_commit(s->ptimer[index]); + s->timer[index].interval = value; + ptimer_transaction_begin(s->timer[index].ptimer); + ptimer_set_limit(s->timer[index].ptimer, + s->timer[index].interval, 1); + ptimer_transaction_commit(s->timer[index].ptimer); break; case AW_A10_PIT_TIMER_COUNT: - s->count[index] = value; + s->timer[index].count = value; break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -226,22 +229,35 @@ static Property a10_pit_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription vmstate_aw_timer = { + .name = "aw_timer", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT32(control, AwA10TimerContext), + VMSTATE_UINT32(interval, AwA10TimerContext), + VMSTATE_UINT32(count, AwA10TimerContext), + VMSTATE_PTIMER(ptimer, AwA10TimerContext), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_a10_pit = { .name = "a10.pit", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(irq_enable, AwA10PITState), VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_PIT_TIMER_MAX), - VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_PIT_TIMER_MAX), - VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_PIT_TIMER_MAX), + VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, + AW_PIT_TIMER_MAX, + 0, vmstate_aw_timer, + AwA10TimerContext), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), VMSTATE_UINT32(count_hi, AwA10PITState), VMSTATE_UINT32(count_ctl, AwA10PITState), - VMSTATE_PTIMER_ARRAY(ptimer, AwA10PITState, AW_PIT_TIMER_MAX), VMSTATE_END_OF_LIST() } }; @@ -256,13 +272,13 @@ static void a10_pit_reset(DeviceState *dev) a10_pit_update_irq(s); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; - s->interval[i] = 0; - s->count[i] = 0; - ptimer_transaction_begin(s->ptimer[i]); - ptimer_stop(s->ptimer[i]); + s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; + s->timer[i].interval = 0; + s->timer[i].count = 0; + ptimer_transaction_begin(s->timer[i].ptimer); + ptimer_stop(s->timer[i].ptimer); a10_pit_set_freq(s, i); - ptimer_transaction_commit(s->ptimer[i]); + ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode = 0; s->watch_dog_control = 0; @@ -277,11 +293,11 @@ static void a10_pit_timer_cb(void *opaque) AwA10PITState *s = tc->container; uint8_t i = tc->index; - if (s->control[i] & AW_A10_PIT_TIMER_EN) { + if (s->timer[i].control & AW_A10_PIT_TIMER_EN) { s->irq_status |= 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->ptimer[i]); - s->control[i] &= ~AW_A10_PIT_TIMER_EN; + if (s->timer[i].control & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i].ptimer); + s->timer[i].control &= ~AW_A10_PIT_TIMER_EN; } a10_pit_update_irq(s); } @@ -294,7 +310,7 @@ static void a10_pit_init(Object *obj) uint8_t i; for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - sysbus_init_irq(sbd, &s->irq[i]); + sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); @@ -305,7 +321,8 @@ static void a10_pit_init(Object *obj) tc->container = s; tc->index = i; - s->ptimer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT); + s->timer[i].ptimer = ptimer_init(a10_pit_timer_cb, tc, + PTIMER_POLICY_DEFAULT); } } From patchwork Thu Dec 19 18:51:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 08/13] hw/timer/allwinner: Add a timer_count field Date: Thu, 19 Dec 2019 19:51:22 +0100 Message-Id: <20191219185127.24388-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To be able to support controllers with less than 6 timers, we need a field to be able to iterate over the different count. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index e0f864a954..8c64c33f01 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -24,6 +24,7 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ + size_t timer_count; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ea92fdda32..3f47588703 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -58,7 +58,7 @@ static void a10_pit_update_irq(AwA10PITState *s) { int i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { qemu_set_irq(s->timer[i].irq, !!(s->irq_status & s->irq_enable & (1 << i))); } @@ -271,7 +271,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status = 0; a10_pit_update_irq(s); - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; s->timer[i].interval = 0; s->timer[i].count = 0; @@ -309,14 +309,16 @@ static void a10_pit_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + s->timer_count = AW_A10_PIT_TIMER_NR; + + for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { AwA10TimerContext *tc = &s->timer[i]; tc->container = s; From patchwork Thu Dec 19 18:51:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 09/13] hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState Date: Thu, 19 Dec 2019 19:51:23 +0100 Message-Id: <20191219185127.24388-10-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This structure will be common to various Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 6 +++--- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 8c64c33f01..3a47633cc4 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -10,7 +10,7 @@ typedef struct AwA10PITState AwA10PITState; -typedef struct AwA10TimerContext { +typedef struct AllwinnerTmrState { AwA10PITState *container; int index; ptimer_state *ptimer; @@ -18,14 +18,14 @@ typedef struct AwA10TimerContext { uint32_t control; uint32_t interval; uint32_t count; -} AwA10TimerContext; +} AllwinnerTmrState; struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ size_t timer_count; - AwA10TimerContext timer[AW_PIT_TIMER_MAX]; + AllwinnerTmrState timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 3f47588703..ecfc198937 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -234,10 +234,10 @@ static const VMStateDescription vmstate_aw_timer = { .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { - VMSTATE_UINT32(control, AwA10TimerContext), - VMSTATE_UINT32(interval, AwA10TimerContext), - VMSTATE_UINT32(count, AwA10TimerContext), - VMSTATE_PTIMER(ptimer, AwA10TimerContext), + VMSTATE_UINT32(control, AllwinnerTmrState), + VMSTATE_UINT32(interval, AllwinnerTmrState), + VMSTATE_UINT32(count, AllwinnerTmrState), + VMSTATE_PTIMER(ptimer, AllwinnerTmrState), VMSTATE_END_OF_LIST() } }; @@ -252,7 +252,7 @@ static const VMStateDescription vmstate_a10_pit = { VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, AW_PIT_TIMER_MAX, 0, vmstate_aw_timer, - AwA10TimerContext), + AllwinnerTmrState), VMSTATE_UINT32(watch_dog_mode, AwA10PITState), VMSTATE_UINT32(watch_dog_control, AwA10PITState), VMSTATE_UINT32(count_lo, AwA10PITState), @@ -289,7 +289,7 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { - AwA10TimerContext *tc = opaque; + AllwinnerTmrState *tc = opaque; AwA10PITState *s = tc->container; uint8_t i = tc->index; @@ -319,7 +319,7 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { - AwA10TimerContext *tc = &s->timer[i]; + AllwinnerTmrState *tc = &s->timer[i]; tc->container = s; tc->index = i; From patchwork Thu Dec 19 18:51:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 10/13] hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState Date: Thu, 19 Dec 2019 19:51:24 +0100 Message-Id: <20191219185127.24388-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This structure will be common to various Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/allwinner-a10.h | 2 +- include/hw/timer/allwinner-a10-pit.h | 6 ++-- hw/timer/allwinner-a10-pit.c | 42 ++++++++++++++-------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 7d2d215630..28c043db39 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -30,7 +30,7 @@ typedef struct AwA10State { ARMCPU cpu; qemu_irq irq[AW_A10_PIC_INT_NR]; - AwA10PITState timer; + AllwinnerTmrCtrlState timer; AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 3a47633cc4..9e28c6697a 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -8,10 +8,10 @@ #define AW_PIT_TIMER_MAX 6 -typedef struct AwA10PITState AwA10PITState; +typedef struct AllwinnerTmrCtrlState AllwinnerTmrCtrlState; typedef struct AllwinnerTmrState { - AwA10PITState *container; + AllwinnerTmrCtrlState *container; int index; ptimer_state *ptimer; qemu_irq irq; @@ -20,7 +20,7 @@ typedef struct AllwinnerTmrState { uint32_t count; } AllwinnerTmrState; -struct AwA10PITState { +struct AllwinnerTmrCtrlState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ecfc198937..f2ac271e80 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -52,9 +52,9 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 #define AW_A10_PIT(obj) \ - OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT) + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) -static void a10_pit_update_irq(AwA10PITState *s) +static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -66,7 +66,7 @@ static void a10_pit_update_irq(AwA10PITState *s) static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AwA10PITState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); uint8_t index; switch (offset) { @@ -111,7 +111,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) } /* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ -static void a10_pit_set_freq(AwA10PITState *s, int index) +static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; @@ -130,7 +130,7 @@ static void a10_pit_set_freq(AwA10PITState *s, int index) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AwA10PITState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); uint8_t index; switch (offset) { @@ -222,10 +222,10 @@ static const MemoryRegionOps a10_pit_ops = { }; static Property a10_pit_properties[] = { - DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), - DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), - DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), - DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), + DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), + DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), + DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), + DEFINE_PROP_UINT32("clk3-freq", AllwinnerTmrCtrlState, clk_freq[3], 0), DEFINE_PROP_END_OF_LIST(), }; @@ -247,24 +247,24 @@ static const VMStateDescription vmstate_a10_pit = { .version_id = 2, .minimum_version_id = 2, .fields = (VMStateField[]) { - VMSTATE_UINT32(irq_enable, AwA10PITState), - VMSTATE_UINT32(irq_status, AwA10PITState), - VMSTATE_STRUCT_ARRAY(timer, AwA10PITState, + VMSTATE_UINT32(irq_enable, AllwinnerTmrCtrlState), + VMSTATE_UINT32(irq_status, AllwinnerTmrCtrlState), + VMSTATE_STRUCT_ARRAY(timer, AllwinnerTmrCtrlState, AW_PIT_TIMER_MAX, 0, vmstate_aw_timer, AllwinnerTmrState), - VMSTATE_UINT32(watch_dog_mode, AwA10PITState), - VMSTATE_UINT32(watch_dog_control, AwA10PITState), - VMSTATE_UINT32(count_lo, AwA10PITState), - VMSTATE_UINT32(count_hi, AwA10PITState), - VMSTATE_UINT32(count_ctl, AwA10PITState), + VMSTATE_UINT32(watch_dog_mode, AllwinnerTmrCtrlState), + VMSTATE_UINT32(watch_dog_control, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_lo, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_hi, AllwinnerTmrCtrlState), + VMSTATE_UINT32(count_ctl, AllwinnerTmrCtrlState), VMSTATE_END_OF_LIST() } }; static void a10_pit_reset(DeviceState *dev) { - AwA10PITState *s = AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s = AW_A10_PIT(dev); uint8_t i; s->irq_enable = 0; @@ -290,7 +290,7 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { AllwinnerTmrState *tc = opaque; - AwA10PITState *s = tc->container; + AllwinnerTmrCtrlState *s = tc->container; uint8_t i = tc->index; if (s->timer[i].control & AW_A10_PIT_TIMER_EN) { @@ -305,7 +305,7 @@ static void a10_pit_timer_cb(void *opaque) static void a10_pit_init(Object *obj) { - AwA10PITState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; @@ -341,7 +341,7 @@ static void a10_pit_class_init(ObjectClass *klass, void *data) static const TypeInfo a10_pit_info = { .name = TYPE_AW_A10_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AwA10PITState), + .instance_size = sizeof(AllwinnerTmrCtrlState), .instance_init = a10_pit_init, .class_init = a10_pit_class_init, }; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 11/13] hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device Date: Thu, 19 Dec 2019 19:51:25 +0100 Message-Id: <20191219185127.24388-12-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Extract the common code from the TYPE_AW_A10_PIT device into a new abstract device: TYPE_AW_COMMON_PIT, then use it as parent, so we inherit the same functionalities. Signed-off-by: Philippe Mathieu-Daudé --- At this point, the only fields we can modify are the timer_count and the region_size. Not enough to implement the H3 timer, since we need to move the WDOG register. Still some progress, so Niek can continue ;) --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 50 +++++++++++++++++++++++----- 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 9e28c6697a..8453a62706 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -4,6 +4,7 @@ #include "hw/ptimer.h" #include "hw/sysbus.h" +#define TYPE_AW_COMMON_PIT "allwinner-timer-controller" #define TYPE_AW_A10_PIT "allwinner-A10-timer" #define AW_PIT_TIMER_MAX 6 diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index f2ac271e80..ad409b96a1 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -54,6 +54,20 @@ #define AW_A10_PIT(obj) \ OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) +typedef struct AllwinnerTmrCtrlClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + size_t timer_count; + size_t region_size; +} AllwinnerTmrCtrlClass; + +#define AW_TIMER_CLASS(klass) \ + OBJECT_CLASS_CHECK(AllwinnerTmrCtrlClass, (klass), TYPE_AW_COMMON_PIT) +#define AW_TIMER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) + static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -303,19 +317,20 @@ static void a10_pit_timer_cb(void *opaque) } } -static void a10_pit_init(Object *obj) +static void aw_pit_instance_init(Object *obj) { AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; - s->timer_count = AW_A10_PIT_TIMER_NR; + s->timer_count = c->timer_count; for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, 0x400); + TYPE_AW_A10_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { @@ -328,26 +343,45 @@ static void a10_pit_init(Object *obj) } } -static void a10_pit_class_init(ObjectClass *klass, void *data) +static void aw_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = a10_pit_reset; dc->props = a10_pit_properties; - dc->desc = "allwinner a10 timer"; + dc->desc = "Allwinner Timer Controller"; dc->vmsd = &vmstate_a10_pit; } +static const TypeInfo allwinner_pit_info = { + .name = TYPE_AW_COMMON_PIT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = aw_pit_instance_init, + .instance_size = sizeof(AllwinnerTmrCtrlState), + .class_init = aw_timer_class_init, + .class_size = sizeof(AllwinnerTmrCtrlClass), + .abstract = true, +}; + +static void a10_pit_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AllwinnerTmrCtrlClass *atc = AW_TIMER_CLASS(klass); + + dc->desc = "Allwinner A10 Timer Controller"; + atc->timer_count = AW_A10_PIT_TIMER_NR; + atc->region_size = 0x400; +} + static const TypeInfo a10_pit_info = { .name = TYPE_AW_A10_PIT, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AllwinnerTmrCtrlState), - .instance_init = a10_pit_init, + .parent = TYPE_AW_COMMON_PIT, .class_init = a10_pit_class_init, }; static void a10_register_types(void) { + type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } From patchwork Thu Dec 19 18:51:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1213671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="i5YwH8bv"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47f1c41cLhz9sSn for ; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 12/13] hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() Date: Thu, 19 Dec 2019 19:51:26 +0100 Message-Id: <20191219185127.24388-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This macro is now used by different Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ad409b96a1..7413f046cc 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -51,8 +51,8 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 -#define AW_A10_PIT(obj) \ - OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) +#define AW_TIMER_CTRL(obj) \ + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_COMMON_PIT) typedef struct AllwinnerTmrCtrlClass { /*< private >*/ @@ -80,7 +80,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; switch (offset) { @@ -144,7 +144,7 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; switch (offset) { @@ -278,7 +278,7 @@ static const VMStateDescription vmstate_a10_pit = { static void a10_pit_reset(DeviceState *dev) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(dev); uint8_t i; s->irq_enable = 0; @@ -319,7 +319,7 @@ static void a10_pit_timer_cb(void *opaque) static void aw_pit_instance_init(Object *obj) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; @@ -330,7 +330,7 @@ static void aw_pit_instance_init(Object *obj) sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, c->region_size); + TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { From patchwork Thu Dec 19 18:51:27 2019 Content-Type: text/plain; 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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 13/13] hw/timer/allwinner: Rename functions not specific to the A10 SoC Date: Thu, 19 Dec 2019 19:51:27 +0100 Message-Id: <20191219185127.24388-14-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These functions are used by different Allwinner timer controllers, rename them. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/allwinner-a10-pit.c | 52 ++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 7413f046cc..dff534cfef 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -68,7 +68,7 @@ typedef struct AllwinnerTmrCtrlClass { #define AW_TIMER_GET_CLASS(obj) \ OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) -static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) +static void allwinner_timer_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -78,7 +78,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) } } -static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) +static uint64_t allwinner_timer_read(void *opaque, hwaddr offset, unsigned size) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; @@ -125,7 +125,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) } /* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ -static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) +static void allwinner_ptimer_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; @@ -141,8 +141,8 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) } } -static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void allwinner_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; @@ -150,11 +150,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -164,7 +164,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, case AW_A10_PIT_TIMER_CONTROL: s->timer[index].control = value; ptimer_transaction_begin(s->timer[index].ptimer); - a10_pit_set_freq(s, index); + allwinner_ptimer_set_freq(s, index); if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { ptimer_set_count(s->timer[index].ptimer, s->timer[index].interval); @@ -229,13 +229,13 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, } } -static const MemoryRegionOps a10_pit_ops = { - .read = a10_pit_read, - .write = a10_pit_write, +static const MemoryRegionOps allwinner_timer_ops = { + .read = allwinner_timer_read, + .write = allwinner_timer_write, .endianness = DEVICE_NATIVE_ENDIAN, }; -static Property a10_pit_properties[] = { +static Property allwinner_timer_properties[] = { DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), @@ -276,14 +276,14 @@ static const VMStateDescription vmstate_a10_pit = { } }; -static void a10_pit_reset(DeviceState *dev) +static void allwinner_timer_reset(DeviceState *dev) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(dev); uint8_t i; s->irq_enable = 0; s->irq_status = 0; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); for (i = 0; i < s->timer_count; i++) { s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; @@ -291,7 +291,7 @@ static void a10_pit_reset(DeviceState *dev) s->timer[i].count = 0; ptimer_transaction_begin(s->timer[i].ptimer); ptimer_stop(s->timer[i].ptimer); - a10_pit_set_freq(s, i); + allwinner_ptimer_set_freq(s, i); ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode = 0; @@ -301,7 +301,7 @@ static void a10_pit_reset(DeviceState *dev) s->count_ctl = 0; } -static void a10_pit_timer_cb(void *opaque) +static void allwinner_ptimer_cb(void *opaque) { AllwinnerTmrState *tc = opaque; AllwinnerTmrCtrlState *s = tc->container; @@ -313,11 +313,11 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i].ptimer); s->timer[i].control &= ~AW_A10_PIT_TIMER_EN; } - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); } } -static void aw_pit_instance_init(Object *obj) +static void allwinner_timer_instance_init(Object *obj) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); @@ -329,8 +329,8 @@ static void aw_pit_instance_init(Object *obj) for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } - memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_COMMON_PIT, c->region_size); + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_timer_ops, + s, TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { @@ -338,7 +338,7 @@ static void aw_pit_instance_init(Object *obj) tc->container = s; tc->index = i; - s->timer[i].ptimer = ptimer_init(a10_pit_timer_cb, tc, + s->timer[i].ptimer = ptimer_init(allwinner_ptimer_cb, tc, PTIMER_POLICY_DEFAULT); } } @@ -347,8 +347,8 @@ static void aw_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - dc->reset = a10_pit_reset; - dc->props = a10_pit_properties; + dc->reset = allwinner_timer_reset; + dc->props = allwinner_timer_properties; dc->desc = "Allwinner Timer Controller"; dc->vmsd = &vmstate_a10_pit; } @@ -356,7 +356,7 @@ static void aw_timer_class_init(ObjectClass *klass, void *data) static const TypeInfo allwinner_pit_info = { .name = TYPE_AW_COMMON_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_init = aw_pit_instance_init, + .instance_init = allwinner_timer_instance_init, .instance_size = sizeof(AllwinnerTmrCtrlState), .class_init = aw_timer_class_init, .class_size = sizeof(AllwinnerTmrCtrlClass), @@ -379,10 +379,10 @@ static const TypeInfo a10_pit_info = { .class_init = a10_pit_class_init, }; -static void a10_register_types(void) +static void allwinner_timer_register_types(void) { type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } -type_init(a10_register_types); +type_init(allwinner_timer_register_types);