From patchwork Thu Dec 19 17:01:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1213563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-516316-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="mhq7y/sD"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dyp96Spcz9sPL for ; Fri, 20 Dec 2019 04:01:37 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type; q=dns; s= default; b=OQ2CCPABgcfiD3c+/IA4zOODuWxwS9LaJsiejI2dNgFaUyKcBG2nI HDQkYkrcNoFWShIB80GQXe3HTJJ5t4FBdRl7LCMHrBHidGQVfDauoou5rEYcgPUc ykWCDiVEVOcxaLGJ8wHzQgfBPla2RAJ9wbfD4njctryIlK25B99s1Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type; s= default; bh=ZnHZLmi0WuoBeYXtkuxU76WaLi4=; b=mhq7y/sDsTs4ZBCwW7pb MspkkM5mJr2fg8LowtmwQ8CzNvZeWz1NbiiVDYjVIVagAQn79Fz2WmveWWPWVIbB vu9m9LxOqrNBm50bOVAFdfFQjx+c5BonAaMdE39mGBfZU3Gxdg3biA+UO16t8KYH Ht2ByEpxa6KA/GTNCtiMzYI= Received: (qmail 90052 invoked by alias); 19 Dec 2019 17:01:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 89960 invoked by uid 89); 19 Dec 2019 17:01:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: esa1.mentor.iphmx.com Received: from esa1.mentor.iphmx.com (HELO esa1.mentor.iphmx.com) (68.232.129.153) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 19 Dec 2019 17:01:24 +0000 IronPort-SDR: iHZedPYte/l8OPKziGx881shBbKoPpaYgicXGezapSIjFAFGXpXThePuuDM6e1Dc6aMSpmPxzM YsPUDRa0Mau7iWqwXVvarcH8+h9mrrNGgFByGgXt3n4Z22RhtK4aMyBYJizvPSQhdwgeoyKyv7 8ZGRb2X4xG97YLlaqMk+S+YjPhcUtoROSnSKRT3B2YQUfjXUWG1sXNLONE2rJ0s+R2bX4IZrOA VKj5RJB98b+xLFhC1CjXDwVeco9nQRIx/u4Z79KmDc3YLyH4yquzHpSxIURrHAeX5xDQDgXC7Y t2A= Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa1.mentor.iphmx.com with ESMTP; 19 Dec 2019 09:01:22 -0800 IronPort-SDR: o4mNr7J9zYxKOQbCZWu53HpHe8l63b+NSFkq5xp2RJPMfcXPzw1dvTiuCVmXXYlHllJfQs+3rF Z7nLLbOd/ZyyV0pMkckVKTBOWizKSNM1P72C+kjL+AbAMSXLtIBmh34+VGBPB7GAn5pb6tmFOJ p8cIUlql/VYmO9Mb6bT42LThNW/HwyWYES75SPFRiAVI3iXsUGHpaBXh9IOY9Av0ByLzy1qeok gTFd5OsbfWoBfwaJNTIFIHsQ0a+MEjzR9yDTmLCbWJNIgb4qPZ30OwWMWsWQ3+NDy4GvWg2hHZ LZo= From: Andrew Stubbs Subject: [committed, amdgcn] Allow constants in vector extends and truncates To: "gcc-patches@gcc.gnu.org" Message-ID: Date: Thu, 19 Dec 2019 17:01:13 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 This patch changes the operand predicates such that vector constants are permitted during compilation. This prevents ICEs caused by the compiler trying to emit such instructions without checking. The machine instruction does not accept constants, but it is expected that the RTL optimizers will remove such artefacts before that becomes a problem, and if not the register allocator will break it out when it checks the constraints. There's not observable change in the testsuite results, with this patch alone, but the fix is prerequisite to another patch I'm working on. Andrew Allow constants in amdgcn extends and truncates 2019-12-19 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (2): Change input predcate to gcn_alu_operand. (extend2): Likewise. (truncv64di2): Likewise. (truncv64di2_exec): Likewise. (v64di2): Likewise. (v64di2_exec): Likewise. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 369aae5bfc5..98dc3e0cb5f 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2491,18 +2491,18 @@ (truncate "trunc")]) (define_insn "2" - [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") (zero_convert:VEC_ALL1REG_INT_MODE - (match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))] + (match_operand:VEC_ALL1REG_INT_ALT 1 "gcn_alu_operand" " v")))] "" "v_mov_b32_sdwa\t%0, %1 dst_sel: dst_unused:UNUSED_PAD src0_sel:" [(set_attr "type" "vop_sdwa") (set_attr "length" "8")]) (define_insn "extend2" - [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") (sign_extend:VEC_ALL1REG_INT_MODE - (match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))] + (match_operand:VEC_ALL1REG_INT_ALT 1 "gcn_alu_operand" " v")))] "" "v_mov_b32_sdwa\t%0, sext(%1) src0_sel:" [(set_attr "type" "vop_sdwa") @@ -2515,7 +2515,7 @@ (define_insn_and_split "truncv64di2" [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") (truncate:VEC_ALL1REG_INT_MODE - (match_operand:V64DI 1 "register_operand" " v")))] + (match_operand:V64DI 1 "gcn_alu_operand" " v")))] "" "#" "reload_completed" @@ -2536,7 +2536,7 @@ [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v") (vec_merge:VEC_ALL1REG_INT_MODE (truncate:VEC_ALL1REG_INT_MODE - (match_operand:V64DI 1 "register_operand" " v")) + (match_operand:V64DI 1 "gcn_alu_operand" " v")) (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_or_unspec_operand" "U0") (match_operand:DI 3 "gcn_exec_operand" " e")))] @@ -2559,9 +2559,9 @@ (set_attr "length" "4")]) (define_insn_and_split "v64di2" - [(set (match_operand:V64DI 0 "register_operand" "=v") + [(set (match_operand:V64DI 0 "register_operand" "=v") (any_extend:V64DI - (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v")))] + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" " v")))] "" "#" "reload_completed" @@ -2584,12 +2584,12 @@ (set_attr "length" "12")]) (define_insn_and_split "v64di2_exec" - [(set (match_operand:V64DI 0 "register_operand" "=v") + [(set (match_operand:V64DI 0 "register_operand" "=v") (vec_merge:V64DI (any_extend:V64DI - (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v")) - (match_operand:V64DI 2 "gcn_alu_or_unspec_operand" "U0") - (match_operand:DI 3 "gcn_exec_operand" " e")))] + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" " v")) + (match_operand:V64DI 2 "gcn_alu_or_unspec_operand" "U0") + (match_operand:DI 3 "gcn_exec_operand" " e")))] "" "#" "reload_completed"