From patchwork Thu Dec 19 14:06:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1213425 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-516300-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="FZ9iXuIj"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dtwR6VTQz9sPh for ; Fri, 20 Dec 2019 01:06:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=hAAdhDLr8VTGhDd2G+CjewmnNgnGo/mVY8ki+4H6VTaxheH7Gf YAP8XJdvtqW37Ax4S57IXd2/4Nh+gQksCaIshLqcgPUEZNlQcjKDhbkGJydIwg2D UpCflQl1dnK+TADG1i4I/nftfc6Wn5TJy5Mi0z/ZUNr5CAEpQEuoEm/Ww= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=Kxbdzl2Al+DKzPbIJCatM7+p8+c=; b=FZ9iXuIjd5WcT2RJAC05 h9MiTKz5efywQazhnIHxB75u/7O0Xh5iTnL8dRy41H6IvMGS6wGbL3lCKBxvyPPN 2wBOAYhq7yaVGVXwqrkV/KuudIl+vPBqeSYuyZD5KxNzlHES2lY3dNEy165lk9lw t8NENIbkdzUg+fxci5swXdw= Received: (qmail 82108 invoked by alias); 19 Dec 2019 14:06:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 82099 invoked by uid 89); 19 Dec 2019 14:06:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=Stubbs, ams@codesourcery.com, stubbs, amscodesourcerycom X-HELO: esa4.mentor.iphmx.com Received: from esa4.mentor.iphmx.com (HELO esa4.mentor.iphmx.com) (68.232.137.252) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 19 Dec 2019 14:06:38 +0000 IronPort-SDR: bz4pj8v0DRXjUuynyTM5+QtluTKO4fXx/2OIGZS5e+PbWiOnOR4zAGiiWaGkasUoieS6ba04OO e6+j5Oq73TeU1P4k/HGuHQHSd9NpXc/R3DUmqQXrk1HMO+qIR1mDDwRMDyRGWgy1FTStz9z0da gBea5A+bm34tLYdctprOO2IbrNhP4JeKY+qyvXti94lWNrD6RwC7+xRI3d26fW4Xfy65QQIQJT tjF1/+Y6n2YK1i/FWi548ymP7nXBQ5UlVwtwj23Vp4o13/CbggqWiREMEQUfpsbd7i+PRQOuQ4 a8Q= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa4.mentor.iphmx.com with ESMTP; 19 Dec 2019 06:06:37 -0800 IronPort-SDR: ZP2SUQMUOz2bVYLGodIccZQ5sg1u+4cNqqhXq+ZwJHhmkEpscfVRlX2M4b2L/5Gg09BYqnl/tD +vXsAZvbMZhCOmiJnTKBKjjArKj+H/KvFf2OhzJpXe1J9gzbsBokp+1wKuFVzqLixyQ4FXBcJK uxVZJ7htbeYDKIuPI9SHbs5drJK7fQo/dy8yA7+6AFpHP++SzjRsjAg7wG+oa0daG6wAkVKYxj b2nwz7TdWG4Rj8ub6WZMZoC1dVyUxcJcKCY9Te8uXQm+kDt0CTFAyaR7V602NNOXGMyaNjK4fC aPE= To: "gcc-patches@gcc.gnu.org" From: Andrew Stubbs Subject: [committed, amdgcn] Add sub-dword add/sub patterns Message-ID: Date: Thu, 19 Dec 2019 14:06:31 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 This patch add vector add and sub instruction patterns for V64QI and V64HI modes. The instructions used are actually 32-bit as GCN does not support sub-dword operations in this way, but I believe it ought to be safe for these operations, provided that the excess bits are ignored properly elsewhere. This results in 80 new test passes. There are a few regressions from vectorization tests that took a different code path and encountered another missing instruction. Andrew Implement sub-dword add/sub on amdgcn 2019-12-19 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (addv64si3): Rename to ... (add3): ... this, and use VEC_ALL1REG_INT_MODE. (addv64si3_dup): Rename to ... (add3_dup): ... this, and use VEC_ALL1REG_INT_MODE. (subv64si3): Rename to ... (sub3): ... this, and use VEC_ALL1REG_INT_MODE. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 3b3be8a9e36..00a7604d686 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1036,23 +1036,23 @@ ;; }}} ;; {{{ ALU special case: add/sub -(define_insn "addv64si3" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (plus:V64SI - (match_operand:V64SI 1 "register_operand" "% v") - (match_operand:V64SI 2 "gcn_alu_operand" "vSvB"))) +(define_insn "add3" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (plus:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" "% v") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" "vSvB"))) (clobber (reg:DI VCC_REG))] "" "v_add%^_u32\t%0, vcc, %2, %1" [(set_attr "type" "vop2") (set_attr "length" "8")]) -(define_insn "addv64si3_dup" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (plus:V64SI - (vec_duplicate:V64SI - (match_operand:SI 2 "gcn_alu_operand" "SvB")) - (match_operand:V64SI 1 "register_operand" " v"))) +(define_insn "add3_dup" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (plus:VEC_ALL1REG_INT_MODE + (vec_duplicate:VEC_ALL1REG_INT_MODE + (match_operand: 2 "gcn_alu_operand" "SvB")) + (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v"))) (clobber (reg:DI VCC_REG))] "" "v_add%^_u32\t%0, vcc, %2, %1" @@ -1158,11 +1158,11 @@ [(set_attr "type" "vop2,vop3b") (set_attr "length" "4,8")]) -(define_insn "subv64si3" - [(set (match_operand:V64SI 0 "register_operand" "= v, v") - (minus:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "vSvB, v") - (match_operand:V64SI 2 "gcn_alu_operand" " v,vSvB"))) +(define_insn "sub3" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v, v") + (minus:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "vSvB, v") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " v,vSvB"))) (clobber (reg:DI VCC_REG))] "" "@