From patchwork Wed Dec 18 01:06:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Bergner X-Patchwork-Id: 1211869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-516163-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="WBY/S2qE"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47cxfw2kFJz9sR4 for ; Wed, 18 Dec 2019 12:06:46 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=cJFDu7xtytqVAThG i3hDlim8mEKr/ZnBEvzFexj0KHdwCm4JRNv1qa/G/nLk+WbUNwTPVKV1zHBbB3PH n7FqiT+RuMmLY4JO+qF+oNqiX3EVCi0fAB4l2z2MGLic5CSrum8Kt0nmw//2/Efv bjYrkMiTRqa6XXYGObwUU/BgrcY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type :content-transfer-encoding; s=default; bh=yZjty785j+NH9f6VjakNb5 SI4WQ=; b=WBY/S2qEF5idPSaioU3rPHGSzid8Tqzsv5mRWbelj2tQndRbesypGu IgQEv1sMjkCsXYpHHIvfULwRYoWVIzIQe0NH/M7d+8nWDNjCtxOtjVRkeEGFqAq2 gZWQkRJIon2E6r9wBcj/H4LsmepaNSf8y9z8WNPYxv3OM1wWvAiaE= Received: (qmail 98720 invoked by alias); 18 Dec 2019 01:06:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 98709 invoked by uid 89); 18 Dec 2019 01:06:34 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, SPF_PASS, UPPERCASE_50_75 autolearn=ham version=3.3.1 spammy=maltivec X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 18 Dec 2019 01:06:27 +0000 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBI12IBo122931; Tue, 17 Dec 2019 20:06:24 -0500 Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wy9vyrcy5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2019 20:06:24 -0500 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBI14l5g004555; Wed, 18 Dec 2019 01:06:23 GMT Received: from b03cxnp07028.gho.boulder.ibm.com (b03cxnp07028.gho.boulder.ibm.com [9.17.130.15]) by ppma04dal.us.ibm.com with ESMTP id 2wvqc6sf0g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 01:06:23 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBI16LHG33751534 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 01:06:21 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E5F86E04C; Wed, 18 Dec 2019 01:06:21 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A08F76E050; Wed, 18 Dec 2019 01:06:20 +0000 (GMT) Received: from [9.160.43.33] (unknown [9.160.43.33]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 01:06:20 +0000 (GMT) To: GCC Patches Cc: Segher Boessenkool From: Peter Bergner Subject: [PATCH] rs6000: Fix PR92923, __builtin_vec_xor() causes subregs to be used when not using V4SImode vectors Message-ID: Date: Tue, 17 Dec 2019 19:06:19 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 X-IsSubscribed: yes PR92923 shows a problem where builtin function usage is causing performance problems due to unneeded subreg usage. These are being caused by the front- end emitting unneeded VIEW_CONVERT_EXPR's on the builtin functions operands. These in tern where caused by a lack of overloaded builtin entries in the rs6000 backend. The following patch adds just enough new definitions to match what our vector documentation says we must support. I have also added new test cases so that we will catch any regressions in this area. This passed bootstrap and regression testing with no errors. Ok for trunk? This is a bug on the release branches too, but given how big this patch ended up being, I don't think we want to backport this. Peter gcc/ PR target/92923 * config/rs6000/rs6000-builtin.def (VAND, VANDC, VNOR, VOR, VXOR): Delete. (EQV_V16QI_UNS, EQV_V8HI_UNS, EQV_V4SI_UNS, EQV_V2DI_UNS, EQV_V1TI_UNS, NAND_V16QI_UNS, NAND_V8HI_UNS, NAND_V4SI_UNS, NAND_V2DI_UNS, NAND_V1TI_UNS, ORC_V16QI_UNS, ORC_V8HI_UNS, ORC_V4SI_UNS, ORC_V2DI_UNS, ORC_V1TI_UNS, VAND_V16QI_UNS, VAND_V16QI, VAND_V8HI_UNS, VAND_V8HI, VAND_V4SI_UNS, VAND_V4SI, VAND_V2DI_UNS, VAND_V2DI, VAND_V4SF, VAND_V2DF, VANDC_V16QI_UNS, VANDC_V16QI, VANDC_V8HI_UNS, VANDC_V8HI, VANDC_V4SI_UNS, VANDC_V4SI, VANDC_V2DI_UNS, VANDC_V2DI, VANDC_V4SF, VANDC_V2DF, VNOR_V16QI_UNS, VNOR_V16QI, VNOR_V8HI_UNS, VNOR_V8HI, VNOR_V4SI_UNS, VNOR_V4SI, VNOR_V2DI_UNS, VNOR_V2DI, VNOR_V4SF, VNOR_V2DF, VOR_V16QI_UNS, VOR_V16QI, VOR_V8HI_UNS, VOR_V8HI, VOR_V4SI_UNS, VOR_V4SI, VOR_V2DI_UNS, VOR_V2DI, VOR_V4SF, VOR_V2DF, VXOR_V16QI_UNS, VXOR_V16QI, VXOR_V8HI_UNS, VXOR_V8HI, VXOR_V4SI_UNS, VXOR_V4SI, VXOR_V2DI_UNS, VXOR_V2DI, VXOR_V4SF, VXOR_V2DF): Add definitions. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins) : Remove. : Add definitions. : Change unsigned usages to use the new *_UNS definition names. (rs6000_gimple_fold_builtin) : Use new definition names. (builtin_function_type) : Handle unsigned builtins. gcc/testsuite/ PR target/92923 * gcc.target/powerpc/pr92923-1.c: New test. * gcc.target/powerpc/pr92923-2.c: Likewise. Index: gcc/config/rs6000/rs6000-builtin.def =================================================================== --- gcc/config/rs6000/rs6000-builtin.def (revision 279479) +++ gcc/config/rs6000/rs6000-builtin.def (working copy) @@ -1000,8 +1000,26 @@ BU_ALTIVEC_2 (VADDUHS, "vadduhs", BU_ALTIVEC_2 (VADDSHS, "vaddshs", CONST, altivec_vaddshs) BU_ALTIVEC_2 (VADDUWS, "vadduws", CONST, altivec_vadduws) BU_ALTIVEC_2 (VADDSWS, "vaddsws", CONST, altivec_vaddsws) -BU_ALTIVEC_2 (VAND, "vand", CONST, andv4si3) -BU_ALTIVEC_2 (VANDC, "vandc", CONST, andcv4si3) +BU_ALTIVEC_2 (VAND_V16QI_UNS, "vand_v16qi_uns", CONST, andv16qi3) +BU_ALTIVEC_2 (VAND_V16QI, "vand_v16qi", CONST, andv16qi3) +BU_ALTIVEC_2 (VAND_V8HI_UNS, "vand_v8hi_uns", CONST, andv8hi3) +BU_ALTIVEC_2 (VAND_V8HI, "vand_v8hi", CONST, andv8hi3) +BU_ALTIVEC_2 (VAND_V4SI_UNS, "vand_v4si_uns", CONST, andv4si3) +BU_ALTIVEC_2 (VAND_V4SI, "vand_v4si", CONST, andv4si3) +BU_ALTIVEC_2 (VAND_V2DI_UNS, "vand_v2di_uns", CONST, andv2di3) +BU_ALTIVEC_2 (VAND_V2DI, "vand_v2di", CONST, andv2di3) +BU_ALTIVEC_2 (VAND_V4SF, "vand_v4sf", CONST, andv4sf3) +BU_ALTIVEC_2 (VAND_V2DF, "vand_v2df", CONST, andv2df3) +BU_ALTIVEC_2 (VANDC_V16QI_UNS,"vandc_v16qi_uns",CONST, andcv16qi3) +BU_ALTIVEC_2 (VANDC_V16QI, "vandc_v16qi", CONST, andcv16qi3) +BU_ALTIVEC_2 (VANDC_V8HI_UNS, "vandc_v8hi_uns", CONST, andcv8hi3) +BU_ALTIVEC_2 (VANDC_V8HI, "vandc_v8hi", CONST, andcv8hi3) +BU_ALTIVEC_2 (VANDC_V4SI_UNS, "vandc_v4si_uns", CONST, andcv4si3) +BU_ALTIVEC_2 (VANDC_V4SI, "vandc_v4si", CONST, andcv4si3) +BU_ALTIVEC_2 (VANDC_V2DI_UNS, "vandc_v2di_uns", CONST, andcv2di3) +BU_ALTIVEC_2 (VANDC_V2DI, "vandc_v2di", CONST, andcv2di3) +BU_ALTIVEC_2 (VANDC_V4SF, "vandc_v4sf", CONST, andcv4sf3) +BU_ALTIVEC_2 (VANDC_V2DF, "vandc_v2df", CONST, andcv2df3) BU_ALTIVEC_2 (VAVGUB, "vavgub", CONST, uavgv16qi3_ceil) BU_ALTIVEC_2 (VAVGSB, "vavgsb", CONST, avgv16qi3_ceil) BU_ALTIVEC_2 (VAVGUH, "vavguh", CONST, uavgv8hi3_ceil) @@ -1057,8 +1075,27 @@ BU_ALTIVEC_2 (VMULOUH, "vmulouh", BU_ALTIVEC_2 (VMULOSH, "vmulosh", CONST, vec_widen_smult_odd_v8hi) BU_P8V_AV_2 (VMULOUW, "vmulouw", CONST, vec_widen_umult_odd_v4si) BU_P8V_AV_2 (VMULOSW, "vmulosw", CONST, vec_widen_smult_odd_v4si) -BU_ALTIVEC_2 (VNOR, "vnor", CONST, norv4si3) -BU_ALTIVEC_2 (VOR, "vor", CONST, iorv4si3) +BU_ALTIVEC_2 (VNOR_V16QI_UNS, "vnor_v16qi_uns", CONST, norv16qi3) +BU_ALTIVEC_2 (VNOR_V16QI, "vnor_v16qi", CONST, norv16qi3) +BU_ALTIVEC_2 (VNOR_V8HI_UNS, "vnor_v8hi_uns", CONST, norv8hi3) +BU_ALTIVEC_2 (VNOR_V8HI, "vnor_v8hi", CONST, norv8hi3) +BU_ALTIVEC_2 (VNOR_V4SI_UNS, "vnor_v4si_uns", CONST, norv4si3) +BU_ALTIVEC_2 (VNOR_V4SI, "vnor_v4si", CONST, norv4si3) +BU_ALTIVEC_2 (VNOR_V2DI_UNS, "vnor_v2di_uns", CONST, norv2di3) +BU_ALTIVEC_2 (VNOR_V2DI, "vnor_v2di", CONST, norv2di3) +BU_ALTIVEC_2 (VNOR_V4SF, "vnor_v4sf", CONST, norv4sf3) +BU_ALTIVEC_2 (VNOR_V2DF, "vnor_v2df", CONST, norv2df3) +BU_ALTIVEC_2 (VOR_V16QI_UNS, "vor_v16qi_uns", CONST, iorv16qi3) +BU_ALTIVEC_2 (VOR_V16QI, "vor_v16qi", CONST, iorv16qi3) +BU_ALTIVEC_2 (VOR_V8HI_UNS, "vor_v8hi_uns", CONST, iorv8hi3) +BU_ALTIVEC_2 (VOR_V8HI, "vor_v8hi", CONST, iorv8hi3) +BU_ALTIVEC_2 (VOR_V4SI_UNS, "vor_v4si_uns", CONST, iorv4si3) +BU_ALTIVEC_2 (VOR_V4SI, "vor_v4si", CONST, iorv4si3) +BU_ALTIVEC_2 (VOR_V2DI_UNS, "vor_v2di_uns", CONST, iorv2di3) +BU_ALTIVEC_2 (VOR_V2DI, "vor_v2di", CONST, iorv2di3) +BU_ALTIVEC_2 (VOR_V4SF, "vor_v4sf", CONST, iorv4sf3) +BU_ALTIVEC_2 (VOR_V2DF, "vor_v2df", CONST, iorv2df3) + BU_ALTIVEC_2 (VPKUHUM, "vpkuhum", CONST, altivec_vpkuhum) BU_ALTIVEC_2 (VPKUWUM, "vpkuwum", CONST, altivec_vpkuwum) BU_ALTIVEC_2 (VPKPX, "vpkpx", CONST, altivec_vpkpx) @@ -1105,7 +1142,17 @@ BU_ALTIVEC_2 (VSUM4SHS, "vsum4shs" BU_ALTIVEC_2 (VSUM2SWS, "vsum2sws", CONST, altivec_vsum2sws) BU_ALTIVEC_2 (VSUMSWS, "vsumsws", CONST, altivec_vsumsws) BU_ALTIVEC_2 (VSUMSWS_BE, "vsumsws_be", CONST, altivec_vsumsws_direct) -BU_ALTIVEC_2 (VXOR, "vxor", CONST, xorv4si3) +BU_ALTIVEC_2 (VXOR_V16QI_UNS, "vxor_v16qi_uns", CONST, xorv16qi3) +BU_ALTIVEC_2 (VXOR_V16QI, "vxor_v16qi", CONST, xorv16qi3) +BU_ALTIVEC_2 (VXOR_V8HI_UNS, "vxor_v8hi_uns", CONST, xorv8hi3) +BU_ALTIVEC_2 (VXOR_V8HI, "vxor_v8hi", CONST, xorv8hi3) +BU_ALTIVEC_2 (VXOR_V4SI_UNS, "vxor_v4si_uns", CONST, xorv4si3) +BU_ALTIVEC_2 (VXOR_V4SI, "vxor_v4si", CONST, xorv4si3) +BU_ALTIVEC_2 (VXOR_V2DI_UNS, "vxor_v2di_uns", CONST, xorv2di3) +BU_ALTIVEC_2 (VXOR_V2DI, "vxor_v2di", CONST, xorv2di3) +BU_ALTIVEC_2 (VXOR_V4SF, "vxor_v4sf", CONST, xorv4sf3) +BU_ALTIVEC_2 (VXOR_V2DF, "vxor_v2df", CONST, xorv2df3) + BU_ALTIVEC_2 (COPYSIGN_V4SF, "copysignfp", CONST, vector_copysignv4sf3) /* Altivec ABS functions. */ @@ -1923,26 +1970,41 @@ BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3) BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm) +BU_P8V_AV_2 (EQV_V16QI_UNS, "eqv_v16qi_uns",CONST, eqvv16qi3) BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3) +BU_P8V_AV_2 (EQV_V8HI_UNS, "eqv_v8hi_uns", CONST, eqvv8hi3) BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3) +BU_P8V_AV_2 (EQV_V4SI_UNS, "eqv_v4si_uns", CONST, eqvv4si3) BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3) +BU_P8V_AV_2 (EQV_V2DI_UNS, "eqv_v2di_uns", CONST, eqvv2di3) BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3) +BU_P8V_AV_2 (EQV_V1TI_UNS, "eqv_v1ti_uns", CONST, eqvv1ti3) BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3) BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3) BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3) -BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3) -BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3) -BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3) -BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3) -BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3) -BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3) -BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3) +BU_P8V_AV_2 (NAND_V16QI_UNS, "nand_v16qi_uns", CONST, nandv16qi3) +BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3) +BU_P8V_AV_2 (NAND_V8HI_UNS, "nand_v8hi_uns", CONST, nandv8hi3) +BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3) +BU_P8V_AV_2 (NAND_V4SI_UNS, "nand_v4si_uns", CONST, nandv4si3) +BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3) +BU_P8V_AV_2 (NAND_V2DI_UNS, "nand_v2di_uns", CONST, nandv2di3) +BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3) +BU_P8V_AV_2 (NAND_V1TI_UNS, "nand_v1ti_uns", CONST, nandv1ti3) +BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3) +BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3) +BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3) +BU_P8V_AV_2 (ORC_V16QI_UNS, "orc_v16qi_uns",CONST, orcv16qi3) BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3) +BU_P8V_AV_2 (ORC_V8HI_UNS, "orc_v8hi_uns", CONST, orcv8hi3) BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3) +BU_P8V_AV_2 (ORC_V4SI_UNS, "orc_v4si_uns", CONST, orcv4si3) BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3) +BU_P8V_AV_2 (ORC_V2DI_UNS, "orc_v2di_uns", CONST, orcv2di3) BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3) +BU_P8V_AV_2 (ORC_V1TI_UNS, "orc_v1ti_uns", CONST, orcv1ti3) BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3) BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3) BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) Index: gcc/config/rs6000/rs6000-call.c =================================================================== --- gcc/config/rs6000/rs6000-call.c (revision 279479) +++ gcc/config/rs6000/rs6000-call.c (working copy) @@ -635,142 +635,145 @@ const struct altivec_builtin_types altiv RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB, @@ -1826,110 +1829,112 @@ const struct altivec_builtin_types altiv { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, @@ -2795,73 +2800,79 @@ const struct altivec_builtin_types altiv ~RS6000_BTI_unsigned_V16QI, 0 }, { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, /* Ternary AltiVec/VSX builtins. */ @@ -4101,15 +4112,15 @@ const struct altivec_builtin_types altiv RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, @@ -4118,15 +4129,15 @@ const struct altivec_builtin_types altiv RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, @@ -4135,15 +4146,15 @@ const struct altivec_builtin_types altiv RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, @@ -4152,15 +4163,15 @@ const struct altivec_builtin_types altiv RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, @@ -4174,16 +4185,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, @@ -4191,16 +4202,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -4208,16 +4219,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, @@ -4225,16 +4236,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, @@ -4247,16 +4258,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, @@ -4264,16 +4275,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -4281,16 +4292,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, @@ -4298,16 +4309,16 @@ const struct altivec_builtin_types altiv RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, @@ -10667,7 +10678,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ gsi_replace (gsi, g, true); return true; /* Flavors of vec_and. */ - case ALTIVEC_BUILTIN_VAND: + case ALTIVEC_BUILTIN_VAND_V16QI_UNS: + case ALTIVEC_BUILTIN_VAND_V16QI: + case ALTIVEC_BUILTIN_VAND_V8HI_UNS: + case ALTIVEC_BUILTIN_VAND_V8HI: + case ALTIVEC_BUILTIN_VAND_V4SI_UNS: + case ALTIVEC_BUILTIN_VAND_V4SI: + case ALTIVEC_BUILTIN_VAND_V2DI_UNS: + case ALTIVEC_BUILTIN_VAND_V2DI: + case ALTIVEC_BUILTIN_VAND_V4SF: + case ALTIVEC_BUILTIN_VAND_V2DF: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -10676,7 +10696,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ gsi_replace (gsi, g, true); return true; /* Flavors of vec_andc. */ - case ALTIVEC_BUILTIN_VANDC: + case ALTIVEC_BUILTIN_VANDC_V16QI_UNS: + case ALTIVEC_BUILTIN_VANDC_V16QI: + case ALTIVEC_BUILTIN_VANDC_V8HI_UNS: + case ALTIVEC_BUILTIN_VANDC_V8HI: + case ALTIVEC_BUILTIN_VANDC_V4SI_UNS: + case ALTIVEC_BUILTIN_VANDC_V4SI: + case ALTIVEC_BUILTIN_VANDC_V2DI_UNS: + case ALTIVEC_BUILTIN_VANDC_V2DI: + case ALTIVEC_BUILTIN_VANDC_V4SF: + case ALTIVEC_BUILTIN_VANDC_V2DF: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -10690,12 +10719,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ return true; /* Flavors of vec_nand. */ case P8V_BUILTIN_VEC_NAND: + case P8V_BUILTIN_NAND_V16QI_UNS: case P8V_BUILTIN_NAND_V16QI: + case P8V_BUILTIN_NAND_V8HI_UNS: case P8V_BUILTIN_NAND_V8HI: + case P8V_BUILTIN_NAND_V4SI_UNS: case P8V_BUILTIN_NAND_V4SI: + case P8V_BUILTIN_NAND_V2DI_UNS: + case P8V_BUILTIN_NAND_V2DI: case P8V_BUILTIN_NAND_V4SF: case P8V_BUILTIN_NAND_V2DF: - case P8V_BUILTIN_NAND_V2DI: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -10708,7 +10741,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ gsi_replace (gsi, g, true); return true; /* Flavors of vec_or. */ - case ALTIVEC_BUILTIN_VOR: + case ALTIVEC_BUILTIN_VOR_V16QI_UNS: + case ALTIVEC_BUILTIN_VOR_V16QI: + case ALTIVEC_BUILTIN_VOR_V8HI_UNS: + case ALTIVEC_BUILTIN_VOR_V8HI: + case ALTIVEC_BUILTIN_VOR_V4SI_UNS: + case ALTIVEC_BUILTIN_VOR_V4SI: + case ALTIVEC_BUILTIN_VOR_V2DI_UNS: + case ALTIVEC_BUILTIN_VOR_V2DI: + case ALTIVEC_BUILTIN_VOR_V4SF: + case ALTIVEC_BUILTIN_VOR_V2DF: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -10717,12 +10759,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ gsi_replace (gsi, g, true); return true; /* flavors of vec_orc. */ + case P8V_BUILTIN_ORC_V16QI_UNS: case P8V_BUILTIN_ORC_V16QI: + case P8V_BUILTIN_ORC_V8HI_UNS: case P8V_BUILTIN_ORC_V8HI: + case P8V_BUILTIN_ORC_V4SI_UNS: case P8V_BUILTIN_ORC_V4SI: + case P8V_BUILTIN_ORC_V2DI_UNS: + case P8V_BUILTIN_ORC_V2DI: case P8V_BUILTIN_ORC_V4SF: case P8V_BUILTIN_ORC_V2DF: - case P8V_BUILTIN_ORC_V2DI: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -10735,7 +10781,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ gsi_replace (gsi, g, true); return true; /* Flavors of vec_xor. */ - case ALTIVEC_BUILTIN_VXOR: + case ALTIVEC_BUILTIN_VXOR_V16QI_UNS: + case ALTIVEC_BUILTIN_VXOR_V16QI: + case ALTIVEC_BUILTIN_VXOR_V8HI_UNS: + case ALTIVEC_BUILTIN_VXOR_V8HI: + case ALTIVEC_BUILTIN_VXOR_V4SI_UNS: + case ALTIVEC_BUILTIN_VXOR_V4SI: + case ALTIVEC_BUILTIN_VXOR_V2DI_UNS: + case ALTIVEC_BUILTIN_VXOR_V2DI: + case ALTIVEC_BUILTIN_VXOR_V4SF: + case ALTIVEC_BUILTIN_VXOR_V2DF: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -10744,7 +10799,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_ gsi_replace (gsi, g, true); return true; /* Flavors of vec_nor. */ - case ALTIVEC_BUILTIN_VNOR: + case ALTIVEC_BUILTIN_VNOR_V16QI_UNS: + case ALTIVEC_BUILTIN_VNOR_V16QI: + case ALTIVEC_BUILTIN_VNOR_V8HI_UNS: + case ALTIVEC_BUILTIN_VNOR_V8HI: + case ALTIVEC_BUILTIN_VNOR_V4SI_UNS: + case ALTIVEC_BUILTIN_VNOR_V4SI: + case ALTIVEC_BUILTIN_VNOR_V2DI_UNS: + case ALTIVEC_BUILTIN_VNOR_V2DI: + case ALTIVEC_BUILTIN_VNOR_V4SF: + case ALTIVEC_BUILTIN_VNOR_V2DF: arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); lhs = gimple_call_lhs (stmt); @@ -12799,6 +12863,41 @@ builtin_function_type (machine_mode mode case ALTIVEC_BUILTIN_VMINUW: case P8V_BUILTIN_VMAXUD: case P8V_BUILTIN_VMINUD: + case ALTIVEC_BUILTIN_VAND_V16QI_UNS: + case ALTIVEC_BUILTIN_VAND_V8HI_UNS: + case ALTIVEC_BUILTIN_VAND_V4SI_UNS: + case ALTIVEC_BUILTIN_VAND_V2DI_UNS: + case ALTIVEC_BUILTIN_VANDC_V16QI_UNS: + case ALTIVEC_BUILTIN_VANDC_V8HI_UNS: + case ALTIVEC_BUILTIN_VANDC_V4SI_UNS: + case ALTIVEC_BUILTIN_VANDC_V2DI_UNS: + case ALTIVEC_BUILTIN_VNOR_V16QI_UNS: + case ALTIVEC_BUILTIN_VNOR_V8HI_UNS: + case ALTIVEC_BUILTIN_VNOR_V4SI_UNS: + case ALTIVEC_BUILTIN_VNOR_V2DI_UNS: + case ALTIVEC_BUILTIN_VOR_V16QI_UNS: + case ALTIVEC_BUILTIN_VOR_V8HI_UNS: + case ALTIVEC_BUILTIN_VOR_V4SI_UNS: + case ALTIVEC_BUILTIN_VOR_V2DI_UNS: + case ALTIVEC_BUILTIN_VXOR_V16QI_UNS: + case ALTIVEC_BUILTIN_VXOR_V8HI_UNS: + case ALTIVEC_BUILTIN_VXOR_V4SI_UNS: + case ALTIVEC_BUILTIN_VXOR_V2DI_UNS: + case P8V_BUILTIN_EQV_V16QI_UNS: + case P8V_BUILTIN_EQV_V8HI_UNS: + case P8V_BUILTIN_EQV_V4SI_UNS: + case P8V_BUILTIN_EQV_V2DI_UNS: + case P8V_BUILTIN_EQV_V1TI_UNS: + case P8V_BUILTIN_NAND_V16QI_UNS: + case P8V_BUILTIN_NAND_V8HI_UNS: + case P8V_BUILTIN_NAND_V4SI_UNS: + case P8V_BUILTIN_NAND_V2DI_UNS: + case P8V_BUILTIN_NAND_V1TI_UNS: + case P8V_BUILTIN_ORC_V16QI_UNS: + case P8V_BUILTIN_ORC_V8HI_UNS: + case P8V_BUILTIN_ORC_V4SI_UNS: + case P8V_BUILTIN_ORC_V2DI_UNS: + case P8V_BUILTIN_ORC_V1TI_UNS: h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; Index: gcc/testsuite/gcc.target/powerpc/pr92923-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr92923-1.c (nonexistent) +++ gcc/testsuite/gcc.target/powerpc/pr92923-1.c (working copy) @@ -0,0 +1,454 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -fdump-tree-gimple" } */ + +/* Verify that overloaded built-ins for "and", "andc", "nor", "or" and "xor" + do not produce VIEW_CONVERT_EXPR operations on their operands. Like so: + + _1 = VIEW_CONVERT_EXPR<__vector signed int>(x); + _2 = VIEW_CONVERT_EXPR<__vector signed int>(y); + _3 = __builtin_altivec_vand (_1, _2); + D.3245 = VIEW_CONVERT_EXPR(_3); +*/ + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) char bcvec_t; +typedef __attribute__((altivec(vector__))) signed char scvec_t; +typedef __attribute__((altivec(vector__))) unsigned char ucvec_t; + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) short bsvec_t; +typedef __attribute__((altivec(vector__))) signed short ssvec_t; +typedef __attribute__((altivec(vector__))) unsigned short usvec_t; + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) int bivec_t; +typedef __attribute__((altivec(vector__))) signed int sivec_t; +typedef __attribute__((altivec(vector__))) unsigned int uivec_t; + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) long long bllvec_t; +typedef __attribute__((altivec(vector__))) signed long long sllvec_t; +typedef __attribute__((altivec(vector__))) unsigned long long ullvec_t; + +typedef __attribute__((altivec(vector__))) double dvec_t; +typedef __attribute__((altivec(vector__))) float fvec_t; + +bcvec_t +and_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_and (x, y); +} + +scvec_t +and_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_and (x, y); +} + +ucvec_t +and_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_and (x, y); +} + +bsvec_t +and_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_and (x, y); +} + +ssvec_t +and_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_and (x, y); +} + +usvec_t +and_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_and (x, y); +} + +bivec_t +and_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_and (x, y); +} + +sivec_t +and_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_and (x, y); +} + +uivec_t +and_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_and (x, y); +} + +bllvec_t +and_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_and (x, y); +} + +sllvec_t +and_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_and (x, y); +} + +ullvec_t +and_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_and (x, y); +} + +dvec_t +and_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_and (x, y); +} + +fvec_t +and_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_and (x, y); +} + +bcvec_t +andc_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +scvec_t +andc_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +ucvec_t +andc_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +bsvec_t +andc_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +ssvec_t +andc_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +usvec_t +andc_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +bivec_t +andc_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_andc (x, y); +} + +sivec_t +andc_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_andc (x, y); +} + +uivec_t +andc_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_andc (x, y); +} + +bllvec_t +andc_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +sllvec_t +andc_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +ullvec_t +andc_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +dvec_t +andc_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +fvec_t +andc_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_andc (x, y); +} + +bcvec_t +nor_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +scvec_t +nor_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +ucvec_t +nor_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +bsvec_t +nor_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +ssvec_t +nor_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +usvec_t +nor_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +bivec_t +nor_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_nor (x, y); +} + +sivec_t +nor_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_nor (x, y); +} + +uivec_t +nor_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_nor (x, y); +} + +bllvec_t +nor_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +sllvec_t +nor_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +ullvec_t +nor_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +dvec_t +nor_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +fvec_t +nor_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_nor (x, y); +} + +bcvec_t +or_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_or (x, y); +} + +scvec_t +or_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_or (x, y); +} + +ucvec_t +or_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_or (x, y); +} + +bsvec_t +or_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_or (x, y); +} + +ssvec_t +or_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_or (x, y); +} + +usvec_t +or_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_or (x, y); +} + +bivec_t +or_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_or (x, y); +} + +sivec_t +or_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_or (x, y); +} + +uivec_t +or_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_or (x, y); +} + +bllvec_t +or_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_or (x, y); +} + +sllvec_t +or_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_or (x, y); +} + +ullvec_t +or_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_or (x, y); +} + +dvec_t +or_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_or (x, y); +} + +fvec_t +or_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_or (x, y); +} + +bcvec_t +xor_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +scvec_t +xor_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +ucvec_t +xor_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +bsvec_t +xor_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +ssvec_t +xor_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +usvec_t +xor_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +bivec_t +xor_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_xor (x, y); +} + +sivec_t +xor_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_xor (x, y); +} + +uivec_t +xor_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_xor (x, y); +} + +bllvec_t +xor_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +sllvec_t +xor_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +ullvec_t +xor_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +dvec_t +xor_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +fvec_t +xor_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_xor (x, y); +} + +/* { dg-final { scan-tree-dump-times "VIEW_CONVERT_EXPR" 0 "gimple" } } */ Index: gcc/testsuite/gcc.target/powerpc/pr92923-2.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr92923-2.c (nonexistent) +++ gcc/testsuite/gcc.target/powerpc/pr92923-2.c (working copy) @@ -0,0 +1,286 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2 -fdump-tree-gimple" } */ + +/* Verify that overloaded built-ins for "eqv", "nand" and "orc" do not + produce VIEW_CONVERT_EXPR operations on their operands. Like so: + + _1 = VIEW_CONVERT_EXPR<__vector signed int>(x); + _2 = VIEW_CONVERT_EXPR<__vector signed int>(y); + _3 = __builtin_altivec_vand (_1, _2); + D.3245 = VIEW_CONVERT_EXPR(_3); +*/ + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) char bcvec_t; +typedef __attribute__((altivec(vector__))) signed char scvec_t; +typedef __attribute__((altivec(vector__))) unsigned char ucvec_t; + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) short bsvec_t; +typedef __attribute__((altivec(vector__))) signed short ssvec_t; +typedef __attribute__((altivec(vector__))) unsigned short usvec_t; + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) int bivec_t; +typedef __attribute__((altivec(vector__))) signed int sivec_t; +typedef __attribute__((altivec(vector__))) unsigned int uivec_t; + +typedef __attribute__((altivec(vector__))) __attribute__((altivec(bool__))) long long bllvec_t; +typedef __attribute__((altivec(vector__))) signed long long sllvec_t; +typedef __attribute__((altivec(vector__))) unsigned long long ullvec_t; + +typedef __attribute__((altivec(vector__))) double dvec_t; +typedef __attribute__((altivec(vector__))) float fvec_t; + +bcvec_t +eqv_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +scvec_t +eqv_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +ucvec_t +eqv_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +bsvec_t +eqv_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +ssvec_t +eqv_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +usvec_t +eqv_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +bivec_t +eqv_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +sivec_t +eqv_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +uivec_t +eqv_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +bllvec_t +eqv_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +sllvec_t +eqv_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +ullvec_t +eqv_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +dvec_t +eqv_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +fvec_t +eqv_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_eqv (x, y); +} + +bcvec_t +nand_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +scvec_t +nand_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +ucvec_t +nand_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +bsvec_t +nand_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +ssvec_t +nand_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +usvec_t +nand_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +bivec_t +nand_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_nand (x, y); +} + +sivec_t +nand_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_nand (x, y); +} + +uivec_t +nand_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_nand (x, y); +} + +bllvec_t +nand_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +sllvec_t +nand_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +ullvec_t +nand_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +dvec_t +nand_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +fvec_t +nand_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_nand (x, y); +} + +bcvec_t +orc_0 (bcvec_t x, bcvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +scvec_t +orc_1 (scvec_t x, scvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +ucvec_t +orc_2 (ucvec_t x, ucvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +bsvec_t +orc_3 (bsvec_t x, bsvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +ssvec_t +orc_4 (ssvec_t x, ssvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +usvec_t +orc_5 (usvec_t x, usvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +bivec_t +orc_6 (bivec_t x, bivec_t y) +{ + return __builtin_vec_orc (x, y); +} + +sivec_t +orc_7 (sivec_t x, sivec_t y) +{ + return __builtin_vec_orc (x, y); +} + +uivec_t +orc_8 (uivec_t x, uivec_t y) +{ + return __builtin_vec_orc (x, y); +} + +bllvec_t +orc_9 (bllvec_t x, bllvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +sllvec_t +orc_10 (sllvec_t x, sllvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +ullvec_t +orc_11 (ullvec_t x, ullvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +dvec_t +orc_12 (dvec_t x, dvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +fvec_t +orc_13 (fvec_t x, fvec_t y) +{ + return __builtin_vec_orc (x, y); +} + +/* { dg-final { scan-tree-dump-times "VIEW_CONVERT_EXPR" 0 "gimple" } } */