From patchwork Thu Nov 23 12:55:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Tuerk X-Patchwork-Id: 840752 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yjKJt4fVDz9sNd for ; Fri, 24 Nov 2017 00:03:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752829AbdKWNCc convert rfc822-to-8bit (ORCPT ); Thu, 23 Nov 2017 08:02:32 -0500 Received: from mail3.emtrion.de ([80.150.99.69]:11935 "EHLO mail3.emtrion.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752826AbdKWNCa (ORCPT ); Thu, 23 Nov 2017 08:02:30 -0500 Received: from tuelinux-v3.emtrion.local (2003:5a:a012:1:250:56ff:fe29:ddb2) by bmk019s01.emtrion.local (2003:5a:a012:1:d9c:d045:28a7:5f84) with Microsoft SMTP Server (TLS) id 8.3.485.1; Thu, 23 Nov 2017 13:57:01 +0100 From: Jan Tuerk To: Rob Herring , Mark Rutland , Thierry Reding , David Airlie , Russell King , Shawn Guo , "Sascha Hauer" , Fabio Estevam , "Jan Tuerk" , =?utf-8?q?Andreas_F=C3=A4rber?= , Kevin Hilman , Maxime Ripard , Alexandre Belloni , Greg Kroah-Hartman , SZ Lin , , , , Subject: [PATCH 1/5] drm/panel: Add support for the EDT ETM0700G0BDH6 Date: Thu, 23 Nov 2017 13:55:51 +0100 Message-ID: <20171123125600.41562-2-jan.tuerk@emtrion.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171123125600.41562-1-jan.tuerk@emtrion.com> References: <20171123125600.41562-1-jan.tuerk@emtrion.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4283-8.100.1062-23484.006 X-TM-AS-Result: No--12.187400-8.000000-31 X-TM-AS-MatchedID: 700378-702796-704171-702358-702609-700156-188019-702311-8 62968-862883-703529-704410-704425-700324-702890-702762-702900-139504-706290 -860275-700008-700264-700802-702791-708712-148004-148036-42000-42003-55 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Emerging Display Technology ETM0700G0BDH6 is exactly the same display as the ETM0700G0DH6, exept the pixelclock polarity. Therefore re-use the ETM0700G0DH6 modes. It is used by default on emtrion Avari based development kits. Signed-off-by: Jan Tuerk --- .../bindings/display/panel/edt,etm0700g0bdh6.txt | 9 +++++++++ drivers/gpu/drm/panel/panel-simple.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt -- 2.11.0 emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de diff --git a/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt new file mode 100644 index 000000000000..099e30bfa17f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/edt,etm0700g0bdh6.txt @@ -0,0 +1,9 @@ +Emerging Display Technology Corp. ETM0700G0BDH6 7.0" WVGA TFT LCD panel + +Required properties: + compatible: "edt,etm0700g0bdh6" + +This panel is exactly the same as ETM0700G0DH6 except the pixelclock polarity. + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index b7c4709f7b34..42442034b53e 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -886,6 +886,18 @@ static const struct panel_desc edt_etm0700g0dh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, }; +static const struct panel_desc edt_etm0700g0bdh6 = { + .modes = &edt_etm0700g0dh6_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 152, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { .clock = 32260, .hdisplay = 800, @@ -2029,6 +2041,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,etm0700g0dh6", .data = &edt_etm0700g0dh6, }, { + .compatible = "edt,etm0700g0bdh6", + .data = &edt_etm0700g0bdh6, + }, { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, { From patchwork Thu Nov 23 12:55:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Tuerk X-Patchwork-Id: 840751 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yjKJl6Rqwz9sNd for ; Fri, 24 Nov 2017 00:03:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751479AbdKWNCi convert rfc822-to-8bit (ORCPT ); Thu, 23 Nov 2017 08:02:38 -0500 Received: from mail3.emtrion.de ([80.150.99.69]:11939 "EHLO mail3.emtrion.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752826AbdKWNCf (ORCPT ); Thu, 23 Nov 2017 08:02:35 -0500 Received: from tuelinux-v3.emtrion.local (2003:5a:a012:1:250:56ff:fe29:ddb2) by bmk019s01.emtrion.local (2003:5a:a012:1:d9c:d045:28a7:5f84) with Microsoft SMTP Server (TLS) id 8.3.485.1; Thu, 23 Nov 2017 13:57:07 +0100 From: Jan Tuerk To: Rob Herring , Mark Rutland , Thierry Reding , David Airlie , Russell King , Shawn Guo , "Sascha Hauer" , Fabio Estevam , "Jan Tuerk" , =?utf-8?q?Andreas_F=C3=A4rber?= , Kevin Hilman , Maxime Ripard , SZ Lin , "Greg Kroah-Hartman" , Alexandre Belloni , , , , Subject: [PATCH 2/5] dt-bindings: Add vendor prefix for emtrion GmbH Date: Thu, 23 Nov 2017 13:55:52 +0100 Message-ID: <20171123125600.41562-3-jan.tuerk@emtrion.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171123125600.41562-1-jan.tuerk@emtrion.com> References: <20171123125600.41562-1-jan.tuerk@emtrion.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4283-8.100.1062-23484.006 X-TM-AS-Result: No--7.166500-8.000000-31 X-TM-AS-MatchedID: 708167-700251-700817-187014-139705-708196-704410-701698-1 88019-702796-712248-701303-148004-148036-10019-41000-42000-42003-55 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org emtrion is a system integrator and manufacturer of embedded systems. Website: https://www.emtrion.de Signed-off-by: Jan Tuerk Acked-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 0994bdd82cd3..5215c5767260 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -102,6 +102,7 @@ eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. embest Shenzhen Embest Technology Co., Ltd. emmicro EM Microelectronic +emtrion emtrion GmbH energymicro Silicon Laboratories (formerly Energy Micro AS) engicam Engicam S.r.l. epcos EPCOS AG From patchwork Thu Nov 23 12:55:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Tuerk X-Patchwork-Id: 840750 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yjKHm2MR8z9sPk for ; Fri, 24 Nov 2017 00:03:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752949AbdKWNCv convert rfc822-to-8bit (ORCPT ); Thu, 23 Nov 2017 08:02:51 -0500 Received: from mail3.emtrion.de ([80.150.99.69]:11941 "EHLO mail3.emtrion.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752925AbdKWNCp (ORCPT ); Thu, 23 Nov 2017 08:02:45 -0500 Received: from tuelinux-v3.emtrion.local (2003:5a:a012:1:250:56ff:fe29:ddb2) by bmk019s01.emtrion.local (2003:5a:a012:1:d9c:d045:28a7:5f84) with Microsoft SMTP Server (TLS) id 8.3.485.1; Thu, 23 Nov 2017 13:57:17 +0100 From: Jan Tuerk To: Rob Herring , Mark Rutland , Thierry Reding , David Airlie , Russell King , Shawn Guo , "Sascha Hauer" , Fabio Estevam , "Jan Tuerk" , =?utf-8?q?Andreas_F=C3=A4rber?= , Kevin Hilman , Geert Uytterhoeven , Alexandre Belloni , SZ Lin , "Greg Kroah-Hartman" , , , , Subject: [PATCH 4/5] ARM: dts: Add support for emtrion emCON-MX6 series Date: Thu, 23 Nov 2017 13:55:54 +0100 Message-ID: <20171123125600.41562-5-jan.tuerk@emtrion.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171123125600.41562-1-jan.tuerk@emtrion.com> References: <20171123125600.41562-1-jan.tuerk@emtrion.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4283-8.100.1062-23484.006 X-TM-AS-Result: No--0.623300-8.000000-31 X-TM-AS-MatchedID: 701762-186035-705753-704713-701433-700752-702609-700918-7 07788-862883-704410-701016-703529-704425-188019-700324-702762-711664-105640 -843086-703969-701604-704332-113241-703786-706769-139704-708196-706355-1213 36-188198-701040-863596-860275-700264-701482-700624-860493-700901-704496-70 2311-705567-702898-700383-701350-702890-700648-702829-702106-709009-863174- 702747-186003-712232-862262-139630-700163-863725-702113-700802-704983-70871 2-148004-148036-20023-29997-42000-42003-55 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot). Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari). The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files. Signed-off-by: Jan Tuerk --- Documentation/devicetree/bindings/arm/emtrion.txt | 13 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6dl-emcon.dtsi | 37 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 233 ++++++ arch/arm/boot/dts/imx6q-emcon.dtsi | 37 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 849 ++++++++++++++++++++++ 7 files changed, 1404 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi -- 2.11.0 emtrion GmbH Kreativpark - Alter Schlachthof 45 76131 Karlsruhe GERMANY http://www.emtrion.de diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..3ff6c6c2034d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,13 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9caf21..5ce643ece228 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -373,6 +373,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -424,6 +425,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-dfi-fs700-m60.dtb \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ + imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..f8ca63258eda --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 outputs on AVARI*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3A { + compatible = "nxp,pca8574"; + reg = <0x3A>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: edt-ft5x06@38 { + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + compatible = "edt,edt-ft5406"; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi new file mode 100644 index 000000000000..47f43bae5ac5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/ { + model = "emtrion SoM emCON-MX6 Solo/DualLite"; + compatible = "emtrion,emcon-mx6","fsl,imx6dl"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..bccfd6344c18 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + mmc3 = &usdhc4; + }; + + chosen { + stdout-path = <&uart1>; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + supplies { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wallplug5p0: supply@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "WALL-PLUG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + base3p3: supply@1 { + compatible = "regulator-fixed"; + reg = <1>; + vin-supply = <&wallplug5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + base1p5: supply@2 { + compatible = "regulator-fixed"; + reg = <2>; + vin-supply = <&base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: otgvbus { + compatible = "regulator-fixed"; + reg = <3>; + vin-supply = <&wallplug5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + }; + + + sndosc: 12MHZosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + +}; + + +&iomuxc { + pinctrl-names = "default"; + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ + pinctrl-0 = < + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash + &pinctrl_usdhc2 + &pinctrl_spdif_out &pinctrl_spdif_in + &pinctrl_cpi1 &pinctrl_cpi2 + >; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sndosc>; + VDDA-supply = <&base3p3>; + VDDIO-supply = <&base3p3>; + }; + + boardID: pca8754a@3A { + compatible = "nxp,pca8574"; + reg = <0x3A>; + gpio-controller; + #gpio-cells = <1>; + }; + + captouch: edt-ft5x06@38 { + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + compatible = "edt,edt-ft5406"; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ssi2 { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi new file mode 100644 index 000000000000..64fc0cd74c05 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad"; + compatible = "emtrion,emcon-mx6","fsl,imx6q"; +}; + +&iomuxc { + pinctrl_cpi2: csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..22ad05880ea7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,849 @@ +/* + * Copyright (C) 2017 emtrion GmbH + * Author: Jan Tuerk + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include +#include +#include + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6","fsl,imx6q", "fsl,imx6dl"; + + aliases { + mmc0 = &usdhc3; + mmc2 = &usdhc1; + mmc1 = &usdhc2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_parallel_disp: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = ; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <4>; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + rgb_encoder: lcd@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: panel { + backlight = <&rgb_backlight>; + power-supply = <®_prallel_disp>; + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + rgb_backlight: rgb_backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = <250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; + + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = <0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + + +&iomuxc { + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + +}; + + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; + + da9063: da9063@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + wakeup-source; + compatible = "dlg,da9063-onkey"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <20000>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <20000>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, + <&gpio2 26 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + + + +/*******Disabled HW following***********/ + + +&weim { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; +