From patchwork Thu Nov 28 22:23:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1202298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-514804-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="FhjmnKsd"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47PBxG46g0z9sR2 for ; Fri, 29 Nov 2019 09:23:28 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=bQj7Q5Ipg5XK jUiqAkxgmn/fR/QtKIJ0kan1KNJQuSE41Q8Ijk9LdyCLHqjNsDmNzmEGLlUv2jZv yyn3s74NbbRK5pIKYQrVLqKk+4Oc5ykmOpDc9xKvW7hUzoOgRxeZI9zr2nBbw/NX Iia2dg/dpqsJK+4qQLLn+AVTxgixwFA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=8E5o5kbZeursB6E+Wm 73taBkKkU=; b=FhjmnKsd8jqGdinmHkDEJO9xMxrHTsOwNqVctG7hswkK891l6v SBr+5zNUbiSIgNMFFxCw/IDxIydAkQ9NHge9yf6e61lQShX3Q33RFis1zIAegt6U kcU6IFs7+nMa4d4tZ7DRr6klqbEqdFayadllf43DGXqJSFnxKjopnx1iU= Received: (qmail 23490 invoked by alias); 28 Nov 2019 22:23:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23483 invoked by uid 89); 28 Nov 2019 22:23:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=cell X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 28 Nov 2019 22:23:18 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 132D4124073B; Thu, 28 Nov 2019 22:23:16 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH] rs6000: Use memory_operand for all simple {l, st}*brx instructions Date: Thu, 28 Nov 2019 22:23:15 +0000 Message-Id: <2233e8a73834a4fb4f959c2c4ae43a1cdd8fa77e.1574978788.git.segher@kernel.crashing.org> X-IsSubscribed: yes We run fwprop before combine, very early even in the case of fwprop1; and fwprop1 will change memory addressing to what it considers cheaper. After the "common" change, it now changes the indexed store instruction in the testcase to be to a constant address. But that is not an improvement at all: the byte reverse instructions only exist in the indexed form, so they will not match anymore. This patch changes the patterns for the byte reverse instructions to allow plain memory_operand, letting reload fix this up. Tested on powerpc64-linux {-m32,-m64}, committing to trunk. Segher 2019-11-28 Segher Boessenkool PR target/92602 * config/rs6000/rs6000.md (bswap2_load for HSI): Change the indexed_or_indirect_operand to be memory_operand. (bswap2_store for HSI): Ditto. (bswapdi2_load): Ditto. (bswapdi2_store): Ditto. --- gcc/config/rs6000/rs6000.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 876dfe3..0187ba0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2510,13 +2510,13 @@ (define_expand "bswap2" (define_insn "bswap2_load" [(set (match_operand:HSI 0 "gpc_reg_operand" "=r") - (bswap:HSI (match_operand:HSI 1 "indexed_or_indirect_operand" "Z")))] + (bswap:HSI (match_operand:HSI 1 "memory_operand" "Z")))] "" "lbrx %0,%y1" [(set_attr "type" "load")]) (define_insn "bswap2_store" - [(set (match_operand:HSI 0 "indexed_or_indirect_operand" "=Z") + [(set (match_operand:HSI 0 "memory_operand" "=Z") (bswap:HSI (match_operand:HSI 1 "gpc_reg_operand" "r")))] "" "stbrx %1,%y0" @@ -2632,13 +2632,13 @@ (define_expand "bswapdi2" ;; Power7/cell has ldbrx/stdbrx, so use it directly (define_insn "bswapdi2_load" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "Z")))] + (bswap:DI (match_operand:DI 1 "memory_operand" "Z")))] "TARGET_POWERPC64 && TARGET_LDBRX" "ldbrx %0,%y1" [(set_attr "type" "load")]) (define_insn "bswapdi2_store" - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "=Z") + [(set (match_operand:DI 0 "memory_operand" "=Z") (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] "TARGET_POWERPC64 && TARGET_LDBRX" "stdbrx %1,%y0"