From patchwork Tue Nov 19 06:50:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1197204 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ducezMlC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HGhq4czPz9sTM for ; Tue, 19 Nov 2019 17:52:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727513AbfKSGu6 (ORCPT ); Tue, 19 Nov 2019 01:50:58 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14231 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727435AbfKSGu4 (ORCPT ); Tue, 19 Nov 2019 01:50:56 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:50:53 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:50:55 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 18 Nov 2019 22:50:55 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:50:55 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:50:55 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 18 Nov 2019 22:50:55 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 03/17] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock ids Date: Mon, 18 Nov 2019 22:50:20 -0800 Message-ID: <1574146234-3871-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146253; bh=ZiS18JWuxnwX5tG02uam2QHdhq0/3nkgaJJSyay5kRU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ducezMlCt4Pq61iIIBvrxIx46nw/2hrY1iLdSp1y6eVJkGVUBiQFzib2vgZduKVom UwbDMFBoHR7aqNW4bwkvlMEak2A4/VDQ5HiKwsQp5q/IL5MamWw65t3Llt0Vko9JJS hEeT/7oqPFPQRdALN6dA1U8CC1+z9XIAm2OKhGr5eKWt9ZcWjADxw8rQITVWaB+S/f bekBuNtqjpqsvF9mlW0Q63iXqXPgqz0JTgvk/EZQ5GSMfRU8w8LVhOR4RhC12thY+B EF1PWhzkIgIb2BFMY708bXb9fvtFugmOwIvAdaKTLN929h8SzXOIWvEk1BNLKEYw+r zxHBTVGsmijKg== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra PMC has clk_out_1, clk_out_2, clk_out_3 clocks and each of these clocks has mux and a gate as a part of PMC controller. This patch adds ids for each of these PMC clock mux and gates to use with the devicetree. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/soc/tegra-pmc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/soc/tegra-pmc.h diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h new file mode 100644 index 000000000000..fa1ccfc2514b --- /dev/null +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +#define _DT_BINDINGS_SOC_TEGRA_PMC_H + +#define TEGRA_PMC_CLK_OUT_1_MUX 0 +#define TEGRA_PMC_CLK_OUT_1 1 +#define TEGRA_PMC_CLK_OUT_2_MUX 2 +#define TEGRA_PMC_CLK_OUT_2 3 +#define TEGRA_PMC_CLK_OUT_3_MUX 4 +#define TEGRA_PMC_CLK_OUT_3 5 + +#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ From patchwork Tue Nov 19 06:50:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1197202 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="CoUWIUDw"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HGhh2yCjz9sTN for ; Tue, 19 Nov 2019 17:52:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727599AbfKSGvA (ORCPT ); Tue, 19 Nov 2019 01:51:00 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10790 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727575AbfKSGvA (ORCPT ); Tue, 19 Nov 2019 01:51:00 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:51:02 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:50:59 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 18 Nov 2019 22:50:59 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:50:58 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:50:58 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:50:58 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 18 Nov 2019 22:50:58 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 05/17] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC blink control Date: Mon, 18 Nov 2019 22:50:22 -0800 Message-ID: <1574146234-3871-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146262; bh=rzjEACmDAo3v51vjKD7mPrAFEwim/IXtmodBCpgf+vc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=CoUWIUDw7KlzW9hBWPiqlu5bPHVAer1LYYCoDfCANjzdtU1abVlonCRVyamhLJTOz ZifwSnJ7x3pgALMf37MOEwXDWQP8lnmv0HOYsjjRiWdSQs7nf3E1jCcYZEIQ3ANLov upoj7PtapcnUB3N6+3lsJy7+7DBi13Hg4vJKsthb9pfIwWy8nX06z6KmSYLCx4b+HB y9HUWL+iWKTf/fdb8E5qH74RmfLV3B1ZkCIJPN7j2CuGEopmN2BWyJm/ybvdEIsSB4 Nwt6WZhykxTNMj5aK60nUKUqRAGjlqRUKIKlm1D8IwcxbSTJgvRW817qdbcDX+hBnL oXTeDampOLIig== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra PMC has a blinking control to output 32 KHz clock to blink pin. This patch adds id for this blink control to use for enabling or disabling the blink output through devicetree. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/soc/tegra-pmc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h index fa1ccfc2514b..bcb24e17981f 100644 --- a/include/dt-bindings/soc/tegra-pmc.h +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -12,5 +12,6 @@ #define TEGRA_PMC_CLK_OUT_2 3 #define TEGRA_PMC_CLK_OUT_3_MUX 4 #define TEGRA_PMC_CLK_OUT_3 5 +#define TEGRA_PMC_CLK_BLINK 6 #endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ From patchwork Tue Nov 19 06:50:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1197196 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="kFQwHHzR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HGhN5xMkz9sSJ for ; Tue, 19 Nov 2019 17:51:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727824AbfKSGvM (ORCPT ); Tue, 19 Nov 2019 01:51:12 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8321 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727792AbfKSGvL (ORCPT ); Tue, 19 Nov 2019 01:51:11 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:51:09 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:51:08 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 18 Nov 2019 22:51:08 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:51:08 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:51:08 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 18 Nov 2019 22:51:07 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 11/17] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Date: Mon, 18 Nov 2019 22:50:28 -0800 Message-ID: <1574146234-3871-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146269; bh=k6+2YQdeTb5W9Ih8fGDwfsFTywHl5MmO6ZKZuuXrGAQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kFQwHHzRj6xpk/itiLyZT0nrmES/Bt4TIglsOQL2rVoUR4UMMagvz/MESG0sST078 7iOmAZJzmXc7QIf4c4ybFGTe2KI8S8djJ2RODkm7tgC6Dc7KWJ7h013bDlUUi/xqTl 4fbjlBd1fgI9VnYEd/MGpEKRMGvnGbLO3TtyWKolsQeZrkIkfWrVSk0Ai9n61tBQGH 5mhMZftdaNEqADBaLZ+F6BIpzZLNGZfuXbKxcTbpm4oyL62Yrf8ndCxdNPH/RbGX4R Xm3G1cAt5xf8VK8ex2TsxcMpWlLYHAkkjruDHv0zWDaWnLvEASCEMFx3eY/end2a3i Jwe9Zcd+MjGgg== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra pmc clocks. This patch removes ids for these clocks from Tegra clock dt-bindings. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra114-car.h | 14 +++++++------- include/dt-bindings/clock/tegra124-car-common.h | 14 +++++++------- include/dt-bindings/clock/tegra20-car.h | 2 +- include/dt-bindings/clock/tegra210-car.h | 14 +++++++------- include/dt-bindings/clock/tegra30-car.h | 14 +++++++------- 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index bb5c2c999c05..9175cd0571b5 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -270,10 +270,10 @@ #define TEGRA114_CLK_AUDIO3 242 #define TEGRA114_CLK_AUDIO4 243 #define TEGRA114_CLK_SPDIF 244 -#define TEGRA114_CLK_CLK_OUT_1 245 -#define TEGRA114_CLK_CLK_OUT_2 246 -#define TEGRA114_CLK_CLK_OUT_3 247 -#define TEGRA114_CLK_BLINK 248 +/* 245 */ +/* 246 */ +/* 247 */ +/* 248 */ /* 249 */ /* 250 */ /* 251 */ @@ -333,9 +333,9 @@ #define TEGRA114_CLK_AUDIO3_MUX 303 #define TEGRA114_CLK_AUDIO4_MUX 304 #define TEGRA114_CLK_SPDIF_MUX 305 -#define TEGRA114_CLK_CLK_OUT_1_MUX 306 -#define TEGRA114_CLK_CLK_OUT_2_MUX 307 -#define TEGRA114_CLK_CLK_OUT_3_MUX 308 +/* 306 */ +/* 307 */ +/* 308 */ #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 #define TEGRA114_CLK_XUSB_SS_DIV2 311 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 0c4f5be0a742..90a0c5e7eb5f 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -269,10 +269,10 @@ #define TEGRA124_CLK_AUDIO3 242 #define TEGRA124_CLK_AUDIO4 243 #define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 +/* 245 */ +/* 246 */ +/* 247 */ +/* 248 */ /* 249 */ /* 250 */ /* 251 */ @@ -332,9 +332,9 @@ #define TEGRA124_CLK_AUDIO3_MUX 303 #define TEGRA124_CLK_AUDIO4_MUX 304 #define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +/* 306 */ +/* 307 */ +/* 308 */ /* 309 */ /* 310 */ #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h index b21a0eb32921..fe541f627965 100644 --- a/include/dt-bindings/clock/tegra20-car.h +++ b/include/dt-bindings/clock/tegra20-car.h @@ -131,7 +131,7 @@ #define TEGRA20_CLK_CCLK 108 #define TEGRA20_CLK_HCLK 109 #define TEGRA20_CLK_PCLK 110 -#define TEGRA20_CLK_BLINK 111 +/* 111 */ #define TEGRA20_CLK_PLL_A 112 #define TEGRA20_CLK_PLL_A_OUT0 113 #define TEGRA20_CLK_PLL_C 114 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 44f60623f99b..a3d8d3e75728 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -304,10 +304,10 @@ #define TEGRA210_CLK_AUDIO3 274 #define TEGRA210_CLK_AUDIO4 275 #define TEGRA210_CLK_SPDIF 276 -#define TEGRA210_CLK_CLK_OUT_1 277 -#define TEGRA210_CLK_CLK_OUT_2 278 -#define TEGRA210_CLK_CLK_OUT_3 279 -#define TEGRA210_CLK_BLINK 280 +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ #define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR1_OUT 282 @@ -386,9 +386,9 @@ #define TEGRA210_CLK_AUDIO3_MUX 353 #define TEGRA210_CLK_AUDIO4_MUX 354 #define TEGRA210_CLK_SPDIF_MUX 355 -#define TEGRA210_CLK_CLK_OUT_1_MUX 356 -#define TEGRA210_CLK_CLK_OUT_2_MUX 357 -#define TEGRA210_CLK_CLK_OUT_3_MUX 358 +/* 356 */ +/* 357 */ +/* 358 */ #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 /* 361 */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 3c90f1535551..20ef2462d9e1 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -230,11 +230,11 @@ #define TEGRA30_CLK_AUDIO3 204 #define TEGRA30_CLK_AUDIO4 205 #define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +/* 207 */ +/* 208 */ +/* 209 */ #define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 +/* 211 */ #define TEGRA30_CLK_CCLK_G 212 #define TEGRA30_CLK_CCLK_LP 213 #define TEGRA30_CLK_TWD 214 @@ -260,9 +260,9 @@ /* 297 */ /* 298 */ /* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +/* 300 */ +/* 301 */ +/* 302 */ #define TEGRA30_CLK_AUDIO0_MUX 303 #define TEGRA30_CLK_AUDIO1_MUX 304 #define TEGRA30_CLK_AUDIO2_MUX 305 From patchwork Tue Nov 19 06:50:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1197194 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="RQGyHB1X"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HGhM6j0Rz9sTG for ; Tue, 19 Nov 2019 17:51:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727792AbfKSGvf (ORCPT ); Tue, 19 Nov 2019 01:51:35 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8392 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727569AbfKSGvR (ORCPT ); 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Mon, 18 Nov 2019 22:51:14 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 14/17] dt-bindings: Add Tegra PMC clock configuration bindings Date: Mon, 18 Nov 2019 22:50:31 -0800 Message-ID: <1574146234-3871-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146276; bh=8xZY11tbp+usm/Nb6Z9xjnnoWn2JHFMyJbgWjmLOHXY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=RQGyHB1XOJXfSAWza0wiwB5OonczD++hm/D7Rafd59D3ZWA9Li5QBPjYqAvqVewP4 QF7eXYrb7XZ6e/EU+9FMkc/7u9CWOeWcmgDdjNj6nyj+MjasoG1smDbr2UcfYFhfIS LfdCEmjGf2azi561IMXMXRcz0Um0VnV3/E2xGXT4mIv6qxS3+wEHSSw415kJMq6Vy/ wL9uilxf2mj0lkJ2xEbxBn/JVZdtTr/KSaTxWYw/25646jCQu2YdAcwNm96hd1OWVq 5p97gRP+YKxhaOVa5SgEtd2ZEnJByFuNJ6z2VM1uAfdLzTZ72N7yfxMEGC7ejgzTWt mQ4HYQugsDn1g== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document clock bindings for pmc clocks clk_out_1, clk_out_2 and clk_out_3. These clocks are part of Tegra PMC block and pmc node is the provider for these clocks. Signed-off-by: Sowjanya Komatineni --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index cb12f33a247f..602a1ac5c0b6 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -21,6 +21,10 @@ Required properties: - clock-names : Must include the following entries: "pclk" (The Tegra clock of that name), "clk32k_in" (The 32KHz clock input to Tegra). +- #clock-cells : Should be 1 for Tegra30 and higher. + In clock consumers, this cell represents the PMC clock ID. + The assignments may be found in header file + . Optional properties: - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. @@ -171,6 +175,7 @@ Example: reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; powergates { pd_audio: aud { @@ -260,6 +265,7 @@ Pad configuration state example: reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; ... @@ -298,3 +304,39 @@ Pinctrl client example: pinctrl-1 = <&hdmi_on>; pinctrl-names = "hdmi-on", "hdmi-off"; }; + +== Clock Control == + +Tegra PMC has 3 clocks clk_1, clk_2 and clk_3. Each of these clocks has +source selection and enable/disable gate. +Parent/source for these clocks can be either of clk_m, clk_m_div2, clk_m_div4, +or extern clock from Tegra CAR module. + +Clock configuration example: + pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + }; + +Clock consumer example: + host1x@50000000 { + ... + vi@54080000 { + ... + assigned-clocks = <&pmc TEGRA_PMC_CLK_OUT_3_MUX>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_EXTERN3>; + }; + ... + }; + ... + i2c@7000c500 { + cam_sensor { + ... + clocks = <&pmc TEGRA_PMC_CLK_OUT_3>; + clock-names = "mclk"; + ... + }; + }; From patchwork Tue Nov 19 06:50:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1197187 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="qixSZeDV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HGgs68Mbz9sT8 for ; Tue, 19 Nov 2019 17:51:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727917AbfKSGvT (ORCPT ); Tue, 19 Nov 2019 01:51:19 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14339 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727892AbfKSGvS (ORCPT ); Tue, 19 Nov 2019 01:51:18 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:51:14 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:51:17 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 18 Nov 2019 22:51:17 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:51:16 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:51:16 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:51:16 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 18 Nov 2019 22:51:16 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 15/17] dt-bindings: tegra186-pmc: Add Tegra PMC clock bindings Date: Mon, 18 Nov 2019 22:50:32 -0800 Message-ID: <1574146234-3871-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146274; bh=G7T/VBzC6jgpoi4v7NU2+pO/USNPyUXRGIQX4N7GGMA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qixSZeDVAGBlCTnUbZKAPWoRGF1e0Ng9EV35HOoonh+TKycDSEvfturUTFKu3kVzf ZNy5pWvEwfaI+XuxnSUy2LYTGIyWs1fgHELJsjUvY0gC3qIh5BkRDEEv9zDtpnxvGX ZWqhwV1yL9BLc0yqO8BTEIfFq+XyHdu0ZeflRbZ9oCwTL+ZS9jVV8GKiuT58JrsCr3 jxeVsecAB3KiB9qI21/2zF/dH6RkeREoP11Bps5vkD3a2gv8vGMebyzHTkPR6sD+aI Gq4q/6ivDp1n9FNbsG/ll96pmadCp06KSydxLRwxEP7CwEQ3FIv/sSt697mdt1jUd6 NiyABHLnyn9pA== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document clock bindings for pmc clocks clk_out_1, clk_out_2 and clk_out_3. These clocks are part of Tegra PMC block and pmc node is the provider for these clocks. Signed-off-by: Sowjanya Komatineni --- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index 2d89cdc39eb0..4576de92e4cc 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -12,6 +12,10 @@ Required properties: - "aotag" - "scratch" - "misc" (Only for Tegra194) +- #clock-cells : Should be 1 for Tegra30 and higher. + In clock consumers, this cell represents the PMC clock ID. + The assignments may be found in header file + . Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. @@ -130,3 +134,43 @@ Pinctrl client example: pinctrl-1 = <&hdmi_on>; pinctrl-names = "hdmi-on", "hdmi-off"; }; + +== Clock Control == + +Tegra PMC has 3 clocks clk_1, clk_2 and clk_3. Each of these clocks has +source selection and enable/disable gate. +Parent/source for these clocks can be either of clk_m, clk_m_div2, clk_m_div4, +or extern clock from Tegra CAR module. + +Clock configuration example: + pmc: pmc@7000e400 { + compatible = "nvidia,tegra186-pmc"; + reg = <0 0x0c360000 0 0x10000>, + <0 0x0c370000 0 0x10000>, + <0 0x0c380000 0 0x10000>, + <0 0x0c390000 0 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + ... + #clock-cells = <1>; + ... + }; + +Clock consumer example: + host1x@50000000 { + ... + vi@54080000 { + ... + assigned-clocks = <&pmc TEGRA_PMC_CLK_OUT_3_MUX>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_EXTERN3>; + }; + ... + }; + ... + i2c@7000c500 { + cam_sensor { + ... + clocks = <&pmc TEGRA_PMC_CLK_OUT_3>; + clock-names = "mclk"; + ... + }; + }; From patchwork Tue Nov 19 06:50:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1197189 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="XSLyLdvj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HGgv67rbz9sTB for ; Tue, 19 Nov 2019 17:51:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727935AbfKSGvV (ORCPT ); Tue, 19 Nov 2019 01:51:21 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14361 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727926AbfKSGvV (ORCPT ); Tue, 19 Nov 2019 01:51:21 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:51:17 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:51:20 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 18 Nov 2019 22:51:20 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:51:19 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:51:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 18 Nov 2019 22:51:19 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 17/17] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car to pmc Date: Mon, 18 Nov 2019 22:50:34 -0800 Message-ID: <1574146234-3871-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146277; bh=qTvAji4nlSTfeFg4MTzoqwXKbO75ceIOy1l+c/njykQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=XSLyLdvjW2mBOG+rtLmBReEZEyHFu74qYEfUx/86ZVr4Z7mxoCqah+0ytTnGOHT9P NzK4wssJlVWpWFB7z6OZx+jnhNc4J7OBdvSU3j8txYXtlGlBCb0K8AuQoI2Ty9PgZp hfT2aWqNJDCkdXahGVafypYOyy9g4Ds9f3fJyaFxSICM0zIplcL3At6N0wIbY03EsR I5+y/AmWggulqlU6Qv0LAdKI4df/0mzAOrPtjNDNYAas8zekqMIpYRrjhApo9/XtCa 6En1WflKGJ6cDuoCx0oKL7GM/r+QndchWXoLuhBLOR1r5JWlb+LYS/cLb+2E1YlsgS PwSQOI5XhhiBw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra clk_out_1, clk_out_2, and clk_out_3 are part of PMC block and pmc is the provider for these clocks. Update bindings document to use pmc as clock provider for clk_out_2 and change id to pmc clock id. Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/sound/nau8825.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/nau8825.txt b/Documentation/devicetree/bindings/sound/nau8825.txt index d16d96839bcb..487eb9574ee2 100644 --- a/Documentation/devicetree/bindings/sound/nau8825.txt +++ b/Documentation/devicetree/bindings/sound/nau8825.txt @@ -101,5 +101,5 @@ Example: nuvoton,crosstalk-enable; clock-names = "mclk"; - clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; + clocks = <&pmc TEGRA_PMC_CLK_OUT_2>; };