From patchwork Tue Nov 5 02:23:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamal Shareef X-Patchwork-Id: 1189284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jd10ct4X"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476YPH4T5Wz9sPL for ; Tue, 5 Nov 2019 13:23:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387436AbfKECX2 (ORCPT ); Mon, 4 Nov 2019 21:23:28 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35596 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728987AbfKECX2 (ORCPT ); Mon, 4 Nov 2019 21:23:28 -0500 Received: by mail-pg1-f196.google.com with SMTP id q22so5290407pgk.2; Mon, 04 Nov 2019 18:23:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=/XQPTUQdnIxsmo3yaVIj6Nhp7ayUgTHZ2bwUnPNImsM=; b=Jd10ct4X+ROh8H/H8/GovQp0g/sOl6KugUoMq/WSwkvJ/f/QIezkkw31N/HGoIeJNL u8JY7bP2fskwM/NYY7xsXG/z+0lWi7vHPZ7TIgksLH7QzYIGi8VpD69aY9SQIfEGt36D xtJm1N/H3CazKJ2gaOz6SuRLF63o0PdX8zF9XHCaYtRcDYdlALP71yPxow6PTCtxTP7T uG3REIVtR4TTc5RUxcsTwuzl4MAGEOEz+c8V2BYLQao9nMsRtmx2azYwRYsjfjSbQir5 +frsGoDVKSWGynfv9BGOEYXGy9NMR4njp862VMtTqOrPp96jmOaain5hDH2xhsAUD+F0 mZ9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=/XQPTUQdnIxsmo3yaVIj6Nhp7ayUgTHZ2bwUnPNImsM=; b=WxVMaN27M6wyGbmoi4op9I+qlrCKg+kWNoNONCqw2S1aoU9d4HT/J9EPTrc8T1OHs0 06RNj7SNz2RhouaWFzfUk03mFM7yYDEwM3+Rn/5STTZbhGWM2rPDOjvLAT2C3vWjQrH2 q1l9cnOjjr00AL4AkXrlyl4l5vZyedQrHVvgNsRjRYLgNCDBNv0cMiw9SD84CEQyYxME TKTmKjCFrKF6Dpq2HIKImQwAwOovDc/yGBKP/uB9ObZqblRqC99OLtooo4O2QvJobqxN h8fIPuXD4lWIGUwKTBOx0umJpg1/MoqsDq9L7OB+PM3rX4BMTMHqSRX8SE14fBENCjs5 TSYA== X-Gm-Message-State: APjAAAUBGE2f2ch7CgZAw5WZi9si9WNt7r7Er/ExcucbhPa+EN9lj/k8 MMpBhqH/E+FMRgAdgpj5olQ= X-Google-Smtp-Source: APXvYqyEXXvmBDJFhtUty1uv1FGUNd0Ur5OhXUk9ZCW72Fx+BuP7WqteYWkiW8tLMyajdedzB7HOhQ== X-Received: by 2002:a63:c103:: with SMTP id w3mr3193120pgf.275.1572920607597; Mon, 04 Nov 2019 18:23:27 -0800 (PST) Received: from jamal-desktop (97-126-66-56.tukw.qwest.net. [97.126.66.56]) by smtp.gmail.com with ESMTPSA id u3sm15397779pgp.51.2019.11.04.18.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 18:23:27 -0800 (PST) From: Jamal Shareef To: outreachy-kernel@googlegroups.com Cc: thierry.reding@gmail.com, airlied@linux.ie, daniel@ffwll.ch, jonathanh@nvidia.com, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Jamal Shareef Subject: [PATCH 1/3] drm/tegra: dc: Remove space after parenthesis Date: Mon, 4 Nov 2019 18:23:20 -0800 Message-Id: <8e5b985c756f33decd07a728b7fc24b5518b3b47.1572920482.git.jamal.k.shareef@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Removes space after left parenthesis. Issue found by checkpatch. Signed-off-by: Jamal Shareef --- drivers/gpu/drm/tegra/dc.h | 40 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 0c4d17851f47..01fe9cc078ff 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -406,15 +406,15 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DISP_ORDER_BLUE_RED (1 << 9) #define DC_DISP_DISP_COLOR_CONTROL 0x430 -#define BASE_COLOR_SIZE666 ( 0 << 0) -#define BASE_COLOR_SIZE111 ( 1 << 0) -#define BASE_COLOR_SIZE222 ( 2 << 0) -#define BASE_COLOR_SIZE333 ( 3 << 0) -#define BASE_COLOR_SIZE444 ( 4 << 0) -#define BASE_COLOR_SIZE555 ( 5 << 0) -#define BASE_COLOR_SIZE565 ( 6 << 0) -#define BASE_COLOR_SIZE332 ( 7 << 0) -#define BASE_COLOR_SIZE888 ( 8 << 0) +#define BASE_COLOR_SIZE666 (0 << 0) +#define BASE_COLOR_SIZE111 (1 << 0) +#define BASE_COLOR_SIZE222 (2 << 0) +#define BASE_COLOR_SIZE333 (3 << 0) +#define BASE_COLOR_SIZE444 (4 << 0) +#define BASE_COLOR_SIZE555 (5 << 0) +#define BASE_COLOR_SIZE565 (6 << 0) +#define BASE_COLOR_SIZE332 (7 << 0) +#define BASE_COLOR_SIZE888 (8 << 0) #define BASE_COLOR_SIZE101010 (10 << 0) #define BASE_COLOR_SIZE121212 (12 << 0) #define DITHER_CONTROL_MASK (3 << 8) @@ -422,17 +422,17 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DITHER_CONTROL_ORDERED (2 << 8) #define DITHER_CONTROL_ERRDIFF (3 << 8) #define BASE_COLOR_SIZE_MASK (0xf << 0) -#define BASE_COLOR_SIZE_666 ( 0 << 0) -#define BASE_COLOR_SIZE_111 ( 1 << 0) -#define BASE_COLOR_SIZE_222 ( 2 << 0) -#define BASE_COLOR_SIZE_333 ( 3 << 0) -#define BASE_COLOR_SIZE_444 ( 4 << 0) -#define BASE_COLOR_SIZE_555 ( 5 << 0) -#define BASE_COLOR_SIZE_565 ( 6 << 0) -#define BASE_COLOR_SIZE_332 ( 7 << 0) -#define BASE_COLOR_SIZE_888 ( 8 << 0) -#define BASE_COLOR_SIZE_101010 ( 10 << 0) -#define BASE_COLOR_SIZE_121212 ( 12 << 0) +#define BASE_COLOR_SIZE_666 (0 << 0) +#define BASE_COLOR_SIZE_111 (1 << 0) +#define BASE_COLOR_SIZE_222 (2 << 0) +#define BASE_COLOR_SIZE_333 (3 << 0) +#define BASE_COLOR_SIZE_444 (4 << 0) +#define BASE_COLOR_SIZE_555 (5 << 0) +#define BASE_COLOR_SIZE_565 (6 << 0) +#define BASE_COLOR_SIZE_332 (7 << 0) +#define BASE_COLOR_SIZE_888 (8 << 0) +#define BASE_COLOR_SIZE_101010 (10 << 0) +#define BASE_COLOR_SIZE_121212 (12 << 0) #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 #define SC1_H_QUALIFIER_NONE (1 << 16) From patchwork Tue Nov 5 02:23:21 2019 Content-Type: text/plain; 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[97.126.66.56]) by smtp.gmail.com with ESMTPSA id v14sm11995297pfm.51.2019.11.04.18.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 18:23:29 -0800 (PST) From: Jamal Shareef To: outreachy-kernel@googlegroups.com Cc: thierry.reding@gmail.com, airlied@linux.ie, daniel@ffwll.ch, jonathanh@nvidia.com, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Jamal Shareef Subject: [PATCH 2/3] drm/tegra: dsi: Remove space in open parenthesis Date: Mon, 4 Nov 2019 18:23:21 -0800 Message-Id: <4357d243bdb0ac22a36f3edb0f08820fbc31348b.1572920482.git.jamal.k.shareef@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Removes space after open left parenthesis. Issue found by checkpatch. Signed-off-by: Jamal Shareef --- drivers/gpu/drm/tegra/dsi.c | 60 ++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index a5d47e301c5f..5966d33831e4 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -283,32 +283,32 @@ static void tegra_dsi_early_unregister(struct drm_connector *connector) * non-burst mode with sync pulses */ static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { - [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | + [0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | PKT_LP, - [ 1] = 0, - [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | + [1] = 0, + [2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | PKT_LP, - [ 3] = 0, - [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [3] = 0, + [4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | PKT_LP, - [ 5] = 0, - [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [5] = 0, + [6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), - [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | + [7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), - [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | PKT_LP, - [ 9] = 0, + [9] = 0, [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), @@ -321,26 +321,26 @@ static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { * non-burst mode with sync events */ static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { - [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | + [0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | PKT_LP, - [ 1] = 0, - [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [1] = 0, + [2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | PKT_LP, - [ 3] = 0, - [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [3] = 0, + [4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | PKT_LP, - [ 5] = 0, - [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [5] = 0, + [6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), - [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), - [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | + [7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), + [8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | PKT_LP, - [ 9] = 0, + [9] = 0, [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), @@ -348,16 +348,16 @@ static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { }; static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { - [ 0] = 0, - [ 1] = 0, - [ 2] = 0, - [ 3] = 0, - [ 4] = 0, - [ 5] = 0, - [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, - [ 7] = 0, - [ 8] = 0, - [ 9] = 0, + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0, + [4] = 0, + [5] = 0, + [6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, + [7] = 0, + [8] = 0, + [9] = 0, [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, [11] = 0, }; From patchwork Tue Nov 5 02:23:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamal Shareef X-Patchwork-Id: 1189285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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[97.126.66.56]) by smtp.gmail.com with ESMTPSA id v17sm21482274pfc.41.2019.11.04.18.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 18:23:30 -0800 (PST) From: Jamal Shareef To: outreachy-kernel@googlegroups.com Cc: thierry.reding@gmail.com, airlied@linux.ie, daniel@ffwll.ch, jonathanh@nvidia.com, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Jamal Shareef Subject: [PATCH 3/3] drm/tegra: gr3d: Remove space after parenthesis Date: Mon, 4 Nov 2019 18:23:22 -0800 Message-Id: <54df25088b18fb99e44cfa3fb28d65ef8a0d3e40.1572920482.git.jamal.k.shareef@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Removes spaces after open parenthesis. Issue found by checkpatch. Signed-off-by: Jamal Shareef --- drivers/gpu/drm/tegra/gr3d.c | 120 +++++++++++++++++------------------ 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c index 8b9a35b1cbb3..35d1dff067b7 100644 --- a/drivers/gpu/drm/tegra/gr3d.c +++ b/drivers/gpu/drm/tegra/gr3d.c @@ -176,16 +176,16 @@ static const struct of_device_id tegra_gr3d_match[] = { MODULE_DEVICE_TABLE(of, tegra_gr3d_match); static const u32 gr3d_addr_regs[] = { - GR3D_IDX_ATTRIBUTE( 0), - GR3D_IDX_ATTRIBUTE( 1), - GR3D_IDX_ATTRIBUTE( 2), - GR3D_IDX_ATTRIBUTE( 3), - GR3D_IDX_ATTRIBUTE( 4), - GR3D_IDX_ATTRIBUTE( 5), - GR3D_IDX_ATTRIBUTE( 6), - GR3D_IDX_ATTRIBUTE( 7), - GR3D_IDX_ATTRIBUTE( 8), - GR3D_IDX_ATTRIBUTE( 9), + GR3D_IDX_ATTRIBUTE(0), + GR3D_IDX_ATTRIBUTE(1), + GR3D_IDX_ATTRIBUTE(2), + GR3D_IDX_ATTRIBUTE(3), + GR3D_IDX_ATTRIBUTE(4), + GR3D_IDX_ATTRIBUTE(5), + GR3D_IDX_ATTRIBUTE(6), + GR3D_IDX_ATTRIBUTE(7), + GR3D_IDX_ATTRIBUTE(8), + GR3D_IDX_ATTRIBUTE(9), GR3D_IDX_ATTRIBUTE(10), GR3D_IDX_ATTRIBUTE(11), GR3D_IDX_ATTRIBUTE(12), @@ -196,16 +196,16 @@ static const u32 gr3d_addr_regs[] = { GR3D_QR_ZTAG_ADDR, GR3D_QR_CTAG_ADDR, GR3D_QR_CZ_ADDR, - GR3D_TEX_TEX_ADDR( 0), - GR3D_TEX_TEX_ADDR( 1), - GR3D_TEX_TEX_ADDR( 2), - GR3D_TEX_TEX_ADDR( 3), - GR3D_TEX_TEX_ADDR( 4), - GR3D_TEX_TEX_ADDR( 5), - GR3D_TEX_TEX_ADDR( 6), - GR3D_TEX_TEX_ADDR( 7), - GR3D_TEX_TEX_ADDR( 8), - GR3D_TEX_TEX_ADDR( 9), + GR3D_TEX_TEX_ADDR(0), + GR3D_TEX_TEX_ADDR(1), + GR3D_TEX_TEX_ADDR(2), + GR3D_TEX_TEX_ADDR(3), + GR3D_TEX_TEX_ADDR(4), + GR3D_TEX_TEX_ADDR(5), + GR3D_TEX_TEX_ADDR(6), + GR3D_TEX_TEX_ADDR(7), + GR3D_TEX_TEX_ADDR(8), + GR3D_TEX_TEX_ADDR(9), GR3D_TEX_TEX_ADDR(10), GR3D_TEX_TEX_ADDR(11), GR3D_TEX_TEX_ADDR(12), @@ -213,16 +213,16 @@ static const u32 gr3d_addr_regs[] = { GR3D_TEX_TEX_ADDR(14), GR3D_TEX_TEX_ADDR(15), GR3D_DW_MEMORY_OUTPUT_ADDRESS, - GR3D_GLOBAL_SURFADDR( 0), - GR3D_GLOBAL_SURFADDR( 1), - GR3D_GLOBAL_SURFADDR( 2), - GR3D_GLOBAL_SURFADDR( 3), - GR3D_GLOBAL_SURFADDR( 4), - GR3D_GLOBAL_SURFADDR( 5), - GR3D_GLOBAL_SURFADDR( 6), - GR3D_GLOBAL_SURFADDR( 7), - GR3D_GLOBAL_SURFADDR( 8), - GR3D_GLOBAL_SURFADDR( 9), + GR3D_GLOBAL_SURFADDR(0), + GR3D_GLOBAL_SURFADDR(1), + GR3D_GLOBAL_SURFADDR(2), + GR3D_GLOBAL_SURFADDR(3), + GR3D_GLOBAL_SURFADDR(4), + GR3D_GLOBAL_SURFADDR(5), + GR3D_GLOBAL_SURFADDR(6), + GR3D_GLOBAL_SURFADDR(7), + GR3D_GLOBAL_SURFADDR(8), + GR3D_GLOBAL_SURFADDR(9), GR3D_GLOBAL_SURFADDR(10), GR3D_GLOBAL_SURFADDR(11), GR3D_GLOBAL_SURFADDR(12), @@ -230,48 +230,48 @@ static const u32 gr3d_addr_regs[] = { GR3D_GLOBAL_SURFADDR(14), GR3D_GLOBAL_SURFADDR(15), GR3D_GLOBAL_SPILLSURFADDR, - GR3D_GLOBAL_SURFOVERADDR( 0), - GR3D_GLOBAL_SURFOVERADDR( 1), - GR3D_GLOBAL_SURFOVERADDR( 2), - GR3D_GLOBAL_SURFOVERADDR( 3), - GR3D_GLOBAL_SURFOVERADDR( 4), - GR3D_GLOBAL_SURFOVERADDR( 5), - GR3D_GLOBAL_SURFOVERADDR( 6), - GR3D_GLOBAL_SURFOVERADDR( 7), - GR3D_GLOBAL_SURFOVERADDR( 8), - GR3D_GLOBAL_SURFOVERADDR( 9), + GR3D_GLOBAL_SURFOVERADDR(0), + GR3D_GLOBAL_SURFOVERADDR(1), + GR3D_GLOBAL_SURFOVERADDR(2), + GR3D_GLOBAL_SURFOVERADDR(3), + GR3D_GLOBAL_SURFOVERADDR(4), + GR3D_GLOBAL_SURFOVERADDR(5), + GR3D_GLOBAL_SURFOVERADDR(6), + GR3D_GLOBAL_SURFOVERADDR(7), + GR3D_GLOBAL_SURFOVERADDR(8), + GR3D_GLOBAL_SURFOVERADDR(9), GR3D_GLOBAL_SURFOVERADDR(10), GR3D_GLOBAL_SURFOVERADDR(11), GR3D_GLOBAL_SURFOVERADDR(12), GR3D_GLOBAL_SURFOVERADDR(13), GR3D_GLOBAL_SURFOVERADDR(14), GR3D_GLOBAL_SURFOVERADDR(15), - GR3D_GLOBAL_SAMP01SURFADDR( 0), - GR3D_GLOBAL_SAMP01SURFADDR( 1), - GR3D_GLOBAL_SAMP01SURFADDR( 2), - GR3D_GLOBAL_SAMP01SURFADDR( 3), - GR3D_GLOBAL_SAMP01SURFADDR( 4), - GR3D_GLOBAL_SAMP01SURFADDR( 5), - GR3D_GLOBAL_SAMP01SURFADDR( 6), - GR3D_GLOBAL_SAMP01SURFADDR( 7), - GR3D_GLOBAL_SAMP01SURFADDR( 8), - GR3D_GLOBAL_SAMP01SURFADDR( 9), + GR3D_GLOBAL_SAMP01SURFADDR(0), + GR3D_GLOBAL_SAMP01SURFADDR(1), + GR3D_GLOBAL_SAMP01SURFADDR(2), + GR3D_GLOBAL_SAMP01SURFADDR(3), + GR3D_GLOBAL_SAMP01SURFADDR(4), + GR3D_GLOBAL_SAMP01SURFADDR(5), + GR3D_GLOBAL_SAMP01SURFADDR(6), + GR3D_GLOBAL_SAMP01SURFADDR(7), + GR3D_GLOBAL_SAMP01SURFADDR(8), + GR3D_GLOBAL_SAMP01SURFADDR(9), GR3D_GLOBAL_SAMP01SURFADDR(10), GR3D_GLOBAL_SAMP01SURFADDR(11), GR3D_GLOBAL_SAMP01SURFADDR(12), GR3D_GLOBAL_SAMP01SURFADDR(13), GR3D_GLOBAL_SAMP01SURFADDR(14), GR3D_GLOBAL_SAMP01SURFADDR(15), - GR3D_GLOBAL_SAMP23SURFADDR( 0), - GR3D_GLOBAL_SAMP23SURFADDR( 1), - GR3D_GLOBAL_SAMP23SURFADDR( 2), - GR3D_GLOBAL_SAMP23SURFADDR( 3), - GR3D_GLOBAL_SAMP23SURFADDR( 4), - GR3D_GLOBAL_SAMP23SURFADDR( 5), - GR3D_GLOBAL_SAMP23SURFADDR( 6), - GR3D_GLOBAL_SAMP23SURFADDR( 7), - GR3D_GLOBAL_SAMP23SURFADDR( 8), - GR3D_GLOBAL_SAMP23SURFADDR( 9), + GR3D_GLOBAL_SAMP23SURFADDR(0), + GR3D_GLOBAL_SAMP23SURFADDR(1), + GR3D_GLOBAL_SAMP23SURFADDR(2), + GR3D_GLOBAL_SAMP23SURFADDR(3), + GR3D_GLOBAL_SAMP23SURFADDR(4), + GR3D_GLOBAL_SAMP23SURFADDR(5), + GR3D_GLOBAL_SAMP23SURFADDR(6), + GR3D_GLOBAL_SAMP23SURFADDR(7), + GR3D_GLOBAL_SAMP23SURFADDR(8), + GR3D_GLOBAL_SAMP23SURFADDR(9), GR3D_GLOBAL_SAMP23SURFADDR(10), GR3D_GLOBAL_SAMP23SURFADDR(11), GR3D_GLOBAL_SAMP23SURFADDR(12),