From patchwork Wed Oct 16 14:58:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1177975 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="psOOW2oH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46tb886jNXz9sCJ for ; Thu, 17 Oct 2019 02:00:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 80837C21CB1; Wed, 16 Oct 2019 14:59:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ECAD8C21C93; Wed, 16 Oct 2019 14:58:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 84612C21D9A; Wed, 16 Oct 2019 14:58:34 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 813B8C21DA6 for ; Wed, 16 Oct 2019 14:58:31 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id r1so13265244pgj.12 for ; Wed, 16 Oct 2019 07:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v1+PrDVA5aM4W4ZnvQQhmQ8krJlVxvNiADXWnLTzIbM=; b=psOOW2oHEPT5E+1Q0FJg9kR5KpnD+d2Pwob571lVP0vVcMVOx1S1Vy8uC0+7K7vS2i ePu42KcHbYqStf+o6izTtYxPwSh3Ncd/ujU3aUPyiPFpNRwj3kFyIr2W3FDwZGY+sHOT sHC/sA8Le5S++YwLIqNytQMABA7rHBY4bJnG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v1+PrDVA5aM4W4ZnvQQhmQ8krJlVxvNiADXWnLTzIbM=; b=O5W9yGjYFUU3pB636p3S30mWkak/96YtT7sGlZduIJvehAs4lXgVo0jAGOcd+naAnD 4vMmjyG5XERFIMwLxmIvhZIALMyPPK4B/a5il2f2Hyy9SDtDBEg393Iu45bQTvYiJiUh uoWz9KPXYhXipdCcGW4heDozOwpucMqlx13I2AmZDinZPLqGQ/oEvOp+9zA0/AvzchkT 38kVDhYIVSoLQQHCB/KLRtxNCtBBwPigxDR+DKpxjCR0vGOQaKnASICS5wcCOffD4NOj YlqcbOmBm1AxTA+6cXpPo+Zi8GGzIW9Lo6czoE/cAyAr/H9YOagCNqePDpr+Gw93Bi6h woMw== X-Gm-Message-State: APjAAAWfghWOVbsNgPD5LMKCb+M5uPlI86AuSAFzydSndTFHq0gNR1Uy mwQ5Y2xNu/WSHCMGhaSU6xv0SA== X-Google-Smtp-Source: APXvYqxZ5S6Ia3i1zp5gOfBWLZy1dhlTT3OfOANb39fuqiFFdXDHMF7B3EPBlyjmI3KJjEW8ExiVcQ== X-Received: by 2002:a17:90a:9104:: with SMTP id k4mr5527025pjo.39.1571237909687; Wed, 16 Oct 2019 07:58:29 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.31]) by smtp.gmail.com with ESMTPSA id q29sm5534110pgc.36.2019.10.16.07.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 07:58:29 -0700 (PDT) From: Jagan Teki To: Rick Chen , Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Bin Meng Date: Wed, 16 Oct 2019 20:28:10 +0530 Message-Id: <20191016145814.19036-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191016145814.19036-1-jagan@amarulasolutions.com> References: <20191016145814.19036-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com Subject: [U-Boot] [PATCH v2 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive Unleashed: add default chosen/stdout-path") Idea is to periodically sync the dts from Linux instead of tweaking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing device tree files from Linux. Signed-off-by: Jagan Teki --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 251 ++++++++++++++++++++++++ arch/riscv/dts/hifive-unleashed-a00.dts | 96 +++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f9cd606a9a..4f30e6936f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi new file mode 100644 index 0000000000..afa43c7ea3 --- /dev/null +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = ð0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci PRCI_CLK_TLCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <42 43 44 45>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <46 47 48 49>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + + }; +}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..88cfcb96bf --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = ; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; From patchwork Wed Oct 16 14:58:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1177976 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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bh=3BqjJp+ulFFSn+3SG+CtJU6b463eKl02kIBKbwp/zvY=; b=BIhAf484mVSohUKgvFlwZD8B7UPXDDuU7hQtgg3rnOlONfnhscTBuWDieBrFPB8ENq yLulbTfVrf9hY6msSYyDFdW2vJqwR/DDLDNhw1rbY5BRai/B0/mViUi02XkffVQbqcRB W0aOreXX/D7EtlAMXEkqYS8Emvjg5n9NOOP5A1x3gXH7/s5qSq5cYJuBgMLNvc1NG5rQ sy30RK2dhOWycr02BQ1IFVBuZxw5rBrOZWysDlF9fNArJmTvSa6UB4whMYMnPzT8yR0t m3cS25fBGP/xh0wBolf/mfsCDG/mvQxM6bgpZ1qTYubNoiaO1eIICVyMBLnXAa/azrOD SNUw== X-Gm-Message-State: APjAAAUxVLtQpotKZ46FP9sarvied1exVnlQs44aO/BVtw2uuZikD6I8 wVuWJ62BEs2RiuUfYJiHht3v9w== X-Google-Smtp-Source: APXvYqx6p/FRtkCTaqgscHVXvWtXk6NYQHrU+YNRzBZirOXC5r99AQ7vAB0Kr3TmxE6FC3F5FU7w8w== X-Received: by 2002:a17:90a:5d0f:: with SMTP id s15mr5558310pji.126.1571237913175; Wed, 16 Oct 2019 07:58:33 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.31]) by smtp.gmail.com with ESMTPSA id q29sm5534110pgc.36.2019.10.16.07.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 07:58:32 -0700 (PDT) From: Jagan Teki To: Rick Chen , Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Bin Meng Date: Wed, 16 Oct 2019 20:28:11 +0530 Message-Id: <20191016145814.19036-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191016145814.19036-1-jagan@amarulasolutions.com> References: <20191016145814.19036-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com Subject: [U-Boot] [PATCH v2 2/5] sifive: fu540: Enable OF_SEPARATE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi. This would help to make the necessary changes in drivers and devicetrees in uboot tree itself. this feature would also be helpful to not pass dtb during opensbi builds. Signed-off-by: Jagan Teki --- configs/sifive_fu540_defconfig | 3 ++- doc/board/sifive/fu540.rst | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 48865e5f11..979d0a0418 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -6,6 +6,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_MISC_INIT_R=y +CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_SEPARATE=y diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 7807f5b2c1..91b94ee06f 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -58,7 +58,7 @@ firmware. We need to compile OpenSBI with below command: .. code-block:: none - make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= FW_PAYLOAD_FDT_PATH= + make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= (Note: Prefer hifive-unleashed-a00.dtb from Linux-5.3 or higher) (Note: Linux-5.2 is also fine but it does not have ethernet DT node) From patchwork Wed Oct 16 14:58:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1177973 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ZKjr7dlb"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46tb6X1TxVz9sPh for ; Thu, 17 Oct 2019 01:59:16 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C8CDBC21CB6; Wed, 16 Oct 2019 14:58:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A4CF7C21E07; Wed, 16 Oct 2019 14:58:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E4138C21CB1; Wed, 16 Oct 2019 14:58:39 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id 06826C21DC1 for ; Wed, 16 Oct 2019 14:58:38 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id q15so11386348pll.11 for ; Wed, 16 Oct 2019 07:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=20VlbFnkHE/Hf/2m8B1RQ50+Fs0CsojlBBg26jtu/4o=; b=ZKjr7dlb5B8gj9e/nOHMk0TgLzDpnDZRjaqlTHHw+plEqmJYyhxVWzPDx5bAe/tNcY jlHAF8Mhr68P9l3yjMDAmfwQpu3TaDamRU8+xGCRK8s0Boldve3QTRiVYkHkuD6Y6EUY GUseNYopO0x2BaoKO64psu0oIRZWCp4d1s2bM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=20VlbFnkHE/Hf/2m8B1RQ50+Fs0CsojlBBg26jtu/4o=; b=tcz++E/N7XbpZXPiepwFKJ57aXPBD31fCGxEE15XZhAvC3oZbCVx+1SxCnXQNIcYpr gAJqqCQOKCvvB/OE+p0KJ7ql2iPFZysMGpgkg10zft6mlxDHmnSqNHa36Fnorm1ewRy5 i6Lm9Fq4mn+T+Fq7A9WYOUT1GPLfBr9PihWOZvWAH+Z1YtojB/DpxKPvB6ZPACzhxYNd doovWTpQxnR4W7zhFCeVJTRGouo7/ZaDD+Pu81493Uy+VIZGuAxQCkDCrzgYoVWyy8HD L/G0m2tJjUkjmGjbyJp/3pqg7Q9nU3gLd+xKw2Kt6+SYurYq8oo2Scm0a3ysmIvP4/uA yZQg== X-Gm-Message-State: APjAAAU3790ihCSe1hE6qcE6uAy3KQ9QJTnwsjFZQeufT/Phgn4NiZzm lccS+LrqZzI2QhFGGFgrqp3pIg== X-Google-Smtp-Source: APXvYqzXAdgz8IdErEoR4SlK2J/loNM/BxLfaEUgukjUbhQm26Ak0CrNzCAf9WqgCF6GUDspkF9+Aw== X-Received: by 2002:a17:902:a514:: with SMTP id s20mr40953302plq.157.1571237916308; Wed, 16 Oct 2019 07:58:36 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.31]) by smtp.gmail.com with ESMTPSA id q29sm5534110pgc.36.2019.10.16.07.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 07:58:35 -0700 (PDT) From: Jagan Teki To: Rick Chen , Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Bin Meng Date: Wed, 16 Oct 2019 20:28:12 +0530 Message-Id: <20191016145814.19036-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191016145814.19036-1-jagan@amarulasolutions.com> References: <20191016145814.19036-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com Subject: [U-Boot] [PATCH v2 3/5] mtd: spi-nor: ids: Add is25wp256 chip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 6996c0a286..04db986561 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -128,6 +128,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ From patchwork Wed Oct 16 14:58:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1177974 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="PvSNDpQ9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46tb7P0Kfpz9sPK for ; Thu, 17 Oct 2019 02:00:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B7CE9C21CB1; Wed, 16 Oct 2019 14:59:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 34875C21D56; Wed, 16 Oct 2019 14:58:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0B54EC21D9A; Wed, 16 Oct 2019 14:58:41 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id E9BEDC21C27 for ; Wed, 16 Oct 2019 14:58:40 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id t10so11391784plr.8 for ; Wed, 16 Oct 2019 07:58:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WCrSXHULd2WrBjIQ3nvzpUExJcEaw9mMZr11Mt1cgm0=; b=PvSNDpQ9fdq3HzWRzq59kjsH/vLLb71CfxJ9+xRLK0UMoalAbQ+4AMzK49YVhQlCLr AoiGbEIvM3IFbao+48Dr1hWte6L67SfzCIkPwZ5aH0OGv5LwDAPCD9DYc42Qq0GzaFKj s2TNxC3Cz5w6uJoMEoa6Oncp4+6pKFvURDQak= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WCrSXHULd2WrBjIQ3nvzpUExJcEaw9mMZr11Mt1cgm0=; b=OGs1kWEZmlzibotj7Uhu2V+MZBIs2FpJ9Guv+16qHPU3dNlYMSdEKPqm+ftxb6Q4DJ g/SK+jGKERkMQsIUUF6yVdFK0KerGS99a+zB3K/queqJK9yCuWDqP9m0h6V3b/Y2gbRb WHEl6NZNQShl6AvNULiO6x2l+PMnHX+Z3bk9zHqfdXRWtu5H9edr69HvHs1m69CHNQ0T ZNyDtslXNfa2Z41U4mNooI9NAS1Jtx+OIhm1dOjCsCCWri/1uY/YPpuTI5C7Je2dSYng jDRbtUptYmya2XoGIp5H5x7xBbIqX667cTMfRAdT3wMQ2IL9dJ5+9dlgurTUF/UHpCc0 9vwA== X-Gm-Message-State: APjAAAUcPaUgqk73hKpGcqIba5R4oBy4IKf4FGzthfGezcrhWi8YrcYU 7+MLIzX7jsiYUwhh6rTwU29SsQ== X-Google-Smtp-Source: APXvYqwtDJrBY02OWjVvf11Kfmr+YGRXJlc38W5OoMkfvfCuZ2lONixvs62KDZ/aGhG6v+6SqEOqbw== X-Received: by 2002:a17:902:a581:: with SMTP id az1mr40718752plb.311.1571237919464; Wed, 16 Oct 2019 07:58:39 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.31]) by smtp.gmail.com with ESMTPSA id q29sm5534110pgc.36.2019.10.16.07.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 07:58:39 -0700 (PDT) From: Jagan Teki To: Rick Chen , Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Bin Meng Date: Wed, 16 Oct 2019 20:28:13 +0530 Message-Id: <20191016145814.19036-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191016145814.19036-1-jagan@amarulasolutions.com> References: <20191016145814.19036-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com Subject: [U-Boot] [PATCH v2 4/5] riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add u-boot specific dts file for hifive-unleashed-a00, this would help to add u-boot specific properties and other node changes without touching the base dts(i) files which are easy to sync from Linux. Added spi2 alias for qspi2 as an initial u-boot specific property change. spi probing in current dm model is very much rely on aliases numbering. even though the qspi2 can't comes under any associated spi nor flash it would require to specify the same to make proper binding happen for other spi slaves. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi new file mode 100644 index 0000000000..25ec8265a5 --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +/ { + aliases { + spi2 = &qspi2; + }; +}; From patchwork Wed Oct 16 14:58:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1177979 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="EHDGwzfT"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46tb8t0cLnz9sPT for ; Thu, 17 Oct 2019 02:01:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C59C2C21E30; Wed, 16 Oct 2019 14:59:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 020BFC21DD7; Wed, 16 Oct 2019 14:59:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 34FABC21D65; Wed, 16 Oct 2019 14:58:44 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 19EEFC21E0D for ; Wed, 16 Oct 2019 14:58:44 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id w3so7539772pgt.5 for ; Wed, 16 Oct 2019 07:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SOCVAvPsRYDpSRDxPEOCO6YNiPCeKidJufsPcI7teE8=; b=EHDGwzfT27IML7GyB24yLn3/VN4CDNcPC18wSXWTgKWldD7jDYzrqAkb/wpWTqPP5P fksc8XtLvI8ckoi+BhUat0A+np2sHHpeCqpPLuesPGa6aan8BBVacxgmgdl3ygFSMuDW bSZ+endI5EXOaa5oORppmYCtY2MIX20zM5S5Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SOCVAvPsRYDpSRDxPEOCO6YNiPCeKidJufsPcI7teE8=; b=NmnuTHDQwt8yQfIUnjPuMueqJyHHoavNHkUjni7HYebBqWPBf+rAJ8ZjsErOFBpMoq XlRs5ApmBoJcHo+lO1E3wbwQiptcv/jjufTXtvuBXKV8tDZqDto1cUinI5FILOlg1ZoZ mbfM852w/dZbDGR0HWPRT0Snd1PMIuDL3eTg9siwOODCdvQgBkSvrci5radfMDQc3B4W Oz5WD9NX3IKrdl+Q6zJ3IfHC+GSzLIAm/SJ+GEIotZBx8bSVUwh5it/bEn4LfUbQbGKq d5LryENyd1BGJXBKrTAGUBhOx0X92pKLerZVIa4YMH0XLIJp8hwO/Bff804M6sczAA+C pfuw== X-Gm-Message-State: APjAAAU/fkpNNss/8nik/J1ntiUW3qCaC7vVBskmjyGdX5NB1Hv3zKQI ipWGjk/WmRSok7UMCuRUKxuSng== X-Google-Smtp-Source: APXvYqx4YU5be+apUEfP94aIFyVAaJsOZIjSTtIbWkns5fkm4SiFD3DE9XIB6mvQHOBUScXCtzjDag== X-Received: by 2002:a17:90a:e98d:: with SMTP id v13mr5579095pjy.64.1571237922600; Wed, 16 Oct 2019 07:58:42 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.31]) by smtp.gmail.com with ESMTPSA id q29sm5534110pgc.36.2019.10.16.07.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 07:58:42 -0700 (PDT) From: Jagan Teki To: Rick Chen , Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Bin Meng Date: Wed, 16 Oct 2019 20:28:14 +0530 Message-Id: <20191016145814.19036-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191016145814.19036-1-jagan@amarulasolutions.com> References: <20191016145814.19036-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com Subject: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 + board/sifive/fu540/Kconfig | 3 +++ doc/board/sifive/fu540.rst | 19 +++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 25ec8265a5..d7a64134db 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -5,6 +5,7 @@ / { aliases { + spi0 = &qspi0; spi2 = &qspi2; }; }; diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 5d65080429..c5a1bca03c 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FS_GENERIC imply CMD_NET imply CMD_PING + imply CMD_SF imply CLK_SIFIVE imply CLK_SIFIVE_FU540_PRCI imply DOS_PARTITION @@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SIFIVE_SERIAL imply SPI imply SPI_SIFIVE + imply SPI_FLASH + imply SPI_FLASH_ISSI imply MMC imply MMC_SPI imply MMC_BROKEN_CD diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 91b94ee06f..2e70cad02e 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -366,3 +366,22 @@ load uImage. Please press Enter to activate this console. / # + +Sample spi nor flash test +------------------------- + +.. code-block:: none + + => sf probe 0:2 + SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB + => sf erase 0x1000000 0x100000 + SF: 1048576 bytes @ 0x1000000 Erased: OK + => mw.b 0xc0000000 0xaa 0x100000 + => sf write 0xc0000000 0x1000000 0x100000 + device 0 offset 0x1000000, size 0x100000 + SF: 1048576 bytes @ 0x1000000 Written: OK + => sf read 0xf0000000 0x1000000 0x100000 + device 0 offset 0x1000000, size 0x100000 + SF: 1048576 bytes @ 0x1000000 Read: OK + => cmp.b 0xf0000000 0xc0000000 0x100000 + Total of 1048576 byte(s) were the same