From patchwork Tue Oct 1 06:59:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9cC5S23z9sN1 for ; Tue, 1 Oct 2019 17:18:51 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9cC4FSNzDqHK for ; Tue, 1 Oct 2019 17:18:51 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=178.32.119.138; helo=6.mo5.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 6.mo5.mail-out.ovh.net (6.mo5.mail-out.ovh.net [178.32.119.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9c606NKzDqF1 for ; Tue, 1 Oct 2019 17:18:42 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.42.23]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 7CCE7250AED for ; Tue, 1 Oct 2019 09:00:17 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id B5791A3AB6EF; Tue, 1 Oct 2019 07:00:12 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:46 +0200 Message-Id: <20191001070002.20271-2-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17978651190835776473 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 01/17] xive/p9: introduce header files for the registers X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is moving the definitions of the registers of the P9 XIVE interrupt controller and the P9 XIVE internal structures in a specific header file and moving the definitions related to the thread interrupt context area to a common file. Signed-off-by: Cédric Le Goater --- include/xive-p9-regs.h | 391 ++++++++++++++++++++++++++++++++++ include/xive-regs.h | 89 ++++++++ include/xive.h | 463 +---------------------------------------- hw/xive.c | 6 +- 4 files changed, 490 insertions(+), 459 deletions(-) create mode 100644 include/xive-p9-regs.h create mode 100644 include/xive-regs.h diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h new file mode 100644 index 000000000000..f6b7c20b322e --- /dev/null +++ b/include/xive-p9-regs.h @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: Apache-2.0 +/* + * XIVE: eXternal Interrupt Virtualization Engine. POWER9 interrupt + * controller + * + * Copyright (c) 2016-2019, IBM Corporation. + */ +#ifndef XIVE_P9_REGS_H +#define XIVE_P9_REGS_H + +#include + +/* IC register offsets */ +#define CQ_SWI_CMD_HIST 0x020 +#define CQ_SWI_CMD_POLL 0x028 +#define CQ_SWI_CMD_BCAST 0x030 +#define CQ_SWI_CMD_ASSIGN 0x038 +#define CQ_SWI_CMD_BLK_UPD 0x040 +#define CQ_SWI_RSP 0x048 +#define X_CQ_CFG_PB_GEN 0x0a +#define CQ_CFG_PB_GEN 0x050 +#define CQ_INT_ADDR_OPT PPC_BITMASK(14,15) +#define X_CQ_IC_BAR 0x10 +#define X_CQ_MSGSND 0x0b +#define CQ_MSGSND 0x058 +#define CQ_CNPM_SEL 0x078 +#define CQ_IC_BAR 0x080 +#define CQ_IC_BAR_VALID PPC_BIT(0) +#define CQ_IC_BAR_64K PPC_BIT(1) +#define X_CQ_TM1_BAR 0x12 +#define CQ_TM1_BAR 0x90 +#define X_CQ_TM2_BAR 0x014 +#define CQ_TM2_BAR 0x0a0 +#define CQ_TM_BAR_VALID PPC_BIT(0) +#define CQ_TM_BAR_64K PPC_BIT(1) +#define X_CQ_PC_BAR 0x16 +#define CQ_PC_BAR 0x0b0 +#define CQ_PC_BAR_VALID PPC_BIT(0) +#define X_CQ_PC_BARM 0x17 +#define CQ_PC_BARM 0x0b8 +#define CQ_PC_BARM_MASK PPC_BITMASK(26,38) +#define X_CQ_VC_BAR 0x18 +#define CQ_VC_BAR 0x0c0 +#define CQ_VC_BAR_VALID PPC_BIT(0) +#define X_CQ_VC_BARM 0x19 +#define CQ_VC_BARM 0x0c8 +#define CQ_VC_BARM_MASK PPC_BITMASK(21,37) +#define X_CQ_TAR 0x1e +#define CQ_TAR 0x0f0 +#define CQ_TAR_TBL_AUTOINC PPC_BIT(0) +#define CQ_TAR_TSEL_BLK PPC_BIT(12) +#define CQ_TAR_TSEL_MIG PPC_BIT(13) +#define CQ_TAR_TSEL_VDT PPC_BIT(14) +#define CQ_TAR_TSEL_EDT PPC_BIT(15) +#define X_CQ_TDR 0x1f +#define CQ_TDR 0x0f8 +#define X_CQ_PBI_CTL 0x20 +#define CQ_PBI_CTL 0x100 +#define CQ_PBI_PC_64K PPC_BIT(5) +#define CQ_PBI_VC_64K PPC_BIT(6) +#define CQ_PBI_LNX_TRIG PPC_BIT(7) +#define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) +#define CQ_PBO_CTL 0x108 +#define CQ_AIB_CTL 0x110 +#define X_CQ_RST_CTL 0x23 +#define CQ_RST_CTL 0x118 +#define X_CQ_FIRMASK 0x33 +#define CQ_FIRMASK 0x198 +#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) +#define CQ_FIR_VC_INFO_ERROR_0_1 PPC_BITMASK(62,63) +#define X_CQ_FIRMASK_AND 0x34 +#define CQ_FIRMASK_AND 0x1a0 +#define X_CQ_FIRMASK_OR 0x35 +#define CQ_FIRMASK_OR 0x1a8 + +/* PC LBS1 register offsets */ +#define X_PC_TCTXT_CFG 0x100 +#define PC_TCTXT_CFG 0x400 +#define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) +#define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) +#define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) +#define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) +#define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) +#define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) +#define PC_TCTXT_CHIPID PPC_BITMASK(12,15) +#define PC_TCTXT_INIT_AGE PPC_BITMASK(30,31) +#define X_PC_TCTXT_TRACK 0x101 +#define PC_TCTXT_TRACK 0x408 +#define PC_TCTXT_TRACK_EN PPC_BIT(0) +#define X_PC_TCTXT_INDIR0 0x104 +#define PC_TCTXT_INDIR0 0x420 +#define PC_TCTXT_INDIR_VALID PPC_BIT(0) +#define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9,15) +#define X_PC_TCTXT_INDIR1 0x105 +#define PC_TCTXT_INDIR1 0x428 +#define X_PC_TCTXT_INDIR2 0x106 +#define PC_TCTXT_INDIR2 0x430 +#define X_PC_TCTXT_INDIR3 0x107 +#define PC_TCTXT_INDIR3 0x438 +#define X_PC_THREAD_EN_REG0 0x108 +#define PC_THREAD_EN_REG0 0x440 +#define X_PC_THREAD_EN_REG0_SET 0x109 +#define PC_THREAD_EN_REG0_SET 0x448 +#define X_PC_THREAD_EN_REG0_CLR 0x10a +#define PC_THREAD_EN_REG0_CLR 0x450 +#define X_PC_THREAD_EN_REG1 0x10c +#define PC_THREAD_EN_REG1 0x460 +#define X_PC_THREAD_EN_REG1_SET 0x10d +#define PC_THREAD_EN_REG1_SET 0x468 +#define X_PC_THREAD_EN_REG1_CLR 0x10e +#define PC_THREAD_EN_REG1_CLR 0x470 +#define X_PC_GLOBAL_CONFIG 0x110 +#define PC_GLOBAL_CONFIG 0x480 +#define PC_GCONF_INDIRECT PPC_BIT(32) +#define PC_GCONF_CHIPID_OVR PPC_BIT(40) +#define PC_GCONF_CHIPID PPC_BITMASK(44,47) +#define X_PC_VSD_TABLE_ADDR 0x111 +#define PC_VSD_TABLE_ADDR 0x488 +#define X_PC_VSD_TABLE_DATA 0x112 +#define PC_VSD_TABLE_DATA 0x490 +#define X_PC_AT_KILL 0x116 +#define PC_AT_KILL 0x4b0 +#define PC_AT_KILL_VALID PPC_BIT(0) +#define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27,31) +#define PC_AT_KILL_OFFSET PPC_BITMASK(48,60) +#define X_PC_AT_KILL_MASK 0x117 +#define PC_AT_KILL_MASK 0x4b8 + +/* PC LBS2 register offsets */ +#define X_PC_VPC_CACHE_ENABLE 0x161 +#define PC_VPC_CACHE_ENABLE 0x708 +#define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0,31) +#define X_PC_VPC_SCRUB_TRIG 0x162 +#define PC_VPC_SCRUB_TRIG 0x710 +#define X_PC_VPC_SCRUB_MASK 0x163 +#define PC_VPC_SCRUB_MASK 0x718 +#define PC_SCRUB_VALID PPC_BIT(0) +#define PC_SCRUB_WANT_DISABLE PPC_BIT(1) +#define PC_SCRUB_WANT_INVAL PPC_BIT(2) +#define PC_SCRUB_BLOCK_ID PPC_BITMASK(27,31) +#define PC_SCRUB_OFFSET PPC_BITMASK(45,63) +#define X_PC_VPC_CWATCH_SPEC 0x167 +#define PC_VPC_CWATCH_SPEC 0x738 +#define PC_VPC_CWATCH_CONFLICT PPC_BIT(0) +#define PC_VPC_CWATCH_FULL PPC_BIT(8) +#define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27,31) +#define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45,63) +#define X_PC_VPC_CWATCH_DAT0 0x168 +#define PC_VPC_CWATCH_DAT0 0x740 +#define X_PC_VPC_CWATCH_DAT1 0x169 +#define PC_VPC_CWATCH_DAT1 0x748 +#define X_PC_VPC_CWATCH_DAT2 0x16a +#define PC_VPC_CWATCH_DAT2 0x750 +#define X_PC_VPC_CWATCH_DAT3 0x16b +#define PC_VPC_CWATCH_DAT3 0x758 +#define X_PC_VPC_CWATCH_DAT4 0x16c +#define PC_VPC_CWATCH_DAT4 0x760 +#define X_PC_VPC_CWATCH_DAT5 0x16d +#define PC_VPC_CWATCH_DAT5 0x768 +#define X_PC_VPC_CWATCH_DAT6 0x16e +#define PC_VPC_CWATCH_DAT6 0x770 +#define X_PC_VPC_CWATCH_DAT7 0x16f +#define PC_VPC_CWATCH_DAT7 0x778 + +/* VC0 register offsets */ +#define X_VC_GLOBAL_CONFIG 0x200 +#define VC_GLOBAL_CONFIG 0x800 +#define VC_GCONF_INDIRECT PPC_BIT(32) +#define X_VC_VSD_TABLE_ADDR 0x201 +#define VC_VSD_TABLE_ADDR 0x808 +#define X_VC_VSD_TABLE_DATA 0x202 +#define VC_VSD_TABLE_DATA 0x810 +#define VC_IVE_ISB_BLOCK_MODE 0x818 +#define VC_EQD_BLOCK_MODE 0x820 +#define VC_VPS_BLOCK_MODE 0x828 +#define X_VC_IRQ_CONFIG_IPI 0x208 +#define VC_IRQ_CONFIG_IPI 0x840 +#define VC_IRQ_CONFIG_MEMB_EN PPC_BIT(45) +#define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46,51) +#define VC_IRQ_CONFIG_HW 0x848 +#define VC_IRQ_CONFIG_CASCADE1 0x850 +#define VC_IRQ_CONFIG_CASCADE2 0x858 +#define VC_IRQ_CONFIG_REDIST 0x860 +#define VC_IRQ_CONFIG_IPI_CASC 0x868 +#define X_VC_AIB_TX_ORDER_TAG2 0x22d +#define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) +#define VC_AIB_TX_ORDER_TAG2 0x890 +#define X_VC_AT_MACRO_KILL 0x23e +#define VC_AT_MACRO_KILL 0x8b0 +#define X_VC_AT_MACRO_KILL_MASK 0x23f +#define VC_AT_MACRO_KILL_MASK 0x8b8 +#define VC_KILL_VALID PPC_BIT(0) +#define VC_KILL_TYPE PPC_BITMASK(14,15) +#define VC_KILL_IRQ 0 +#define VC_KILL_IVC 1 +#define VC_KILL_SBC 2 +#define VC_KILL_EQD 3 +#define VC_KILL_BLOCK_ID PPC_BITMASK(27,31) +#define VC_KILL_OFFSET PPC_BITMASK(48,60) +#define X_VC_EQC_CACHE_ENABLE 0x211 +#define VC_EQC_CACHE_ENABLE 0x908 +#define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0,15) +#define X_VC_EQC_SCRUB_TRIG 0x212 +#define VC_EQC_SCRUB_TRIG 0x910 +#define X_VC_EQC_SCRUB_MASK 0x213 +#define VC_EQC_SCRUB_MASK 0x918 +#define X_VC_EQC_CWATCH_SPEC 0x215 +#define VC_EQC_CONFIG 0x920 +#define X_VC_EQC_CONFIG 0x214 +#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) +#define VC_EQC_CONF_SYNC_HW PPC_BIT(33) +#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) +#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) +#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) +#define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) +#define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) +#define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) +#define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) +#define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) +#define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) +#define VC_EQC_CWATCH_SPEC 0x928 +#define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) +#define VC_EQC_CWATCH_FULL PPC_BIT(8) +#define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28,31) +#define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40,63) +#define X_VC_EQC_CWATCH_DAT0 0x216 +#define VC_EQC_CWATCH_DAT0 0x930 +#define X_VC_EQC_CWATCH_DAT1 0x217 +#define VC_EQC_CWATCH_DAT1 0x938 +#define X_VC_EQC_CWATCH_DAT2 0x218 +#define VC_EQC_CWATCH_DAT2 0x940 +#define X_VC_EQC_CWATCH_DAT3 0x219 +#define VC_EQC_CWATCH_DAT3 0x948 +#define X_VC_IVC_SCRUB_TRIG 0x222 +#define VC_IVC_SCRUB_TRIG 0x990 +#define X_VC_IVC_SCRUB_MASK 0x223 +#define VC_IVC_SCRUB_MASK 0x998 +#define X_VC_SBC_SCRUB_TRIG 0x232 +#define VC_SBC_SCRUB_TRIG 0xa10 +#define X_VC_SBC_SCRUB_MASK 0x233 +#define VC_SBC_SCRUB_MASK 0xa18 +#define VC_SCRUB_VALID PPC_BIT(0) +#define VC_SCRUB_WANT_DISABLE PPC_BIT(1) +#define VC_SCRUB_WANT_INVAL PPC_BIT(2) /* EQC and SBC only */ +#define VC_SCRUB_BLOCK_ID PPC_BITMASK(28,31) +#define VC_SCRUB_OFFSET PPC_BITMASK(40,63) +#define X_VC_IVC_CACHE_ENABLE 0x221 +#define VC_IVC_CACHE_ENABLE 0x988 +#define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0,15) +#define X_VC_SBC_CACHE_ENABLE 0x231 +#define VC_SBC_CACHE_ENABLE 0xa08 +#define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0,15) +#define VC_IVC_CACHE_SCRUB_TRIG 0x990 +#define VC_IVC_CACHE_SCRUB_MASK 0x998 +#define VC_SBC_CACHE_ENABLE 0xa08 +#define VC_SBC_CACHE_SCRUB_TRIG 0xa10 +#define VC_SBC_CACHE_SCRUB_MASK 0xa18 +#define VC_SBC_CONFIG 0xa20 +#define X_VC_SBC_CONFIG 0x234 +#define VC_SBC_CONF_CPLX_CIST PPC_BIT(44) +#define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) +#define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) + +/* VC1 register offsets */ + +/* VSD Table address register definitions (shared) */ +#define VST_ADDR_AUTOINC PPC_BIT(0) +#define VST_TABLE_SELECT PPC_BITMASK(13,15) +#define VST_TSEL_IVT 0 +#define VST_TSEL_SBE 1 +#define VST_TSEL_EQDT 2 +#define VST_TSEL_VPDT 3 +#define VST_TSEL_IRQ 4 /* VC only */ +#define VST_TABLE_OFFSET PPC_BITMASK(27,31) + +/* Number of queue overflow pages */ +#define VC_QUEUE_OVF_COUNT 6 + +/* Bits in a VSD entry. + * + * Note: the address is naturally aligned, we don't use a PPC_BITMASK, + * but just a mask to apply to the address before OR'ing it in. + * + * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the + * VSD and is only meant to be used in indirect mode ! + */ +#define VSD_MODE PPC_BITMASK(0,1) +#define VSD_MODE_SHARED 1 +#define VSD_MODE_EXCLUSIVE 2 +#define VSD_MODE_FORWARD 3 +#define VSD_ADDRESS_MASK 0x0ffffffffffff000ull +#define VSD_MIGRATION_REG PPC_BITMASK(52,55) +#define VSD_INDIRECT PPC_BIT(56) +#define VSD_TSIZE PPC_BITMASK(59,63) +#define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */ + +/* + * Definition of the XIVE in-memory tables + */ + +/* IVE/EAS + * + * One per interrupt source. Targets that interrupt to a given EQ + * and provides the corresponding logical interrupt number (EQ data) + * + * We also map this structure to the escalation descriptor inside + * an EQ, though in that case the valid and masked bits are not used. + */ +struct xive_ive { + /* Use a single 64-bit definition to make it easier to + * perform atomic updates + */ + uint64_t w; +#define IVE_VALID PPC_BIT(0) +#define IVE_EQ_BLOCK PPC_BITMASK(4,7) /* Destination EQ block# */ +#define IVE_EQ_INDEX PPC_BITMASK(8,31) /* Destination EQ index */ +#define IVE_MASKED PPC_BIT(32) /* Masked */ +#define IVE_EQ_DATA PPC_BITMASK(33,63) /* Data written to the EQ */ +}; + +/* EQ */ +struct xive_eq { + uint32_t w0; +#define EQ_W0_VALID PPC_BIT32(0) /* "v" bit */ +#define EQ_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ +#define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ +#define EQ_W0_BACKLOG PPC_BIT32(3) /* "b" bit */ +#define EQ_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */ +#define EQ_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */ +#define EQ_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */ +#define EQ_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */ +#define EQ_W0_QSIZE PPC_BITMASK32(12,15) +#define EQ_W0_SW0 PPC_BIT32(16) +#define EQ_W0_FIRMWARE EQ_W0_SW0 /* Owned by FW */ +#define EQ_QSIZE_4K 0 +#define EQ_QSIZE_64K 4 +#define EQ_W0_HWDEP PPC_BITMASK32(24,31) + uint32_t w1; +#define EQ_W1_ESn PPC_BITMASK32(0,1) +#define EQ_W1_ESn_P PPC_BIT32(0) +#define EQ_W1_ESn_Q PPC_BIT32(1) +#define EQ_W1_ESe PPC_BITMASK32(2,3) +#define EQ_W1_ESe_P PPC_BIT32(2) +#define EQ_W1_ESe_Q PPC_BIT32(3) +#define EQ_W1_GENERATION PPC_BIT32(9) +#define EQ_W1_PAGE_OFF PPC_BITMASK32(10,31) + uint32_t w2; +#define EQ_W2_MIGRATION_REG PPC_BITMASK32(0,3) +#define EQ_W2_OP_DESC_HI PPC_BITMASK32(4,31) + uint32_t w3; +#define EQ_W3_OP_DESC_LO PPC_BITMASK32(0,31) + uint32_t w4; +#define EQ_W4_ESC_EQ_BLOCK PPC_BITMASK32(4,7) +#define EQ_W4_ESC_EQ_INDEX PPC_BITMASK32(8,31) + uint32_t w5; +#define EQ_W5_ESC_EQ_DATA PPC_BITMASK32(1,31) + uint32_t w6; +#define EQ_W6_FORMAT_BIT PPC_BIT32(8) +#define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) +#define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) + uint32_t w7; +#define EQ_W7_F0_IGNORE PPC_BIT32(0) +#define EQ_W7_F0_BLK_GROUPING PPC_BIT32(1) +#define EQ_W7_F0_PRIORITY PPC_BITMASK32(8,15) +#define EQ_W7_F1_WAKEZ PPC_BIT32(0) +#define EQ_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1,31) +}; + +/* VP */ +struct xive_vp { + uint32_t w0; +#define VP_W0_VALID PPC_BIT32(0) + uint32_t w1; + uint32_t w2; + uint32_t w3; + uint32_t w4; + uint32_t w5; + uint32_t w6; + uint32_t w7; + uint32_t w8; +#define VP_W8_GRP_VALID PPC_BIT32(0) + uint32_t w9; + uint32_t wa; + uint32_t wb; + uint32_t wc; + uint32_t wd; + uint32_t we; + uint32_t wf; +}; + +#endif /* XIVE_P9_REGS_H */ diff --git a/include/xive-regs.h b/include/xive-regs.h new file mode 100644 index 000000000000..2d7286619ef5 --- /dev/null +++ b/include/xive-regs.h @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: Apache-2.0 +/* + * XIVE: eXternal Interrupt Virtualization Engine. POWER9 interrupt + * controller + * + * Copyright (c) 2016-2019, IBM Corporation. + */ +#ifndef XIVE_REGS_H +#define XIVE_REGS_H + +/* + * TM registers are special, see below + */ + +/* TM register offsets */ +#define TM_QW0_USER 0x000 /* All rings */ +#define TM_QW1_OS 0x010 /* Ring 0..2 */ +#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ +#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ + +/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ +#define TM_NSR 0x0 /* + + - + */ +#define TM_CPPR 0x1 /* - + - + */ +#define TM_IPB 0x2 /* - + + + */ +#define TM_LSMFB 0x3 /* - + + + */ +#define TM_ACK_CNT 0x4 /* - + - - */ +#define TM_INC 0x5 /* - + - + */ +#define TM_AGE 0x6 /* - + - + */ +#define TM_PIPR 0x7 /* - + - + */ + +/* QW word 2 contains the valid bit at the top and other fields + * depending on the QW + */ +#define TM_WORD2 0x8 +#define TM_QW0W2_VU PPC_BIT32(0) +#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ? +#define TM_QW1W2_VO PPC_BIT32(0) +#define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31) +#define TM_QW2W2_VP PPC_BIT32(0) +#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31) +#define TM_QW3W2_VT PPC_BIT32(0) +#define TM_QW3W2_LP PPC_BIT32(6) +#define TM_QW3W2_LE PPC_BIT32(7) +#define TM_QW3W2_T PPC_BIT32(31) + +/* In addition to normal loads to "peek" and writes (only when invalid) + * using 4 and 8 bytes accesses, the above registers support these + * "special" byte operations: + * + * - Byte load from QW0[NSR] - User level NSR (EBB) + * - Byte store to QW0[NSR] - User level NSR (EBB) + * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access + * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 + * otherwise VT||0000000 + * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) + * + * Then we have all these "special" CI ops at these offset that trigger + * all sorts of side effects: + * + * We can OR'in these a cache line index from 0...3 (ie, 0, 0x80, 0x100, 0x180) + * to select a specific snooper. 0 is pretty busy so 0x80 or 0x100 is recommended + * XXX TODO. add that and find way to tell KVM about it. + */ +#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ +#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ +#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ +#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */ +#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ +#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */ +#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/ +#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ +#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */ +#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ +#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */ +#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ +/* XXX more... */ + +/* NSR fields for the various QW ack types */ +#define TM_QW0_NSR_EB PPC_BIT8(0) +#define TM_QW1_NSR_EO PPC_BIT8(0) +#define TM_QW3_NSR_HE PPC_BITMASK8(0,1) +#define TM_QW3_NSR_HE_NONE 0 +#define TM_QW3_NSR_HE_POOL 1 +#define TM_QW3_NSR_HE_PHYS 2 +#define TM_QW3_NSR_HE_LSI 3 +#define TM_QW3_NSR_I PPC_BIT8(2) +#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7) + +#endif /* XIVE_REGS_H__ */ diff --git a/include/xive.h b/include/xive.h index b88cdabea40b..e18fb9d783ae 100644 --- a/include/xive.h +++ b/include/xive.h @@ -1,464 +1,13 @@ // SPDX-License-Identifier: Apache-2.0 -/* Copyright 2016-2018 IBM Corp. */ - -#ifndef __XIVE_H__ -#define __XIVE_H__ - -/* IC register offsets */ -#define CQ_SWI_CMD_HIST 0x020 -#define CQ_SWI_CMD_POLL 0x028 -#define CQ_SWI_CMD_BCAST 0x030 -#define CQ_SWI_CMD_ASSIGN 0x038 -#define CQ_SWI_CMD_BLK_UPD 0x040 -#define CQ_SWI_RSP 0x048 -#define X_CQ_CFG_PB_GEN 0x0a -#define CQ_CFG_PB_GEN 0x050 -#define CQ_INT_ADDR_OPT PPC_BITMASK(14,15) -#define X_CQ_IC_BAR 0x10 -#define X_CQ_MSGSND 0x0b -#define CQ_MSGSND 0x058 -#define CQ_CNPM_SEL 0x078 -#define CQ_IC_BAR 0x080 -#define CQ_IC_BAR_VALID PPC_BIT(0) -#define CQ_IC_BAR_64K PPC_BIT(1) -#define X_CQ_TM1_BAR 0x12 -#define CQ_TM1_BAR 0x90 -#define X_CQ_TM2_BAR 0x014 -#define CQ_TM2_BAR 0x0a0 -#define CQ_TM_BAR_VALID PPC_BIT(0) -#define CQ_TM_BAR_64K PPC_BIT(1) -#define X_CQ_PC_BAR 0x16 -#define CQ_PC_BAR 0x0b0 -#define CQ_PC_BAR_VALID PPC_BIT(0) -#define X_CQ_PC_BARM 0x17 -#define CQ_PC_BARM 0x0b8 -#define CQ_PC_BARM_MASK PPC_BITMASK(26,38) -#define X_CQ_VC_BAR 0x18 -#define CQ_VC_BAR 0x0c0 -#define CQ_VC_BAR_VALID PPC_BIT(0) -#define X_CQ_VC_BARM 0x19 -#define CQ_VC_BARM 0x0c8 -#define CQ_VC_BARM_MASK PPC_BITMASK(21,37) -#define X_CQ_TAR 0x1e -#define CQ_TAR 0x0f0 -#define CQ_TAR_TBL_AUTOINC PPC_BIT(0) -#define CQ_TAR_TSEL_BLK PPC_BIT(12) -#define CQ_TAR_TSEL_MIG PPC_BIT(13) -#define CQ_TAR_TSEL_VDT PPC_BIT(14) -#define CQ_TAR_TSEL_EDT PPC_BIT(15) -#define X_CQ_TDR 0x1f -#define CQ_TDR 0x0f8 -#define X_CQ_PBI_CTL 0x20 -#define CQ_PBI_CTL 0x100 -#define CQ_PBI_PC_64K PPC_BIT(5) -#define CQ_PBI_VC_64K PPC_BIT(6) -#define CQ_PBI_LNX_TRIG PPC_BIT(7) -#define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) -#define CQ_PBO_CTL 0x108 -#define CQ_AIB_CTL 0x110 -#define X_CQ_RST_CTL 0x23 -#define CQ_RST_CTL 0x118 -#define X_CQ_FIRMASK 0x33 -#define CQ_FIRMASK 0x198 -#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) -#define CQ_FIR_VC_INFO_ERROR_0_1 PPC_BITMASK(62,63) -#define X_CQ_FIRMASK_AND 0x34 -#define CQ_FIRMASK_AND 0x1a0 -#define X_CQ_FIRMASK_OR 0x35 -#define CQ_FIRMASK_OR 0x1a8 - -/* PC LBS1 register offsets */ -#define X_PC_TCTXT_CFG 0x100 -#define PC_TCTXT_CFG 0x400 -#define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) -#define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) -#define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) -#define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) -#define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) -#define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) -#define PC_TCTXT_CHIPID PPC_BITMASK(12,15) -#define PC_TCTXT_INIT_AGE PPC_BITMASK(30,31) -#define X_PC_TCTXT_TRACK 0x101 -#define PC_TCTXT_TRACK 0x408 -#define PC_TCTXT_TRACK_EN PPC_BIT(0) -#define X_PC_TCTXT_INDIR0 0x104 -#define PC_TCTXT_INDIR0 0x420 -#define PC_TCTXT_INDIR_VALID PPC_BIT(0) -#define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9,15) -#define X_PC_TCTXT_INDIR1 0x105 -#define PC_TCTXT_INDIR1 0x428 -#define X_PC_TCTXT_INDIR2 0x106 -#define PC_TCTXT_INDIR2 0x430 -#define X_PC_TCTXT_INDIR3 0x107 -#define PC_TCTXT_INDIR3 0x438 -#define X_PC_THREAD_EN_REG0 0x108 -#define PC_THREAD_EN_REG0 0x440 -#define X_PC_THREAD_EN_REG0_SET 0x109 -#define PC_THREAD_EN_REG0_SET 0x448 -#define X_PC_THREAD_EN_REG0_CLR 0x10a -#define PC_THREAD_EN_REG0_CLR 0x450 -#define X_PC_THREAD_EN_REG1 0x10c -#define PC_THREAD_EN_REG1 0x460 -#define X_PC_THREAD_EN_REG1_SET 0x10d -#define PC_THREAD_EN_REG1_SET 0x468 -#define X_PC_THREAD_EN_REG1_CLR 0x10e -#define PC_THREAD_EN_REG1_CLR 0x470 -#define X_PC_GLOBAL_CONFIG 0x110 -#define PC_GLOBAL_CONFIG 0x480 -#define PC_GCONF_INDIRECT PPC_BIT(32) -#define PC_GCONF_CHIPID_OVR PPC_BIT(40) -#define PC_GCONF_CHIPID PPC_BITMASK(44,47) -#define X_PC_VSD_TABLE_ADDR 0x111 -#define PC_VSD_TABLE_ADDR 0x488 -#define X_PC_VSD_TABLE_DATA 0x112 -#define PC_VSD_TABLE_DATA 0x490 -#define X_PC_AT_KILL 0x116 -#define PC_AT_KILL 0x4b0 -#define PC_AT_KILL_VALID PPC_BIT(0) -#define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27,31) -#define PC_AT_KILL_OFFSET PPC_BITMASK(48,60) -#define X_PC_AT_KILL_MASK 0x117 -#define PC_AT_KILL_MASK 0x4b8 - -/* PC LBS2 register offsets */ -#define X_PC_VPC_CACHE_ENABLE 0x161 -#define PC_VPC_CACHE_ENABLE 0x708 -#define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0,31) -#define X_PC_VPC_SCRUB_TRIG 0x162 -#define PC_VPC_SCRUB_TRIG 0x710 -#define X_PC_VPC_SCRUB_MASK 0x163 -#define PC_VPC_SCRUB_MASK 0x718 -#define PC_SCRUB_VALID PPC_BIT(0) -#define PC_SCRUB_WANT_DISABLE PPC_BIT(1) -#define PC_SCRUB_WANT_INVAL PPC_BIT(2) -#define PC_SCRUB_BLOCK_ID PPC_BITMASK(27,31) -#define PC_SCRUB_OFFSET PPC_BITMASK(45,63) -#define X_PC_VPC_CWATCH_SPEC 0x167 -#define PC_VPC_CWATCH_SPEC 0x738 -#define PC_VPC_CWATCH_CONFLICT PPC_BIT(0) -#define PC_VPC_CWATCH_FULL PPC_BIT(8) -#define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27,31) -#define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45,63) -#define X_PC_VPC_CWATCH_DAT0 0x168 -#define PC_VPC_CWATCH_DAT0 0x740 -#define X_PC_VPC_CWATCH_DAT1 0x169 -#define PC_VPC_CWATCH_DAT1 0x748 -#define X_PC_VPC_CWATCH_DAT2 0x16a -#define PC_VPC_CWATCH_DAT2 0x750 -#define X_PC_VPC_CWATCH_DAT3 0x16b -#define PC_VPC_CWATCH_DAT3 0x758 -#define X_PC_VPC_CWATCH_DAT4 0x16c -#define PC_VPC_CWATCH_DAT4 0x760 -#define X_PC_VPC_CWATCH_DAT5 0x16d -#define PC_VPC_CWATCH_DAT5 0x768 -#define X_PC_VPC_CWATCH_DAT6 0x16e -#define PC_VPC_CWATCH_DAT6 0x770 -#define X_PC_VPC_CWATCH_DAT7 0x16f -#define PC_VPC_CWATCH_DAT7 0x778 - -/* VC0 register offsets */ -#define X_VC_GLOBAL_CONFIG 0x200 -#define VC_GLOBAL_CONFIG 0x800 -#define VC_GCONF_INDIRECT PPC_BIT(32) -#define X_VC_VSD_TABLE_ADDR 0x201 -#define VC_VSD_TABLE_ADDR 0x808 -#define X_VC_VSD_TABLE_DATA 0x202 -#define VC_VSD_TABLE_DATA 0x810 -#define VC_IVE_ISB_BLOCK_MODE 0x818 -#define VC_EQD_BLOCK_MODE 0x820 -#define VC_VPS_BLOCK_MODE 0x828 -#define X_VC_IRQ_CONFIG_IPI 0x208 -#define VC_IRQ_CONFIG_IPI 0x840 -#define VC_IRQ_CONFIG_MEMB_EN PPC_BIT(45) -#define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46,51) -#define VC_IRQ_CONFIG_HW 0x848 -#define VC_IRQ_CONFIG_CASCADE1 0x850 -#define VC_IRQ_CONFIG_CASCADE2 0x858 -#define VC_IRQ_CONFIG_REDIST 0x860 -#define VC_IRQ_CONFIG_IPI_CASC 0x868 -#define X_VC_AIB_TX_ORDER_TAG2 0x22d -#define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) -#define VC_AIB_TX_ORDER_TAG2 0x890 -#define X_VC_AT_MACRO_KILL 0x23e -#define VC_AT_MACRO_KILL 0x8b0 -#define X_VC_AT_MACRO_KILL_MASK 0x23f -#define VC_AT_MACRO_KILL_MASK 0x8b8 -#define VC_KILL_VALID PPC_BIT(0) -#define VC_KILL_TYPE PPC_BITMASK(14,15) -#define VC_KILL_IRQ 0 -#define VC_KILL_IVC 1 -#define VC_KILL_SBC 2 -#define VC_KILL_EQD 3 -#define VC_KILL_BLOCK_ID PPC_BITMASK(27,31) -#define VC_KILL_OFFSET PPC_BITMASK(48,60) -#define X_VC_EQC_CACHE_ENABLE 0x211 -#define VC_EQC_CACHE_ENABLE 0x908 -#define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0,15) -#define X_VC_EQC_SCRUB_TRIG 0x212 -#define VC_EQC_SCRUB_TRIG 0x910 -#define X_VC_EQC_SCRUB_MASK 0x213 -#define VC_EQC_SCRUB_MASK 0x918 -#define X_VC_EQC_CWATCH_SPEC 0x215 -#define VC_EQC_CONFIG 0x920 -#define X_VC_EQC_CONFIG 0x214 -#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) -#define VC_EQC_CONF_SYNC_HW PPC_BIT(33) -#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) -#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) -#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) -#define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) -#define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) -#define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) -#define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) -#define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) -#define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) -#define VC_EQC_CWATCH_SPEC 0x928 -#define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) -#define VC_EQC_CWATCH_FULL PPC_BIT(8) -#define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28,31) -#define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40,63) -#define X_VC_EQC_CWATCH_DAT0 0x216 -#define VC_EQC_CWATCH_DAT0 0x930 -#define X_VC_EQC_CWATCH_DAT1 0x217 -#define VC_EQC_CWATCH_DAT1 0x938 -#define X_VC_EQC_CWATCH_DAT2 0x218 -#define VC_EQC_CWATCH_DAT2 0x940 -#define X_VC_EQC_CWATCH_DAT3 0x219 -#define VC_EQC_CWATCH_DAT3 0x948 -#define X_VC_IVC_SCRUB_TRIG 0x222 -#define VC_IVC_SCRUB_TRIG 0x990 -#define X_VC_IVC_SCRUB_MASK 0x223 -#define VC_IVC_SCRUB_MASK 0x998 -#define X_VC_SBC_SCRUB_TRIG 0x232 -#define VC_SBC_SCRUB_TRIG 0xa10 -#define X_VC_SBC_SCRUB_MASK 0x233 -#define VC_SBC_SCRUB_MASK 0xa18 -#define VC_SCRUB_VALID PPC_BIT(0) -#define VC_SCRUB_WANT_DISABLE PPC_BIT(1) -#define VC_SCRUB_WANT_INVAL PPC_BIT(2) /* EQC and SBC only */ -#define VC_SCRUB_BLOCK_ID PPC_BITMASK(28,31) -#define VC_SCRUB_OFFSET PPC_BITMASK(40,63) -#define X_VC_IVC_CACHE_ENABLE 0x221 -#define VC_IVC_CACHE_ENABLE 0x988 -#define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0,15) -#define X_VC_SBC_CACHE_ENABLE 0x231 -#define VC_SBC_CACHE_ENABLE 0xa08 -#define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0,15) -#define VC_IVC_CACHE_SCRUB_TRIG 0x990 -#define VC_IVC_CACHE_SCRUB_MASK 0x998 -#define VC_SBC_CACHE_ENABLE 0xa08 -#define VC_SBC_CACHE_SCRUB_TRIG 0xa10 -#define VC_SBC_CACHE_SCRUB_MASK 0xa18 -#define VC_SBC_CONFIG 0xa20 -#define X_VC_SBC_CONFIG 0x234 -#define VC_SBC_CONF_CPLX_CIST PPC_BIT(44) -#define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) -#define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) - -/* VC1 register offsets */ - -/* VSD Table address register definitions (shared) */ -#define VST_ADDR_AUTOINC PPC_BIT(0) -#define VST_TABLE_SELECT PPC_BITMASK(13,15) -#define VST_TSEL_IVT 0 -#define VST_TSEL_SBE 1 -#define VST_TSEL_EQDT 2 -#define VST_TSEL_VPDT 3 -#define VST_TSEL_IRQ 4 /* VC only */ -#define VST_TABLE_OFFSET PPC_BITMASK(27,31) - -/* Number of queue overflow pages */ -#define VC_QUEUE_OVF_COUNT 6 - -/* Bits in a VSD entry. - * - * Note: the address is naturally aligned, we don't use a PPC_BITMASK, - * but just a mask to apply to the address before OR'ing it in. - * - * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the - * VSD and is only meant to be used in indirect mode ! - */ -#define VSD_MODE PPC_BITMASK(0,1) -#define VSD_MODE_SHARED 1 -#define VSD_MODE_EXCLUSIVE 2 -#define VSD_MODE_FORWARD 3 -#define VSD_ADDRESS_MASK 0x0ffffffffffff000ull -#define VSD_MIGRATION_REG PPC_BITMASK(52,55) -#define VSD_INDIRECT PPC_BIT(56) -#define VSD_TSIZE PPC_BITMASK(59,63) -#define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */ - -/* - * TM registers are special, see below - */ - -/* TM register offsets */ -#define TM_QW0_USER 0x000 /* All rings */ -#define TM_QW1_OS 0x010 /* Ring 0..2 */ -#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ -#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ - -/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ -#define TM_NSR 0x0 /* + + - + */ -#define TM_CPPR 0x1 /* - + - + */ -#define TM_IPB 0x2 /* - + + + */ -#define TM_LSMFB 0x3 /* - + + + */ -#define TM_ACK_CNT 0x4 /* - + - - */ -#define TM_INC 0x5 /* - + - + */ -#define TM_AGE 0x6 /* - + - + */ -#define TM_PIPR 0x7 /* - + - + */ - -/* QW word 2 contains the valid bit at the top and other fields - * depending on the QW - */ -#define TM_WORD2 0x8 -#define TM_QW0W2_VU PPC_BIT32(0) -#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ? -#define TM_QW1W2_VO PPC_BIT32(0) -#define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31) -#define TM_QW2W2_VP PPC_BIT32(0) -#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31) -#define TM_QW3W2_VT PPC_BIT32(0) -#define TM_QW3W2_LP PPC_BIT32(6) -#define TM_QW3W2_LE PPC_BIT32(7) -#define TM_QW3W2_T PPC_BIT32(31) - -/* In addition to normal loads to "peek" and writes (only when invalid) - * using 4 and 8 bytes accesses, the above registers support these - * "special" byte operations: - * - * - Byte load from QW0[NSR] - User level NSR (EBB) - * - Byte store to QW0[NSR] - User level NSR (EBB) - * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access - * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 - * otherwise VT||0000000 - * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) - * - * Then we have all these "special" CI ops at these offset that trigger - * all sorts of side effects: - * - * We can OR'in these a cache line index from 0...3 (ie, 0, 0x80, 0x100, 0x180) - * to select a specific snooper. 0 is pretty busy so 0x80 or 0x100 is recommended - * XXX TODO. add that and find way to tell KVM about it. - */ -#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ -#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ -#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ -#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */ -#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ -#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */ -#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/ -#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ -#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */ -#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ -#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */ -#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ -/* XXX more... */ - -/* NSR fields for the various QW ack types */ -#define TM_QW0_NSR_EB PPC_BIT8(0) -#define TM_QW1_NSR_EO PPC_BIT8(0) -#define TM_QW3_NSR_HE PPC_BITMASK8(0,1) -#define TM_QW3_NSR_HE_NONE 0 -#define TM_QW3_NSR_HE_POOL 1 -#define TM_QW3_NSR_HE_PHYS 2 -#define TM_QW3_NSR_HE_LSI 3 -#define TM_QW3_NSR_I PPC_BIT8(2) -#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7) - /* - * Definition of the XIVE in-memory tables - */ - -/* IVE/EAS - * - * One per interrupt source. Targets that interrupt to a given EQ - * and provides the corresponding logical interrupt number (EQ data) + * XIVE: eXternal Interrupt Virtualization Engine. POWER9 interrupt + * controller * - * We also map this structure to the escalation descriptor inside - * an EQ, though in that case the valid and masked bits are not used. + * Copyright (c) 2016-2019, IBM Corporation. */ -struct xive_ive { - /* Use a single 64-bit definition to make it easier to - * perform atomic updates - */ - uint64_t w; -#define IVE_VALID PPC_BIT(0) -#define IVE_EQ_BLOCK PPC_BITMASK(4,7) /* Destination EQ block# */ -#define IVE_EQ_INDEX PPC_BITMASK(8,31) /* Destination EQ index */ -#define IVE_MASKED PPC_BIT(32) /* Masked */ -#define IVE_EQ_DATA PPC_BITMASK(33,63) /* Data written to the EQ */ -}; - -/* EQ */ -struct xive_eq { - uint32_t w0; -#define EQ_W0_VALID PPC_BIT32(0) /* "v" bit */ -#define EQ_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ -#define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ -#define EQ_W0_BACKLOG PPC_BIT32(3) /* "b" bit */ -#define EQ_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */ -#define EQ_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */ -#define EQ_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */ -#define EQ_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */ -#define EQ_W0_QSIZE PPC_BITMASK32(12,15) -#define EQ_W0_SW0 PPC_BIT32(16) -#define EQ_W0_FIRMWARE EQ_W0_SW0 /* Owned by FW */ -#define EQ_QSIZE_4K 0 -#define EQ_QSIZE_64K 4 -#define EQ_W0_HWDEP PPC_BITMASK32(24,31) - uint32_t w1; -#define EQ_W1_ESn PPC_BITMASK32(0,1) -#define EQ_W1_ESn_P PPC_BIT32(0) -#define EQ_W1_ESn_Q PPC_BIT32(1) -#define EQ_W1_ESe PPC_BITMASK32(2,3) -#define EQ_W1_ESe_P PPC_BIT32(2) -#define EQ_W1_ESe_Q PPC_BIT32(3) -#define EQ_W1_GENERATION PPC_BIT32(9) -#define EQ_W1_PAGE_OFF PPC_BITMASK32(10,31) - uint32_t w2; -#define EQ_W2_MIGRATION_REG PPC_BITMASK32(0,3) -#define EQ_W2_OP_DESC_HI PPC_BITMASK32(4,31) - uint32_t w3; -#define EQ_W3_OP_DESC_LO PPC_BITMASK32(0,31) - uint32_t w4; -#define EQ_W4_ESC_EQ_BLOCK PPC_BITMASK32(4,7) -#define EQ_W4_ESC_EQ_INDEX PPC_BITMASK32(8,31) - uint32_t w5; -#define EQ_W5_ESC_EQ_DATA PPC_BITMASK32(1,31) - uint32_t w6; -#define EQ_W6_FORMAT_BIT PPC_BIT32(8) -#define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) -#define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) - uint32_t w7; -#define EQ_W7_F0_IGNORE PPC_BIT32(0) -#define EQ_W7_F0_BLK_GROUPING PPC_BIT32(1) -#define EQ_W7_F0_PRIORITY PPC_BITMASK32(8,15) -#define EQ_W7_F1_WAKEZ PPC_BIT32(0) -#define EQ_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1,31) -}; -/* VP */ -struct xive_vp { - uint32_t w0; -#define VP_W0_VALID PPC_BIT32(0) - uint32_t w1; - uint32_t w2; - uint32_t w3; - uint32_t w4; - uint32_t w5; - uint32_t w6; - uint32_t w7; - uint32_t w8; -#define VP_W8_GRP_VALID PPC_BIT32(0) - uint32_t w9; - uint32_t wa; - uint32_t wb; - uint32_t wc; - uint32_t wd; - uint32_t we; - uint32_t wf; -}; +#ifndef XIVE_H +#define XIVE_H /* Internal APIs to other modules */ @@ -514,4 +63,4 @@ void __xive_source_eoi(struct irq_source *is, uint32_t isn); void xive_source_mask(struct irq_source *is, uint32_t isn); -#endif /* __XIVE_H__ */ +#endif /* XIVE_H */ diff --git a/hw/xive.c b/hw/xive.c index 96a9bc647e78..ec71932cc169 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: Apache-2.0 /* - * XIVE - P9 interrupt controller + * XIVE: eXternal Interrupt Virtualization Engine. POWER9 interrupt + * controller * - * Copyright 2016-2019 IBM Corp. + * Copyright (c) 2016-2019, IBM Corporation. */ #include @@ -10,6 +11,7 @@ #include #include #include +#include #include #include #include From patchwork Tue Oct 1 06:59:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169749 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9W46Rg2z9sN1 for ; Tue, 1 Oct 2019 17:14:24 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9W45K90zDqXB for ; Tue, 1 Oct 2019 17:14:24 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.77.114; helo=8.mo7.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 451 seconds by postgrey-1.36 at bilbo; Tue, 01 Oct 2019 17:07:59 AEST Received: from 8.mo7.mail-out.ovh.net (8.mo7.mail-out.ovh.net [46.105.77.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Mg50nrzDqQZ for ; Tue, 1 Oct 2019 17:07:58 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.35.124]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 31F15135310 for ; Tue, 1 Oct 2019 09:00:20 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 69BCCA3AB744; Tue, 1 Oct 2019 07:00:17 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:47 +0200 Message-Id: <20191001070002.20271-3-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17979495613320039385 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 02/17] xive/p9: minor cleanup of the interface X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The XIVE driver exposes an API to the core OPAL layer and to other OPAL drivers. This is a minor cleanup preparing ground for future XIVE logic. Signed-off-by: Cédric Le Goater --- include/interrupts.h | 1 - include/skiboot.h | 1 - include/xive.h | 7 ++++--- core/fast-reboot.c | 2 +- hw/slw.c | 1 + hw/xive.c | 4 ++-- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/interrupts.h b/include/interrupts.h index d1ee5c4c112b..dfd48f2f2d59 100644 --- a/include/interrupts.h +++ b/include/interrupts.h @@ -184,7 +184,6 @@ extern uint32_t get_ics_phandle(void); struct cpu_thread; extern void reset_cpu_icp(void); -extern void reset_cpu_xive(void); extern void icp_send_eoi(uint32_t interrupt); extern void icp_prep_for_pm(void); extern void icp_kick_cpu(struct cpu_thread *cpu); diff --git a/include/skiboot.h b/include/skiboot.h index 96d25b83dac3..4258955484ae 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -298,7 +298,6 @@ enum wakeup_engine_states { extern enum wakeup_engine_states wakeup_engine_state; extern bool has_deep_states; extern void nx_p9_rng_late_init(void); -extern void xive_late_init(void); diff --git a/include/xive.h b/include/xive.h index e18fb9d783ae..224d65837f53 100644 --- a/include/xive.h +++ b/include/xive.h @@ -57,10 +57,11 @@ void xive_cpu_callin(struct cpu_thread *cpu); */ void *xive_get_trigger_port(uint32_t girq); -/* To be used by special EOI override in PSI */ +/* To be used by PSI to prevent asserted LSI to constantly re-fire */ struct irq_source; -void __xive_source_eoi(struct irq_source *is, uint32_t isn); - void xive_source_mask(struct irq_source *is, uint32_t isn); +void xive_cpu_reset(void); +void xive_late_init(void); + #endif /* XIVE_H */ diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 9631eb96d072..9611652d8c96 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -324,7 +324,7 @@ void __noreturn fast_reboot_entry(void) prlog(PR_DEBUG, "RESET: CPU 0x%04x reset in\n", this_cpu()->pir); if (proc_gen == proc_gen_p9) { - reset_cpu_xive(); + xive_cpu_reset(); } else if (proc_gen == proc_gen_p8) { /* We reset our ICP first ! Otherwise we might get stray * interrupts when unsplitting diff --git a/hw/slw.c b/hw/slw.c index ed8a5f9e6877..f1d0298b3fd1 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/hw/xive.c b/hw/xive.c index ec71932cc169..5369369b9895 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2637,7 +2637,7 @@ static int64_t xive_source_set_xive(struct irq_source *is, return __xive_set_irq_config(is, isn, server, prio, isn, true, true); } -void __xive_source_eoi(struct irq_source *is, uint32_t isn) +static void __xive_source_eoi(struct irq_source *is, uint32_t isn) { struct xive_src *s = container_of(is, struct xive_src, is); uint32_t idx = isn - s->esb_base; @@ -4819,7 +4819,7 @@ static void xive_reset_mask_source_cb(struct irq_source *is, } } -void reset_cpu_xive(void) +void xive_cpu_reset(void) { struct cpu_thread *c = this_cpu(); struct xive_cpu_state *xs = c->xstate; From patchwork Tue Oct 1 06:59:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169739 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9SH4cRwz9sN1 for ; Tue, 1 Oct 2019 17:11:59 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9SH2rLtzDqQw for ; Tue, 1 Oct 2019 17:11:59 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.74.219; helo=8.mo68.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 8.mo68.mail-out.ovh.net (8.mo68.mail-out.ovh.net [46.105.74.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9C23sF1zDqR0 for ; Tue, 1 Oct 2019 17:00:29 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.57.16]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id D018B145292 for ; Tue, 1 Oct 2019 09:00:24 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id D66EBA3AB772; Tue, 1 Oct 2019 07:00:20 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:48 +0200 Message-Id: <20191001070002.20271-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17980621514022030297 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 03/17] xive/p9: use MMIO access for VC_EQC_CONFIG X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There is no reason to issue loads on XSCOM when syncing the interrupt controller. All should be in place to use MMIOs. Signed-off-by: Cédric Le Goater --- hw/xive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index 5369369b9895..89e3e2def1be 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2530,7 +2530,7 @@ static int64_t xive_sync(struct xive *x) /* XXX Add timeout */ for (;;) { - r = xive_regrx(x, VC_EQC_CONFIG); + r = xive_regr(x, VC_EQC_CONFIG); if ((r & SYNC_MASK) == SYNC_MASK) break; cpu_relax(); From patchwork Tue Oct 1 06:59:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169740 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9SY53PWz9sN1 for ; Tue, 1 Oct 2019 17:12:13 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9SY2QKhzDqBt for ; Tue, 1 Oct 2019 17:12:13 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.73.133; helo=10.mo177.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 10.mo177.mail-out.ovh.net (10.mo177.mail-out.ovh.net [46.105.73.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9C6573tzDqQQ for ; Tue, 1 Oct 2019 17:00:33 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.57.14]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id A0C3B10C862 for ; Tue, 1 Oct 2019 09:00:28 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 5B7B8A3AB7C7; Tue, 1 Oct 2019 07:00:24 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:49 +0200 Message-Id: <20191001070002.20271-5-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17981747415224519641 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 04/17] xive/p9: remove code not using indirect mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" An indirect table is a one page array of XIVE VSDs pointing to subpages containing XIVE virtual structures: NVTs, ENDs, EASs or ESBs. The OPAL XIVE driver uses direct tables for the EAS and ESB tables. The number of interrupts being 1M, the tables are respectivelly 256K and 8M per chip. We want the EAS lookup to be fast so we keep this table direct. The NVT and END are bigger structures (64 and 32 bytes). If the table were direct, we would use 32M and 32M of OPAL memory per chip. They are indirect today and Linux allocates the pages on behalf of OPAL when a new indirect subpage is needed. We plan to increase the NVT space and END space in P10. Remove USE_INDIRECT ifdef and associated code not used anymore. Signed-off-by: Cédric Le Goater --- hw/xive.c | 123 ++++++------------------------------------------------ 1 file changed, 12 insertions(+), 111 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 89e3e2def1be..1c756b54acbc 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -23,9 +23,6 @@ /* Use Block group mode to move chip_id into block .... */ #define USE_BLOCK_GROUP_MODE -/* Indirect mode */ -#define USE_INDIRECT - /* Always notify from EQ to VP (no EOI on EQs). Will speed up * EOIs at the expense of potentially higher powerbus traffic. */ @@ -171,14 +168,9 @@ * * XXX Adjust that based on BAR value ? */ -#ifdef USE_INDIRECT #define MAX_EQ_COUNT (1 * 1024 * 1024) #define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ? #define IND_EQ_TABLE_SIZE ((MAX_EQ_COUNT / EQ_PER_PAGE) * 8) -#else -#define MAX_EQ_COUNT (4 * 1024 * 64) -#define EQT_SIZE (MAX_EQ_COUNT * 32) -#endif /* Number of priorities (and thus EQDs) we allocate for each VP */ #define NUM_INT_PRIORITIES 8 @@ -201,16 +193,10 @@ * * XXX Adjust that based on BAR value ? */ -#ifdef USE_INDIRECT #define MAX_VP_ORDER 19 /* 512k */ #define MAX_VP_COUNT (1ul << MAX_VP_ORDER) #define VP_PER_PAGE (0x10000 / 64) // Use sizeof ? #define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8) -#else -#define MAX_VP_ORDER 13 /* 8k */ -#define MAX_VP_COUNT (1ul << MAX_VP_ORDER) -#define VPT_SIZE (MAX_VP_COUNT * 64) -#endif #ifdef USE_BLOCK_GROUP_MODE @@ -407,37 +393,28 @@ struct xive { void *sbe_base; void *ivt_base; -#ifdef USE_INDIRECT /* Indirect END/EQ table. NULL entries are unallocated, count is * the numbre of pointers (ie, sub page placeholders). */ uint64_t *eq_ind_base; uint32_t eq_ind_count; -#else - void *eq_base; -#endif + /* EQ allocation bitmap. Each bit represent 8 EQs */ bitmap_t *eq_map; -#ifdef USE_INDIRECT /* Indirect NVT/VP table. NULL entries are unallocated, count is * the numbre of pointers (ie, sub page placeholders). */ uint64_t *vp_ind_base; uint32_t vp_ind_count; -#else - void *vp_base; -#endif #ifndef USE_BLOCK_GROUP_MODE /* VP allocation buddy when not using block group mode */ struct buddy *vp_buddy; #endif -#ifdef USE_INDIRECT /* Pool of donated pages for provisioning indirect EQ and VP pages */ struct list_head donated_pages; -#endif /* To ease a possible change to supporting more than one block of * interrupts per chip, we store here the "base" global number @@ -804,7 +781,6 @@ static struct xive_eq *xive_get_eq(struct xive *x, unsigned int idx) { struct xive_eq *p; -#ifdef USE_INDIRECT if (idx >= (x->eq_ind_count * EQ_PER_PAGE)) return NULL; p = (struct xive_eq *)(x->eq_ind_base[idx / EQ_PER_PAGE] & @@ -813,14 +789,6 @@ static struct xive_eq *xive_get_eq(struct xive *x, unsigned int idx) return NULL; return &p[idx % EQ_PER_PAGE]; -#else - if (idx >= MAX_EQ_COUNT) - return NULL; - if (!x->eq_base) - return NULL; - p = x->eq_base; - return p + idx; -#endif } static struct xive_ive *xive_get_ive(struct xive *x, unsigned int isn) @@ -874,7 +842,6 @@ static struct xive_vp *xive_get_vp(struct xive *x, unsigned int idx) { struct xive_vp *p; -#ifdef USE_INDIRECT assert(idx < (x->vp_ind_count * VP_PER_PAGE)); p = (struct xive_vp *)(x->vp_ind_base[idx / VP_PER_PAGE] & VSD_ADDRESS_MASK); @@ -882,11 +849,6 @@ static struct xive_vp *xive_get_vp(struct xive *x, unsigned int idx) return NULL; return &p[idx % VP_PER_PAGE]; -#else - assert(idx < MAX_VP_COUNT); - p = x->vp_base; - return p + idx; -#endif } static void xive_init_default_vp(struct xive_vp *vp, @@ -934,12 +896,10 @@ static uint32_t *xive_get_eq_buf(uint32_t eq_blk, uint32_t eq_idx) return (uint32_t *)addr; } -#ifdef USE_INDIRECT -static void *xive_get_donated_page(struct xive *x __unused) +static void *xive_get_donated_page(struct xive *x) { return (void *)list_pop_(&x->donated_pages, 0); } -#endif #define XIVE_ALLOC_IS_ERR(_idx) ((_idx) >= 0xfffffff0) @@ -947,9 +907,9 @@ static void *xive_get_donated_page(struct xive *x __unused) #define XIVE_ALLOC_NO_IND 0xfffffffe /* Indirect need provisioning */ #define XIVE_ALLOC_NO_MEM 0xfffffffd /* Local allocation failed */ -static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect __unused) +static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) { - uint32_t ind_idx __unused; + uint32_t ind_idx; int idx; xive_vdbg(x, "Allocating EQ set...\n"); @@ -968,7 +928,6 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect __unused) xive_vdbg(x, "Got EQs 0x%x..0x%x\n", idx, idx + 7); -#ifdef USE_INDIRECT /* Calculate the indirect page where the EQs reside */ ind_idx = idx / EQ_PER_PAGE; @@ -1004,7 +963,6 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect __unused) (((uint64_t)page) & VSD_ADDRESS_MASK); /* Any cache scrub needed ? */ } -#endif /* USE_INDIRECT */ return idx; } @@ -1022,7 +980,6 @@ static void xive_free_eq_set(struct xive *x, uint32_t eqs) bitmap_clr_bit(*x->eq_map, idx); } -#ifdef USE_INDIRECT static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t order) { uint32_t pbase, pend, i; @@ -1052,14 +1009,6 @@ static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t orde } return true; } -#else -static inline bool xive_provision_vp_ind(struct xive *x __unused, - uint32_t vp_idx __unused, - uint32_t order __unused) -{ - return true; -} -#endif /* USE_INDIRECT */ #ifdef USE_BLOCK_GROUP_MODE @@ -1562,7 +1511,6 @@ static bool xive_set_local_tables(struct xive *x) SETFIELD(VSD_TSIZE, 0ull, ilog2(SBE_SIZE) - 12))) return false; -#ifdef USE_INDIRECT /* Set EQDT as indirect mode with 64K subpages */ if (!xive_set_vsd(x, VST_TSEL_EQDT, x->block_id, base | (((uint64_t)x->eq_ind_base) & VSD_ADDRESS_MASK) | @@ -1574,19 +1522,6 @@ static bool xive_set_local_tables(struct xive *x) (((uint64_t)x->vp_ind_base) & VSD_ADDRESS_MASK) | VSD_INDIRECT | SETFIELD(VSD_TSIZE, 0ull, 4))) return false; -#else - /* Set EQDT as direct mode */ - if (!xive_set_vsd(x, VST_TSEL_EQDT, x->block_id, base | - (((uint64_t)x->eq_base) & VSD_ADDRESS_MASK) | - SETFIELD(VSD_TSIZE, 0ull, ilog2(EQT_SIZE) - 12))) - return false; - - /* Set VPDT as direct mode */ - if (!xive_set_vsd(x, VST_TSEL_VPDT, x->block_id, base | - (((uint64_t)x->vp_base) & VSD_ADDRESS_MASK) | - SETFIELD(VSD_TSIZE, 0ull, ilog2(VPT_SIZE) - 12))) - return false; -#endif /* Setup quue overflows */ for (i = 0; i < VC_QUEUE_OVF_COUNT; i++) { @@ -1696,7 +1631,7 @@ static void xive_dump_mmio(struct xive *x) static bool xive_config_init(struct xive *x) { - uint64_t val __unused; + uint64_t val; /* Configure PC and VC page sizes and disable Linux trigger mode */ xive_regwx(x, CQ_PBI_CTL, CQ_PBI_PC_64K | CQ_PBI_VC_64K | CQ_PBI_FORCE_TM_LOCAL); @@ -1705,18 +1640,14 @@ static bool xive_config_init(struct xive *x) /*** The rest can use MMIO ***/ -#ifdef USE_INDIRECT /* Enable indirect mode in VC config */ val = xive_regr(x, VC_GLOBAL_CONFIG); val |= VC_GCONF_INDIRECT; xive_regw(x, VC_GLOBAL_CONFIG, val); -#endif /* Enable indirect mode in PC config */ val = xive_regr(x, PC_GLOBAL_CONFIG); -#ifdef USE_INDIRECT val |= PC_GCONF_INDIRECT; -#endif val |= PC_GCONF_CHIPID_OVR; val = SETFIELD(PC_GCONF_CHIPID, val, x->block_id); xive_regw(x, PC_GLOBAL_CONFIG, val); @@ -1836,9 +1767,9 @@ static bool xive_setup_set_xlate(struct xive *x) static bool xive_prealloc_tables(struct xive *x) { - uint32_t i __unused, vp_init_count __unused, vp_init_base __unused; - uint32_t pbase __unused, pend __unused; - uint64_t al __unused; + uint32_t i, vp_init_count, vp_init_base; + uint32_t pbase, pend; + uint64_t al; /* ESB/SBE has 4 entries per byte */ x->sbe_base = local_alloc(x->chip_id, SBE_SIZE, SBE_SIZE); @@ -1862,7 +1793,6 @@ static bool xive_prealloc_tables(struct xive *x) memset(x->ivt_base, 0, IVT_SIZE); xive_dbg(x, "IVT at %p size 0x%x\n", x->ivt_base, IVT_SIZE); -#ifdef USE_INDIRECT /* Indirect EQ table. (XXX Align to 64K until I figure out the * HW requirements) */ @@ -1924,26 +1854,6 @@ static bool xive_prealloc_tables(struct xive *x) x->vp_ind_base[i] = vsd; } -#else /* USE_INDIRECT */ - - /* Allocate direct EQ and VP tables */ - x->eq_base = local_alloc(x->chip_id, EQT_SIZE, EQT_SIZE); - if (!x->eq_base) { - xive_err(x, "Failed to allocate EQ table\n"); - return false; - } - memset(x->eq_base, 0, EQT_SIZE); - x->vp_base = local_alloc(x->chip_id, VPT_SIZE, VPT_SIZE); - if (!x->vp_base) { - xive_err(x, "Failed to allocate VP table\n"); - return false; - } - /* We clear the entries (non-valid). They will be initialized - * when actually used - */ - memset(x->vp_base, 0, VPT_SIZE); -#endif /* USE_INDIRECT */ - /* Allocate the queue overflow pages */ x->q_ovf = local_alloc(x->chip_id, VC_QUEUE_OVF_COUNT * 0x10000, 0x10000); if (!x->q_ovf) { @@ -1953,7 +1863,6 @@ static bool xive_prealloc_tables(struct xive *x) return true; } -#ifdef USE_INDIRECT static void xive_add_provisioning_properties(void) { uint32_t chips[XIVE_MAX_CHIPS]; @@ -1972,9 +1881,6 @@ static void xive_add_provisioning_properties(void) dt_add_property(xive_dt_node, "ibm,xive-provision-chips", chips, 4 * count); } -#else -static inline void xive_add_provisioning_properties(void) { } -#endif static void xive_create_mmio_dt_node(struct xive *x) { @@ -2849,9 +2755,8 @@ static struct xive *init_one_xive(struct dt_node *np) xive_dbg(x, "Initializing block ID %d...\n", x->block_id); chip->xive = x; -#ifdef USE_INDIRECT list_head_init(&x->donated_pages); -#endif + /* Base interrupt numbers and allocator init */ /* XXX Consider allocating half as many ESBs than MMIO space * so that HW sources land outside of ESB space... @@ -4271,7 +4176,7 @@ static int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio, static int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr) { struct proc_chip *c = get_chip(chip_id); - struct list_node *n __unused; + struct list_node *n; if (xive_mode != XIVE_MODE_EXPL) return OPAL_WRONG_STATE; @@ -4281,12 +4186,12 @@ static int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr) return OPAL_PARAMETER; if (addr & 0xffff) return OPAL_PARAMETER; -#ifdef USE_INDIRECT + n = (struct list_node *)addr; lock(&c->xive->lock); list_add(&c->xive->donated_pages, n); unlock(&c->xive->lock); -#endif + return OPAL_SUCCESS; } @@ -4579,7 +4484,6 @@ static void xive_cleanup_cpu_tima(struct cpu_thread *c) xive_regw(x, PC_TCTXT_INDIR0, 0); } -#ifdef USE_INDIRECT static int64_t xive_vc_ind_cache_kill(struct xive *x, uint64_t type) { uint64_t val; @@ -4658,7 +4562,6 @@ static void xive_cleanup_eq_ind(struct xive *x) } xive_vc_ind_cache_kill(x, VC_KILL_EQD); } -#endif /* USE_INDIRECT */ static void xive_reset_one(struct xive *x) { @@ -4765,14 +4668,12 @@ static void xive_reset_one(struct xive *x) assert(buddy_reserve(x->vp_buddy, 0x800, 11)); #endif -#ifdef USE_INDIRECT /* Forget about remaining donated pages */ list_head_init(&x->donated_pages); /* And cleanup donated indirect VP and EQ pages */ xive_cleanup_vp_ind(x); xive_cleanup_eq_ind(x); -#endif /* The rest must not be called with the lock held */ unlock(&x->lock); From patchwork Tue Oct 1 06:59:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9XC0Q3mz9sP7 for ; Tue, 1 Oct 2019 17:15:23 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9XB4l6szDqSc for ; Tue, 1 Oct 2019 17:15:22 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.43.205; helo=6.mo1.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 6.mo1.mail-out.ovh.net (6.mo1.mail-out.ovh.net [46.105.43.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Pk35cpzDqRk for ; Tue, 1 Oct 2019 17:09:45 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.42.167]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 67BC1191D2B for ; Tue, 1 Oct 2019 09:00:31 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 75248A3AB824; Tue, 1 Oct 2019 07:00:28 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:50 +0200 Message-Id: <20191001070002.20271-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17982591838984309721 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 05/17] xive/p9: remove code not using block group mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" block group mode is now required, it can not be disabled. Signed-off-by: Cédric Le Goater --- hw/xive.c | 209 +----------------------------------------------------- 1 file changed, 1 insertion(+), 208 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 1c756b54acbc..9b2c2b831867 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -20,9 +20,6 @@ #include #include -/* Use Block group mode to move chip_id into block .... */ -#define USE_BLOCK_GROUP_MODE - /* Always notify from EQ to VP (no EOI on EQs). Will speed up * EOIs at the expense of potentially higher powerbus traffic. */ @@ -198,22 +195,12 @@ #define VP_PER_PAGE (0x10000 / 64) // Use sizeof ? #define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8) -#ifdef USE_BLOCK_GROUP_MODE - /* Initial number of VPs (XXX Make it a variable ?). Round things * up to a max of 32 cores per chip */ #define INITIAL_VP_BASE 0x80 #define INITIAL_VP_COUNT 0x80 -#else - -/* Initial number of VPs on block 0 only */ -#define INITIAL_BLK0_VP_BASE 0x800 -#define INITIAL_BLK0_VP_COUNT 0x800 - -#endif - /* The xive operation mode indicates the active "API" and corresponds * to the "mode" parameter of the opal_xive_reset() call */ @@ -408,11 +395,6 @@ struct xive { uint64_t *vp_ind_base; uint32_t vp_ind_count; -#ifndef USE_BLOCK_GROUP_MODE - /* VP allocation buddy when not using block group mode */ - struct buddy *vp_buddy; -#endif - /* Pool of donated pages for provisioning indirect EQ and VP pages */ struct list_head donated_pages; @@ -476,7 +458,6 @@ static struct dt_node *xive_dt_node; static uint32_t xive_block_to_chip[XIVE_MAX_CHIPS]; static uint32_t xive_block_count; -#ifdef USE_BLOCK_GROUP_MODE static uint32_t xive_chip_to_block(uint32_t chip_id) { struct proc_chip *c = get_chip(chip_id); @@ -485,7 +466,6 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) assert(c->xive); return c->xive->block_id; } -#endif /* Conversion between GIRQ and block/index. * @@ -515,15 +495,9 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) #define GIRQ_TO_CHIP(__isn) (VC_BLK_TO_CHIP(GIRQ_TO_BLK(__isn))) /* Routing of physical processors to VPs */ -#ifdef USE_BLOCK_GROUP_MODE #define PIR2VP_IDX(__pir) (0x80 | P9_PIR2LOCALCPU(__pir)) #define PIR2VP_BLK(__pir) (xive_chip_to_block(P9_PIR2GCID(__pir))) #define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(VC_BLK_TO_CHIP(__blk), (__idx) & 0x7f)) -#else -#define PIR2VP_IDX(__pir) (0x800 | (P9_PIR2GCID(__pir) << 7) | P9_PIR2LOCALCPU(__pir)) -#define PIR2VP_BLK(__pir) (0) -#define VP2PIR(__blk, __idx) (P9_PIRFROMLOCALCPU(((__idx) >> 7) & 0xf, (__idx) & 0x7f)) -#endif /* Decoding of OPAL API VP IDs. The VP IDs are encoded as follow * @@ -558,7 +532,6 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) * on the left of the index (the entire VP block is in a single * block ID) */ -#ifdef USE_BLOCK_GROUP_MODE /* VP allocation */ static uint32_t xive_chips_alloc_bits = 0; @@ -621,58 +594,6 @@ static uint32_t xive_encode_vp(uint32_t blk, uint32_t idx, uint32_t order) return vp; } -#else /* USE_BLOCK_GROUP_MODE */ - -/* VP# decoding/encoding */ -static bool xive_decode_vp(uint32_t vp, uint32_t *blk, uint32_t *idx, - uint8_t *order, bool *group) -{ - uint32_t o = (vp >> 24) & 0x1f; - uint32_t index = vp & 0x00ffffff; - uint32_t imask = (1 << o) - 1; - - /* Groups not supported yet */ - if ((vp >> 31) & 1) - return false; - if (group) - *group = false; - - /* PIR case */ - if (((vp >> 30) & 1) == 0) { - if (find_cpu_by_pir(index) == NULL) - return false; - if (blk) - *blk = PIR2VP_BLK(index); - if (idx) - *idx = PIR2VP_IDX(index); - return true; - } - - /* Ensure o > 0, we have *at least* 2 VPs per block */ - if (o == 0) - return false; - - /* Extract index */ - if (idx) - *idx = index & imask; - /* Extract block ID */ - if (blk) - *blk = index >> o; - - /* Return order as well if asked for */ - if (order) - *order = o; - - return true; -} - -static uint32_t xive_encode_vp(uint32_t blk, uint32_t idx, uint32_t order) -{ - return 0x40000000 | (order << 24) | (blk << order) | idx; -} - -#endif /* !USE_BLOCK_GROUP_MODE */ - #define xive_regw(__x, __r, __v) \ __xive_regw(__x, __r, X_##__r, __v, #__r) #define xive_regr(__x, __r) \ @@ -1010,8 +931,6 @@ static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t orde return true; } -#ifdef USE_BLOCK_GROUP_MODE - static void xive_init_vp_allocator(void) { /* Initialize chip alloc bits */ @@ -1096,90 +1015,6 @@ static void xive_free_vps(uint32_t vp) unlock(&xive_buddy_lock); } -#else /* USE_BLOCK_GROUP_MODE */ - -static void xive_init_vp_allocator(void) -{ - struct proc_chip *chip; - - for_each_chip(chip) { - struct xive *x = chip->xive; - if (!x) - continue; - /* Each chip has a MAX_VP_ORDER buddy */ - x->vp_buddy = buddy_create(MAX_VP_ORDER); - assert(x->vp_buddy); - - /* We reserve the whole range of VPs representing HW chips. - * - * These are 0x800..0xfff on block 0 only, so order 11 - * starting at 0x800. - */ - if (x->block_id == 0) - assert(buddy_reserve(x->vp_buddy, 0x800, 11)); - } -} - -static uint32_t xive_alloc_vps(uint32_t order) -{ - struct proc_chip *chip; - struct xive *x = NULL; - int vp = -1; - - /* Minimum order is 1 */ - if (order < 1) - order = 1; - - /* Try on every chip */ - for_each_chip(chip) { - x = chip->xive; - if (!x) - continue; - assert(x->vp_buddy); - lock(&x->lock); - vp = buddy_alloc(x->vp_buddy, order); - unlock(&x->lock); - if (vp >= 0) - break; - } - if (vp < 0) - return XIVE_ALLOC_NO_SPACE; - - /* We have VPs, make sure we have backing for the - * NVTs on that block - */ - if (!xive_provision_vp_ind(x, vp, order)) { - lock(&x->lock); - buddy_free(x->vp_buddy, vp, order); - unlock(&x->lock); - return XIVE_ALLOC_NO_IND; - } - - /* Encode the VP number */ - return xive_encode_vp(x->block_id, vp, order); -} - -static void xive_free_vps(uint32_t vp) -{ - uint32_t idx, blk; - uint8_t order; - struct xive *x; - - assert(xive_decode_vp(vp, &blk, &idx, &order, NULL)); - - /* Grab appropriate xive */ - x = xive_from_pc_blk(blk); - /* XXX Return error instead ? */ - assert(x); - - /* Free that in the buddy */ - lock(&x->lock); - buddy_free(x->vp_buddy, idx, order); - unlock(&x->lock); -} - -#endif /* ndef USE_BLOCK_GROUP_MODE */ - enum xive_cache_type { xive_cache_ivc, xive_cache_sbc, @@ -1211,17 +1046,8 @@ static void xive_scrub_workaround_vp(struct xive *x, uint32_t block, uint32_t id * Note: This means the workaround only works for block group * mode. */ -#ifdef USE_BLOCK_GROUP_MODE __xive_cache_watch(x, xive_cache_vpc, block, INITIAL_VP_BASE, 0, 0, NULL, true, false); -#else - /* WARNING: Some workarounds related to cache scrubs require us to - * have at least one firmware owned (permanent) indirect entry for - * each XIVE instance. This currently only happens in block group - * mode - */ -#warning Block group mode should not be disabled -#endif } static void xive_scrub_workaround_eq(struct xive *x, uint32_t block __unused, uint32_t idx) @@ -1654,9 +1480,7 @@ static bool xive_config_init(struct xive *x) xive_dbg(x, "PC_GLOBAL_CONFIG=%016llx\n", val); val = xive_regr(x, PC_TCTXT_CFG); -#ifdef USE_BLOCK_GROUP_MODE val |= PC_TCTXT_CFG_BLKGRP_EN | PC_TCTXT_CFG_HARD_CHIPID_BLK; -#endif val |= PC_TCTXT_CHIPID_OVERRIDE; val |= PC_TCTXT_CFG_TARGET_EN; val = SETFIELD(PC_TCTXT_CHIPID, val, x->block_id); @@ -1820,13 +1644,8 @@ static bool xive_prealloc_tables(struct xive *x) memset(x->vp_ind_base, 0, al); /* Populate/initialize VP/EQs indirect backing */ -#ifdef USE_BLOCK_GROUP_MODE vp_init_count = INITIAL_VP_COUNT; vp_init_base = INITIAL_VP_BASE; -#else - vp_init_count = x->block_id == 0 ? INITIAL_BLK0_VP_COUNT : 0; - vp_init_base = INITIAL_BLK0_VP_BASE; -#endif /* Allocate pages for some VPs in indirect mode */ pbase = vp_init_base / VP_PER_PAGE; @@ -1871,11 +1690,7 @@ static void xive_add_provisioning_properties(void) dt_add_property_cells(xive_dt_node, "ibm,xive-provision-page-size", 0x10000); -#ifdef USE_BLOCK_GROUP_MODE count = 1 << xive_chips_alloc_bits; -#else - count = xive_block_count; -#endif for (i = 0; i < count; i++) chips[i] = xive_block_to_chip[i]; dt_add_property(xive_dt_node, "ibm,xive-provision-chips", @@ -4640,16 +4455,10 @@ static void xive_reset_one(struct xive *x) struct xive_vp vp0 = {0}; /* Ignore the physical CPU VPs */ -#ifdef USE_BLOCK_GROUP_MODE if (i >= INITIAL_VP_BASE && i < (INITIAL_VP_BASE + INITIAL_VP_COUNT)) continue; -#else - if (x->block_id == 0 && - i >= INITIAL_BLK0_VP_BASE && - i < (INITIAL_BLK0_VP_BASE + INITIAL_BLK0_VP_BASE)) - continue; -#endif + /* Is the VP valid ? */ vp = xive_get_vp(x, i); if (!vp || !(vp->w0 & VP_W0_VALID)) @@ -4661,13 +4470,6 @@ static void xive_reset_one(struct xive *x) i, 0, 8, &vp0, false, true); } -#ifndef USE_BLOCK_GROUP_MODE - /* If block group mode isn't enabled, reset VP alloc buddy */ - buddy_reset(x->vp_buddy); - if (x->block_id == 0) - assert(buddy_reserve(x->vp_buddy, 0x800, 11)); -#endif - /* Forget about remaining donated pages */ list_head_init(&x->donated_pages); @@ -4754,7 +4556,6 @@ static int64_t __xive_reset(uint64_t version) xive_reset_one(chip->xive); } -#ifdef USE_BLOCK_GROUP_MODE /* Cleanup global VP allocator */ buddy_reset(xive_vp_buddy); @@ -4764,7 +4565,6 @@ static int64_t __xive_reset(uint64_t version) * reserve that range on each chip. */ assert(buddy_reserve(xive_vp_buddy, 0x80, 7)); -#endif /* USE_BLOCK_GROUP_MODE */ return OPAL_SUCCESS; } @@ -4800,19 +4600,12 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) return OPAL_PARAMETER; if (group) return OPAL_PARAMETER; -#ifdef USE_BLOCK_GROUP_MODE if (blk) return OPAL_PARAMETER; if (order < (xive_chips_alloc_bits + 1)) return OPAL_PARAMETER; if (idx & ((1 << (order - xive_chips_alloc_bits)) - 1)) return OPAL_PARAMETER; -#else - if (order < 1) - return OPAL_PARAMETER; - if (idx & ((1 << order) - 1)) - return OPAL_PARAMETER; -#endif count = 1 << order; for (i = 0; i < count; i++) { From patchwork Tue Oct 1 06:59:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169741 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9Ss4fdqz9sN1 for ; Tue, 1 Oct 2019 17:12:29 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9Ss3LPqzDqDX for ; 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Tue, 1 Oct 2019 07:00:31 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:51 +0200 Message-Id: <20191001070002.20271-7-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17983717740328291289 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 06/17] xive/p9: remove dead code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Cédric Le Goater --- hw/xive.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 9b2c2b831867..39b1199d0125 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2601,10 +2601,6 @@ static struct xive *init_one_xive(struct dt_node *np) xive_dbg(x, "Handling interrupts [%08x..%08x]\n", x->int_base, x->int_max - 1); - /* System dependant values that must be set before BARs */ - //xive_regwx(x, CQ_CFG_PB_GEN, xx); - //xive_regwx(x, CQ_MSGSND, xx); - /* Setup the BARs */ if (!xive_configure_bars(x)) goto fail; From patchwork Tue Oct 1 06:59:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9dX0TMVz9sPd for ; Tue, 1 Oct 2019 17:20:00 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9dW6RHgzDqHK for ; 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Tue, 1 Oct 2019 07:00:35 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:52 +0200 Message-Id: <20191001070002.20271-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17984843640282844121 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 07/17] xive/p9: obsolete OPAL_XIVE_IRQ_*_VIA_FW flags X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0 processors. Keep the flags in case of a similar issue in the next generation of the XIVE logic and keep it also for Linux which still has handlers in its XIVE layer. However, there is no need to keep the code in POWER9 XIVE driver. Signed-off-by: Cédric Le Goater --- include/opal-api.h | 4 ++-- hw/xive.c | 12 ------------ 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/include/opal-api.h b/include/opal-api.h index ad913bfa382d..e7156f36a756 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -1149,8 +1149,8 @@ enum { OPAL_XIVE_IRQ_STORE_EOI = 0x00000002, OPAL_XIVE_IRQ_LSI = 0x00000004, OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, - OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, - OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, + OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* DD1.0 workaround */ + OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, /* DD1.0 workaround */ }; /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */ diff --git a/hw/xive.c b/hw/xive.c index 39b1199d0125..4a2b0df7b042 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3629,18 +3629,6 @@ static int64_t opal_xive_get_irq_info(uint32_t girq, if (out_flags) *out_flags = xive_convert_irq_flags(s->flags); - /* - * If the orig source has a set_xive callback, then set - * OPAL_XIVE_IRQ_MASK_VIA_FW as masking/unmasking requires - * source specific workarounds. Same with EOI. - */ - if (out_flags && s->orig_ops) { - if (s->orig_ops->set_xive) - *out_flags |= OPAL_XIVE_IRQ_MASK_VIA_FW; - if (s->orig_ops->eoi) - *out_flags |= OPAL_XIVE_IRQ_EOI_VIA_FW; - } - idx = girq - s->esb_base; if (out_esb_shift) From patchwork Tue Oct 1 06:59:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169751 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9Wt21mgz9sN1 for ; Tue, 1 Oct 2019 17:15:06 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9Wt0zmXzDqTh for ; Tue, 1 Oct 2019 17:15:06 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.73.133; helo=10.mo177.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 10.mo177.mail-out.ovh.net (10.mo177.mail-out.ovh.net [46.105.73.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Nq6xfBzDq8F for ; Tue, 1 Oct 2019 17:08:58 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.54.172]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 3F49D10C862 for ; Tue, 1 Oct 2019 09:00:43 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id C8576A3AB8FB; Tue, 1 Oct 2019 07:00:39 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:53 +0200 Message-Id: <20191001070002.20271-9-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17985969540611345369 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 08/17] xive/p9: obsolete OPAL_XIVE_IRQ_SHIFT_BUG flags X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0 processors. HW395455 P9/PHB4: Wrong Interrupt ESB CI Load Opcode Location in 64K page mode Signed-off-by: Cédric Le Goater --- include/opal-api.h | 2 +- include/xive.h | 2 +- hw/phb4.c | 1 + hw/xive.c | 7 ------- 4 files changed, 3 insertions(+), 9 deletions(-) diff --git a/include/opal-api.h b/include/opal-api.h index e7156f36a756..dd74e662cd95 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -1148,7 +1148,7 @@ enum { OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001, OPAL_XIVE_IRQ_STORE_EOI = 0x00000002, OPAL_XIVE_IRQ_LSI = 0x00000004, - OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, + OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* DD1.0 workaround */ OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* DD1.0 workaround */ OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, /* DD1.0 workaround */ }; diff --git a/include/xive.h b/include/xive.h index 224d65837f53..5706d275ae47 100644 --- a/include/xive.h +++ b/include/xive.h @@ -41,7 +41,7 @@ uint32_t xive_get_notify_base(uint32_t girq); #define XIVE_SRC_EOI_PAGE1 0x02 /* EOI on the second page */ #define XIVE_SRC_STORE_EOI 0x04 /* EOI using stores supported */ #define XIVE_SRC_LSI 0x08 /* Interrupt is an LSI */ -#define XIVE_SRC_SHIFT_BUG 0x10 /* ESB update offset << 4 */ +#define XIVE_SRC_SHIFT_BUG 0x10 /* ESB update offset << 4 (PHB4 LSI DD1) */ struct irq_source_ops; void xive_register_hw_source(uint32_t base, uint32_t count, uint32_t shift, diff --git a/hw/phb4.c b/hw/phb4.c index 3c71427aef2f..f02e675f0a02 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5738,6 +5738,7 @@ static void phb4_create(struct dt_node *np) xive_register_hw_source(p->base_msi, p->num_irqs - 8, 16, p->int_mmio, irq_flags, NULL, NULL); + /* XIVE_SRC_SHIFT_BUG is a DD1 workaround */ xive_register_hw_source(p->base_lsi, 8, 16, p->int_mmio + ((p->num_irqs - 8) << 16), XIVE_SRC_LSI | XIVE_SRC_SHIFT_BUG, diff --git a/hw/xive.c b/hw/xive.c index 4a2b0df7b042..84c1c107f253 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2219,9 +2219,6 @@ static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked) else offset = 0xc00; /* PQ = 00 */ - if (s->flags & XIVE_SRC_SHIFT_BUG) - offset <<= 4; - in_be64(mmio_base + offset); } @@ -2404,8 +2401,6 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn) in_be64(mmio_base); else { offset = 0xc00; - if (s->flags & XIVE_SRC_SHIFT_BUG) - offset <<= 4; eoi_val = in_be64(mmio_base + offset); xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n", isn, eoi_val); @@ -3602,8 +3597,6 @@ static uint64_t xive_convert_irq_flags(uint64_t iflags) if (iflags & XIVE_SRC_LSI) oflags |= OPAL_XIVE_IRQ_LSI; - if (iflags & XIVE_SRC_SHIFT_BUG) - oflags |= OPAL_XIVE_IRQ_SHIFT_BUG; return oflags; } From patchwork Tue Oct 1 06:59:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169742 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9T76Bw5z9sN1 for ; Tue, 1 Oct 2019 17:12:43 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9T75DM6zDqRn for ; Tue, 1 Oct 2019 17:12:43 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=87.98.158.110; helo=7.mo1.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 7.mo1.mail-out.ovh.net (7.mo1.mail-out.ovh.net [87.98.158.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9CS2gYLzDqQZ for ; Tue, 1 Oct 2019 17:00:51 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.54.172]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id AEF191913BF for ; Tue, 1 Oct 2019 09:00:46 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 32EC7A3AB971; Tue, 1 Oct 2019 07:00:43 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:54 +0200 Message-Id: <20191001070002.20271-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17986813963836165081 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 09/17] xive/p9: fix EQ bitmap assignment when allocation fails X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Wehn allocating a EQ set for a VP, the EQ base index bit is marked as allocated even if allocation fails, due to a lack of available pages. Move bit assignment at the end of xive_alloc_eq_set(). Signed-off-by: Cédric Le Goater --- hw/xive.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 84c1c107f253..00c79b9c8f43 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -832,6 +832,7 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) { uint32_t ind_idx; int idx; + int eq_base_idx; xive_vdbg(x, "Allocating EQ set...\n"); @@ -843,14 +844,13 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) xive_dbg(x, "Allocation from EQ bitmap failed !\n"); return XIVE_ALLOC_NO_SPACE; } - bitmap_set_bit(*x->eq_map, idx); - idx <<= 3; + eq_base_idx = idx << 3; - xive_vdbg(x, "Got EQs 0x%x..0x%x\n", idx, idx + 7); + xive_vdbg(x, "Got EQs 0x%x..0x%x\n", eq_base_idx, eq_base_idx + 7); /* Calculate the indirect page where the EQs reside */ - ind_idx = idx / EQ_PER_PAGE; + ind_idx = eq_base_idx / EQ_PER_PAGE; /* Is there an indirect page ? If not, check if we can provision it */ if (!x->eq_ind_base[ind_idx]) { @@ -885,14 +885,15 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) /* Any cache scrub needed ? */ } - return idx; + bitmap_set_bit(*x->eq_map, idx); + return eq_base_idx; } static void xive_free_eq_set(struct xive *x, uint32_t eqs) { uint32_t idx; - xive_vdbg(x, "Freeing EQ set...\n"); + xive_vdbg(x, "Freeing EQ 0x%x..0x%x\n", eqs, eqs + 7); assert((eqs & 7) == 0); assert(x->eq_map); From patchwork Tue Oct 1 06:59:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169743 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9TS0wmyz9sN1 for ; Tue, 1 Oct 2019 17:13:00 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9TR5FqnzDqSf for ; Tue, 1 Oct 2019 17:12:59 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=178.33.251.80; helo=2.mo69.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 2.mo69.mail-out.ovh.net (2.mo69.mail-out.ovh.net [178.33.251.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9CY0NwCzDqPm for ; Tue, 1 Oct 2019 17:00:55 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.57.50]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 183216B256 for ; Tue, 1 Oct 2019 09:00:51 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id A2CE9A3AB9EF; Tue, 1 Oct 2019 07:00:46 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:55 +0200 Message-Id: <20191001070002.20271-11-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17987939864083663833 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 10/17] xive/p9: introduce definitions for priorities X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The priority number 7 is used in a couple of places but it has different meanings. It can be the maximum priority number or the escalation priority number. Signed-off-by: Cédric Le Goater --- hw/xive.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 00c79b9c8f43..bc895dd427b3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -172,9 +172,15 @@ /* Number of priorities (and thus EQDs) we allocate for each VP */ #define NUM_INT_PRIORITIES 8 +/* Max priority number */ +#define XIVE_MAX_PRIO 7 + /* Priority used for the one queue in XICS emulation */ #define XIVE_EMULATION_PRIO 7 +/* Priority used for gather/silent escalation (KVM) */ +#define XIVE_ESCALATION_PRIO 7 + /* Max number of VPs. We allocate an indirect table big enough so * that when fully populated we can have that many VPs. * @@ -847,7 +853,8 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) eq_base_idx = idx << 3; - xive_vdbg(x, "Got EQs 0x%x..0x%x\n", eq_base_idx, eq_base_idx + 7); + xive_vdbg(x, "Got EQs 0x%x..0x%x\n", eq_base_idx, + eq_base_idx + XIVE_MAX_PRIO); /* Calculate the indirect page where the EQs reside */ ind_idx = eq_base_idx / EQ_PER_PAGE; @@ -893,7 +900,7 @@ static void xive_free_eq_set(struct xive *x, uint32_t eqs) { uint32_t idx; - xive_vdbg(x, "Freeing EQ 0x%x..0x%x\n", eqs, eqs + 7); + xive_vdbg(x, "Freeing EQ 0x%x..0x%x\n", eqs, eqs + XIVE_MAX_PRIO); assert((eqs & 7) == 0); assert(x->eq_map); @@ -2064,7 +2071,7 @@ static inline bool xive_eq_for_target(uint32_t target, uint8_t prio, uint32_t vp_blk, vp_idx; uint32_t eq_blk, eq_idx; - if (prio > 7) + if (prio > XIVE_MAX_PRIO) return false; /* Get the VP block/index from the target word */ @@ -2141,7 +2148,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, xive_vdbg(x, "ISN %x masked !\n", isn); /* Put prio 7 in the EQ */ - prio = 7; + prio = XIVE_MAX_PRIO; } else { /* Unmasking */ new_ive = ive->w & ~IVE_MASKED; @@ -3724,7 +3731,7 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, * the escalation interrupt number here. */ if (eq->w0 & EQ_W0_UNCOND_ESCALATE) - esc_idx |= 7; + esc_idx |= XIVE_ESCALATION_PRIO; *out_escalate_irq = MAKE_ESCALATION_GIRQ(blk, esc_idx); } @@ -4024,7 +4031,8 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id, * look at EQ 7 instead. */ /* Grab EQ for prio 7 to check for silent escalation */ - if (!xive_eq_for_target(vp_id, 7, &eq_blk, &eq_idx)) + if (!xive_eq_for_target(vp_id, XIVE_ESCALATION_PRIO, + &eq_blk, &eq_idx)) return OPAL_PARAMETER; eq_x = xive_from_vc_blk(eq_blk); @@ -4070,7 +4078,7 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) return OPAL_PARAMETER; /* Grab prio 7 */ - eq_orig = xive_get_eq(x, idx + 7); + eq_orig = xive_get_eq(x, idx + XIVE_ESCALATION_PRIO); if (!eq_orig) return OPAL_PARAMETER; @@ -4125,7 +4133,7 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) eq.w4 = SETFIELD(EQ_W4_ESC_EQ_BLOCK, eq.w4, blk); eq.w4 = SETFIELD(EQ_W4_ESC_EQ_INDEX, - eq.w4, idx + 7); + eq.w4, idx + XIVE_ESCALATION_PRIO); } else if (eq.w0 & EQ_W0_UNCOND_ESCALATE) { /* Clear the "u" bit, disable escalations if it was set */ eq.w0 &= ~EQ_W0_UNCOND_ESCALATE; From patchwork Tue Oct 1 06:59:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9Tk6Rmkz9sN1 for ; Tue, 1 Oct 2019 17:13:14 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9Tk4ZbQzDqTh for ; Tue, 1 Oct 2019 17:13:14 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.75.26; helo=8.mo179.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 8.mo179.mail-out.ovh.net (8.mo179.mail-out.ovh.net [46.105.75.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Cc2LrrzDqRJ for ; Tue, 1 Oct 2019 17:00:59 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.109.146.82]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 96B63143683 for ; Tue, 1 Oct 2019 09:00:54 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 0E788A3ABA7A; Tue, 1 Oct 2019 07:00:51 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:56 +0200 Message-Id: <20191001070002.20271-12-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17989065764102835161 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 11/17] xive/p9: fix silent escalation EQ setup X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When setting the silent/gather escalation for a VP, all EQs [0-6] should point to the silent EQ 7. Fix the loop in routine xive_setup_silent_gather() to include EQ 6 which was missing. Signed-off-by: Cédric Le Goater --- hw/xive.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index bc895dd427b3..26ae10f9782b 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -4118,7 +4118,9 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) /* Mark/unmark all other prios with the new "u" bit and update * escalation */ - for (i = 0; i < 6; i++) { + for (i = 0; i < NUM_INT_PRIORITIES; i++) { + if (i == XIVE_ESCALATION_PRIO) + continue; eq_orig = xive_get_eq(x, idx + i); if (!eq_orig) continue; From patchwork Tue Oct 1 06:59:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169745 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9V04G2jz9sN1 for ; Tue, 1 Oct 2019 17:13:28 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9V028P4zDqTV for ; Tue, 1 Oct 2019 17:13:28 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.75.45; helo=9.mo178.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 9.mo178.mail-out.ovh.net (9.mo178.mail-out.ovh.net [46.105.75.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Cg6XY2zDqPQ for ; Tue, 1 Oct 2019 17:01:02 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.35.185]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 0C4B27AA12 for ; Tue, 1 Oct 2019 09:00:57 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 7CA8AA3ABB09; Tue, 1 Oct 2019 07:00:54 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:57 +0200 Message-Id: <20191001070002.20271-13-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17989910186711419865 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 12/17] xive/p9: cleanup all EQs when a VP block is freed. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" EQ 7 was missing from the cleanup loop. Signed-off-by: Cédric Le Goater --- hw/xive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index 26ae10f9782b..ff5a1bed847d 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -4635,7 +4635,7 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) /* Ensure EQs are disabled and cleaned up. Ideally the caller * should have done it but we double check it here */ - for (j = 0; j < 7; j++) { + for (j = 0; j < NUM_INT_PRIORITIES; j++) { struct xive *eq_x = xive_from_vc_blk(eq_blk); struct xive_eq eq, *orig_eq = xive_get_eq(eq_x, eq_idx + j); From patchwork Tue Oct 1 06:59:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169746 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9VD5q5fz9sN1 for ; Tue, 1 Oct 2019 17:13:40 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9VD40dNzDqVR for ; Tue, 1 Oct 2019 17:13:40 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.58.226; helo=3.mo2.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 3.mo2.mail-out.ovh.net (3.mo2.mail-out.ovh.net [46.105.58.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Cm0j8GzDqQx for ; Tue, 1 Oct 2019 17:01:07 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.42.119]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 9DE301AD33F for ; Tue, 1 Oct 2019 09:01:02 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id D6496A3ABB60; Tue, 1 Oct 2019 07:00:57 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:58 +0200 Message-Id: <20191001070002.20271-14-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17991317562075679705 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 13/17] xive/p9: remove ACK# setting in the NVT X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The pressure relief is disabled (PC_TCTXT_CFG_STORE_ACK) because we use the same field in the NVT W1 to stash the VP END base index. We do not need to disable manually the ACK# register in the NVT W5. Signed-off-by: Cédric Le Goater --- hw/xive.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index ff5a1bed847d..0156ae66e150 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -4728,7 +4728,6 @@ static int64_t opal_xive_alloc_vp_block(uint32_t alloc_order) */ memset(vp, 0, sizeof(*vp)); vp->w1 = (blk << 28) | eqs; - vp->w5 = 0xff000000; } return vp_base; fail: From patchwork Tue Oct 1 06:59:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169747 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9VV665Cz9sN1 for ; Tue, 1 Oct 2019 17:13:54 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9VV3Fk1zDqSJ for ; Tue, 1 Oct 2019 17:13:54 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=178.33.250.45; helo=2.mo179.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 2.mo179.mail-out.ovh.net (2.mo179.mail-out.ovh.net [178.33.250.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Cn5Vz5zDqQx for ; Tue, 1 Oct 2019 17:01:08 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.109.159.203]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id B9D001415C1 for ; Tue, 1 Oct 2019 09:01:05 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 538B1A3ABBA5; Tue, 1 Oct 2019 07:01:02 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 08:59:59 +0200 Message-Id: <20191001070002.20271-15-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17992161989664279513 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 14/17] xive/p9: introduce NVT_SHIFT X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This defines the size of our VP space which is constrained by the definition of the END structure in the XIVE architecture for POWER9: #define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) #define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) The NVT/VP id is returned to the hypervisor by the OPAL call opal_xive_get_vp_info() and later pushed in W2 of the OS CAM line when a vCPU is dispatched on an HW thread. Signed-off-by: Cédric Le Goater --- hw/xive.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 0156ae66e150..e944e858d128 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -196,7 +196,10 @@ * * XXX Adjust that based on BAR value ? */ -#define MAX_VP_ORDER 19 /* 512k */ + +#define NVT_SHIFT 19 /* in sync with EQ_W6_NVT_INDEX */ + +#define MAX_VP_ORDER NVT_SHIFT /* 512k */ #define MAX_VP_COUNT (1ul << MAX_VP_ORDER) #define VP_PER_PAGE (0x10000 / 64) // Use sizeof ? #define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8) @@ -4049,7 +4052,7 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id, } if (out_cam_value) - *out_cam_value = (blk << 19) | idx; + *out_cam_value = (blk << NVT_SHIFT) | idx; if (out_report_cl_pair) { *out_report_cl_pair = ((uint64_t)(vp->w6 & 0x0fffffff)) << 32; From patchwork Tue Oct 1 07:00:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169759 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46jB6x08n1z9sQq for ; Tue, 1 Oct 2019 17:42:01 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46jB6w5NsszDqRG for ; Tue, 1 Oct 2019 17:42:00 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.72.36; helo=2.mo4.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 2.mo4.mail-out.ovh.net (2.mo4.mail-out.ovh.net [46.105.72.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46jB5713trzDqQr for ; Tue, 1 Oct 2019 17:40:24 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.35.158]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id 66C5F204627 for ; Tue, 1 Oct 2019 09:01:09 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id B8D88A3ABBFD; Tue, 1 Oct 2019 07:01:05 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 09:00:00 +0200 Message-Id: <20191001070002.20271-16-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17993287887971650521 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 15/17] xive/p9: remove XIVE_INT_SAFETY_GAP X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" It was used by bringup code only. Using HW interrupt numbers in a high range was a way to check that HW interrupt numbers (OPAL) and logical interrupt numbers (Linux) were not getting mixed in the event queues. Signed-off-by: Cédric Le Goater --- hw/xive.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index e944e858d128..bbfe2ecdff84 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -36,7 +36,6 @@ #define XIVE_EXTRA_CHECK_INIT_CACHE #undef XIVE_CHECK_MISROUTED_IPI #define XIVE_CHECK_LOCKS -#define XIVE_INT_SAFETY_GAP 0x1000 #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG @@ -44,7 +43,6 @@ #undef XIVE_EXTRA_CHECK_INIT_CACHE #undef XIVE_CHECK_MISROUTED_IPI #undef XIVE_CHECK_LOCKS -#define XIVE_INT_SAFETY_GAP 0x10 #endif /* @@ -151,6 +149,12 @@ */ #define MAX_INT_ENTRIES (1 * 1024 * 1024) +/* + * First interrupt number, also the first logical interrupt number + * allocated by Linux + */ +#define XIVE_INT_FIRST 0x10 + /* Corresponding direct table sizes */ #define SBE_SIZE (MAX_INT_ENTRIES / 4) #define IVT_SIZE (MAX_INT_ENTRIES * 8) @@ -2590,8 +2594,8 @@ static struct xive *init_one_xive(struct dt_node *np) /* Make sure we never hand out "2" as it's reserved for XICS emulation * IPI returns. Generally start handing out at 0x10 */ - if (x->int_ipi_top < XIVE_INT_SAFETY_GAP) - x->int_ipi_top = XIVE_INT_SAFETY_GAP; + if (x->int_ipi_top < XIVE_INT_FIRST) + x->int_ipi_top = XIVE_INT_FIRST; /* Allocate a few bitmaps */ x->eq_map = zalloc(BITMAP_BYTES(MAX_EQ_COUNT >> 3)); @@ -3490,7 +3494,7 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) /* XXX Use "p" to select queue */ val = xive_read_eq(xs, just_poll); - if (val && val < XIVE_INT_SAFETY_GAP) + if (val && val < XIVE_INT_FIRST) xive_cpu_err(c, "Bogus interrupt 0x%x received !\n", val); /* Convert to magic IPI if needed */ From patchwork Tue Oct 1 07:00:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169750 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9WT01Xjz9sP7 for ; Tue, 1 Oct 2019 17:14:45 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9WS5tgwzDqWn for ; Tue, 1 Oct 2019 17:14:44 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.50.107; helo=6.mo69.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 453 seconds by postgrey-1.36 at bilbo; Tue, 01 Oct 2019 17:08:52 AEST Received: from 6.mo69.mail-out.ovh.net (6.mo69.mail-out.ovh.net [46.105.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9Nh4rrwzDqCT for ; Tue, 1 Oct 2019 17:08:50 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.42.202]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id DDB106B248 for ; Tue, 1 Oct 2019 09:01:13 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 23A8BA3ABC17; Tue, 1 Oct 2019 07:01:09 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 09:00:01 +0200 Message-Id: <20191001070002.20271-17-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17994413786707954649 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 16/17] xive/p9: use predefined bitmasks to manipulate EQ addresses X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Cédric Le Goater --- hw/xive.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index bbfe2ecdff84..aa692149c3ca 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3761,7 +3761,7 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, if (out_qpage) { if (eq->w0 & EQ_W0_ENQUEUE) *out_qpage = - (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3; + (((uint64_t)(eq->w2 & EQ_W2_OP_DESC_HI)) << 32) | eq->w3; else *out_qpage = 0; } @@ -3846,8 +3846,8 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, case 16: case 21: case 24: - eq.w3 = ((uint64_t)qpage) & 0xffffffff; - eq.w2 = (((uint64_t)qpage)) >> 32 & 0x0fffffff; + eq.w3 = ((uint64_t)qpage) & EQ_W3_OP_DESC_LO; + eq.w2 = (((uint64_t)qpage) >> 32) & EQ_W2_OP_DESC_HI; eq.w0 |= EQ_W0_ENQUEUE; eq.w0 = SETFIELD(EQ_W0_QSIZE, eq.w0, qsize - 12); break; From patchwork Tue Oct 1 07:00:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1169748 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46j9Vp0cPfz9sP7 for ; Tue, 1 Oct 2019 17:14:10 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46j9Vn6jGDzDqWk for ; Tue, 1 Oct 2019 17:14:09 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=46.105.58.91; helo=7.mo178.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from 7.mo178.mail-out.ovh.net (7.mo178.mail-out.ovh.net [46.105.58.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46j9D43yqfzDqRP for ; Tue, 1 Oct 2019 17:01:21 +1000 (AEST) Received: from player731.ha.ovh.net (unknown [10.108.42.88]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 2C3A37AA93 for ; Tue, 1 Oct 2019 09:01:17 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 96513A3ABC44; Tue, 1 Oct 2019 07:01:13 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 1 Oct 2019 09:00:02 +0200 Message-Id: <20191001070002.20271-18-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191001070002.20271-1-clg@kaod.org> References: <20191001070002.20271-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17995539688861699033 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrgeefgdduuddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH v3 17/17] xive/p9: introduce the ESB magic MMIO offsets X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The following offsets into the ESB MMIO allow to read or manipulate the PQ bits. They must be used with an 8-byte load instruction. They all return the previous state of the interrupt (atomically). Additionally, some ESB pages support doing an EOI via a store and some ESBs support doing a trigger via a separate trigger page. Signed-off-by: Cédric Le Goater --- include/xive-regs.h | 19 +++++++++++++++++++ hw/xive.c | 20 ++++++++++---------- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/include/xive-regs.h b/include/xive-regs.h index 2d7286619ef5..a6a6ce35a291 100644 --- a/include/xive-regs.h +++ b/include/xive-regs.h @@ -86,4 +86,23 @@ #define TM_QW3_NSR_I PPC_BIT8(2) #define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7) +/* + * "magic" Event State Buffer (ESB) MMIO offsets. + * + * The following offsets into the ESB MMIO allow to read or manipulate + * the PQ bits. They must be used with an 8-byte load instruction. + * They all return the previous state of the interrupt (atomically). + * + * Additionally, some ESB pages support doing an EOI via a store and + * some ESBs support doing a trigger via a separate trigger page. + */ +#define XIVE_ESB_STORE_TRIGGER 0x000 /* Store in range 0x000-0x3FF */ +#define XIVE_ESB_STORE_EOI 0x400 /* Store */ +#define XIVE_ESB_LOAD_EOI 0x000 /* Load */ +#define XIVE_ESB_GET 0x800 /* Load */ +#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ +#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ +#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ +#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ + #endif /* XIVE_REGS_H__ */ diff --git a/hw/xive.c b/hw/xive.c index aa692149c3ca..f1f9c6a056ee 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1077,7 +1077,7 @@ static void xive_scrub_workaround_eq(struct xive *x, uint32_t block __unused, ui /* Ensure the above has returned before we do anything else * the XIVE store queue is completely empty */ - load_wait(in_be64(mmio + 0x800)); + load_wait(in_be64(mmio + XIVE_ESB_GET)); } static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, @@ -2230,9 +2230,9 @@ static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked) if (s->flags & XIVE_SRC_EOI_PAGE1) mmio_base += 1ull << (s->esb_shift - 1); if (masked) - offset = 0xd00; /* PQ = 01 */ + offset = XIVE_ESB_SET_PQ_01; else - offset = 0xc00; /* PQ = 00 */ + offset = XIVE_ESB_SET_PQ_00; in_be64(mmio_base + offset); } @@ -2398,7 +2398,7 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn) /* If the XIVE supports the new "store EOI facility, use it */ if (s->flags & XIVE_SRC_STORE_EOI) - out_be64(mmio_base + 0x400, 0); + out_be64(mmio_base + XIVE_ESB_STORE_EOI, 0); else { uint64_t offset; @@ -2415,7 +2415,7 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn) if (s->flags & XIVE_SRC_LSI) in_be64(mmio_base); else { - offset = 0xc00; + offset = XIVE_ESB_SET_PQ_00; eoi_val = in_be64(mmio_base + offset); xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n", isn, eoi_val); @@ -2423,7 +2423,7 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn) return; /* Re-trigger always on page0 or page1 ? */ - out_be64(mmio_base, 0); + out_be64(mmio_base + XIVE_ESB_STORE_TRIGGER, 0); } } } @@ -2686,9 +2686,9 @@ static void xive_ipi_eoi(struct xive *x, uint32_t idx) * This allows us to then do a re-trigger if Q was set rather * than synthetizing an interrupt in software */ - eoi_val = in_8(mm + 0x10c00); + eoi_val = in_8(mm + 0x10000 + XIVE_ESB_SET_PQ_00); if (eoi_val & 1) { - out_8(mm, 0); + out_8(mm + XIVE_ESB_STORE_TRIGGER, 0); } } @@ -2698,7 +2698,7 @@ static void xive_ipi_trigger(struct xive *x, uint32_t idx) xive_vdbg(x, "Trigger IPI 0x%x\n", idx); - out_8(mm, 0); + out_8(mm + XIVE_ESB_STORE_TRIGGER, 0); } @@ -3258,7 +3258,7 @@ static int64_t opal_xive_eoi(uint32_t xirr) * Note: We aren't doing an actual EOI. Instead we are clearing * both P and Q and will re-check the queue if Q was set. */ - eoi_val = in_8(xs->eqmmio + 0xc00); + eoi_val = in_8(xs->eqmmio + XIVE_ESB_SET_PQ_00); xive_cpu_vdbg(c, " isn %08x, eoi_val=%02x\n", xirr, eoi_val); /* Q was set ? Check EQ again after doing a sync to ensure