From patchwork Thu Sep 5 10:50:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1158364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46PHYf5QWWz9s3Z for ; Thu, 5 Sep 2019 20:51:34 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gxRUHlRu"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46PHYf3mdgzDr2h for ; Thu, 5 Sep 2019 20:51:34 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gxRUHlRu"; dkim-atps=neutral Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46PHY044yPzDqsZ for ; Thu, 5 Sep 2019 20:50:58 +1000 (AEST) Received: by mail-pf1-x444.google.com with SMTP id b13so1483540pfo.8 for ; Thu, 05 Sep 2019 03:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=otsplvs4zWsgEGBe2AmxBqlylAuEDmXnC+iMkC7NsyU=; b=gxRUHlRuMQkZcnUPja1mjTIV4teAy/BTaykgje7jVwJa+VTwluLdiILbUbeywgoM7O iG73pO3sM4OasHmzdQMOBSavAazOh3vBUKVCdW2ZOuKwHw+TuWOBFLP4xHT97tzSl31D PYukBnIu0gk0+fq+XJNDXAn4lQIjjHQZBHR5xSc+TiqQGgs/St2AKLNaQ3qwqwIJt7MN t+ipsxumsmq4hBRkaH6mEW98nYxcOtTrN3Raa6EVjCPj+kCg+gV2WrvRg20o1dNsMDoI tF0reRb+0Opk2mjBpFl+6KRceTsYTcxc5QiFaFYYcMpkdotnBaMS7KvBgpDV1Am+WCPg g0/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=otsplvs4zWsgEGBe2AmxBqlylAuEDmXnC+iMkC7NsyU=; b=tXXNCT+W7eZwTjrEeLIfpusVkimXhzhTO9OJB9oX7VYN5hwMpSG5O7Ni8PeKItdyxC 1vFVXix0akrBOig2b+OupHG0VZI5ROD722XCU5PCyDrqMPtv0Z4Qf7rp5OPqe0Dm2aPm GOOvGl3pYF20r5zFYgyf9OFJrOCPamAPsIBQ6lNzmse5FHubsZRjzvEbiBaThxEvNAqO 2y1Z6or/lIPVUFg4Rm/RgBd0i5Ro+Zi7Cr3uuyov+AOtO551EKaFUdLkMbdpEpMqzpCw RLxS1u+lPiuLQNIOcBCRZ6EW+HTerieHfRjkidwqVtDml+bGH4ilKB/GLffijsK5oFDt LRmA== X-Gm-Message-State: APjAAAXHlO9JQfBJHaVe5fl89xhDHj0cGFn3GPTLUkbPdGP+5ELw1Sif P0wfJt5j9qJZuO83jlAdegbAJAdH X-Google-Smtp-Source: APXvYqw/9T3mZUDww64Wk5csbDl9TH/5sh4wkUlNG5oBJY4Q7N2rcVPdlasfu72YxXRhNppxxWXhVw== X-Received: by 2002:a63:20a:: with SMTP id 10mr2536439pgc.226.1567680654276; Thu, 05 Sep 2019 03:50:54 -0700 (PDT) Received: from wafer.ozlabs.ibm.com.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id 2sm4728985pfa.43.2019.09.05.03.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 03:50:53 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Sep 2019 20:50:39 +1000 Message-Id: <20190905105042.27526-1-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [Skiboot] [PATCH v3 1/4] hw/psi: Add chip ID to interrupt names X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Each chip has a separate PSI, but the interrupt names are the same for both. Add the chip ID to the interrupt name of each to help differentiate between the two. Before: $ ./count_irqs.py |grep psi:i2c 27: 13006 - XIVE-IRQ 2097147 Level opal-psi:i2c 507: 3447 - XIVE-IRQ 1048571 Level opal-psi:i2c After: $ ~/count_irqs.py |grep i2c 27: 4338 - XIVE-IRQ 2097147 Level opal-psi#8:i2c 507: 11668 - XIVE-IRQ 1048571 Level opal-psi#0:i2c Signed-off-by: Oliver O'Halloran Reviewed-by: Cédric Le Goater --- hw/psi.c | 56 +++++++++++++++++++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index a74c105ff0ec..a54b503ce463 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -486,19 +486,24 @@ static char *psi_p8_irq_name(struct irq_source *is, uint32_t isn) { struct psi *psi = is->data; uint32_t idx = isn - psi->interrupt; + char tmp[30]; static const char *names[P8_IRQ_PSI_IRQ_COUNT] = { - "psi:fsp", - "psi:occ", - "psi:fsi", - "psi:lpchc", - "psi:local_err", - "psi:external", + "fsp", + "occ", + "fsi", + "lpchc", + "local_err", + "external", }; if (idx >= P8_IRQ_PSI_IRQ_COUNT) return NULL; - return strdup(names[idx]); + + snprintf(tmp, sizeof(tmp), "psi#%x:%s", + psi->chip_id, names[idx]); + + return strdup(tmp); } static const struct irq_source_ops psi_p8_irq_ops = { @@ -587,27 +592,32 @@ static char *psi_p9_irq_name(struct irq_source *is, uint32_t isn) { struct psi *psi = is->data; uint32_t idx = isn - psi->interrupt; + char tmp[30]; static const char *names[P9_PSI_NUM_IRQS] = { - "psi:fsp", - "psi:occ", - "psi:fsi", - "psi:lpchc", - "psi:local_err", - "psi:global_err", - "psi:external", - "psi:lpc_serirq_mux0", /* Have a callback to get name ? */ - "psi:lpc_serirq_mux1", /* Have a callback to get name ? */ - "psi:lpc_serirq_mux2", /* Have a callback to get name ? */ - "psi:lpc_serirq_mux3", /* Have a callback to get name ? */ - "psi:i2c", - "psi:dio", - "psi:psu" + "fsp", + "occ", + "fsi", + "lpchc", + "local_err", + "global_err", + "external", + "lpc_serirq_mux0", /* Have a callback to get name ? */ + "lpc_serirq_mux1", /* Have a callback to get name ? */ + "lpc_serirq_mux2", /* Have a callback to get name ? */ + "lpc_serirq_mux3", /* Have a callback to get name ? */ + "i2c", + "dio", + "psu" }; - if (idx >= P9_PSI_NUM_IRQS) + if (idx >= ARRAY_SIZE(names)) return NULL; - return strdup(names[idx]); + + snprintf(tmp, sizeof(tmp), "psi#%x:%s", + psi->chip_id, names[idx]); + + return strdup(tmp); } static const struct irq_source_ops psi_p9_irq_ops = { From patchwork Thu Sep 5 10:50:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1158363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46PHYB1kNcz9s3Z for ; Thu, 5 Sep 2019 20:51:10 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Thu, 05 Sep 2019 03:50:56 -0700 (PDT) Received: from wafer.ozlabs.ibm.com.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id 2sm4728985pfa.43.2019.09.05.03.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 03:50:56 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Sep 2019 20:50:40 +1000 Message-Id: <20190905105042.27526-2-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190905105042.27526-1-oohall@gmail.com> References: <20190905105042.27526-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v3 2/4] hw/psi-p9: Make interrupt name array global X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The array of P9 PSI interrupt names is currently a static constant inside psi_p9_irq_name(). We'd like to use these names in another function so move it outside. Signed-off-by: Oliver O'Halloran Reviewed-by: Cédric Le Goater --- hw/psi.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index a54b503ce463..70cf120a8397 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -514,6 +514,23 @@ static const struct irq_source_ops psi_p8_irq_ops = { .name = psi_p8_irq_name, }; +static const char *psi_p9_irq_names[P9_PSI_NUM_IRQS] = { + "fsp", + "occ", + "fsi", + "lpchc", + "local_err", + "global_err", + "external", + "lpc_serirq_mux0", /* Have a callback to get name ? */ + "lpc_serirq_mux1", /* Have a callback to get name ? */ + "lpc_serirq_mux2", /* Have a callback to get name ? */ + "lpc_serirq_mux3", /* Have a callback to get name ? */ + "i2c", + "dio", + "psu" +}; + static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) { struct psi *psi = is->data; @@ -594,28 +611,11 @@ static char *psi_p9_irq_name(struct irq_source *is, uint32_t isn) uint32_t idx = isn - psi->interrupt; char tmp[30]; - static const char *names[P9_PSI_NUM_IRQS] = { - "fsp", - "occ", - "fsi", - "lpchc", - "local_err", - "global_err", - "external", - "lpc_serirq_mux0", /* Have a callback to get name ? */ - "lpc_serirq_mux1", /* Have a callback to get name ? */ - "lpc_serirq_mux2", /* Have a callback to get name ? */ - "lpc_serirq_mux3", /* Have a callback to get name ? */ - "i2c", - "dio", - "psu" - }; - - if (idx >= ARRAY_SIZE(names)) + if (idx >= ARRAY_SIZE(psi_p9_irq_names)) return NULL; snprintf(tmp, sizeof(tmp), "psi#%x:%s", - psi->chip_id, names[idx]); + psi->chip_id, psi_p9_irq_names[idx]); return strdup(tmp); } From patchwork Thu Sep 5 10:50:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1158365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46PHYz4Frbz9s7T for ; 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Thu, 05 Sep 2019 03:50:58 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Sep 2019 20:50:41 +1000 Message-Id: <20190905105042.27526-3-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190905105042.27526-1-oohall@gmail.com> References: <20190905105042.27526-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v3 3/4] hw/psi-p9: Mask OPAL-owned LSIs without handlers X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Some versions of Swift have the TPM interrupt line of the second chip pulled up instead of down. This causes the PSI's external (TPM) interrupt to constantly re-fire since it's an LSI and the interrupt signal is constantly active. There's nothing that can be done to clear the underlying interrupt condition so we to ensure that it's masked. The problem isn't really specific to the external interrupt and will occur for any of the PSI interrupts that don't have an actual handler (FSP, global error, and sometimes the external). When one of these is delivered to OPAL we should log that it happened and mask it to prevent re-firing. Reviewed-by: Cédric Le Goater Signed-off-by: Oliver O'Halloran --- v3: Folded xive_source_mask() helper into this patch. --- hw/psi.c | 35 +++++++++++++++++++++++++++++------ hw/xive.c | 7 +++++++ include/xive.h | 2 ++ 3 files changed, 38 insertions(+), 6 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index 70cf120a8397..d466f5a807e9 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -531,6 +531,30 @@ static const char *psi_p9_irq_names[P9_PSI_NUM_IRQS] = { "psu" }; +static void psi_p9_mask_unhandled_irq(struct irq_source *is, uint32_t isn) +{ + struct psi *psi = is->data; + int idx = isn - psi->interrupt; + const char *name; + + if (idx < ARRAY_SIZE(psi_p9_irq_names)) + name = psi_p9_irq_names[idx]; + else + name = "unknown!"; + + prerror("PSI[0x%03x]: Masking unhandled LSI %d (%s)\n", + psi->chip_id, idx, name); + + /* + * All the PSI interrupts are LSIs and will be constantly re-fired + * unless the underlying interrupt condition is cleared. If we don't + * have a handler for the interrupt then it needs to be masked to + * prevent the IRQ from locking up the thread which handles it. + */ + xive_source_mask(is, isn); + +} + static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) { struct psi *psi = is->data; @@ -543,21 +567,17 @@ static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) case P9_PSI_IRQ_OCC: occ_p9_interrupt(psi->chip_id); break; - case P9_PSI_IRQ_FSI: - printf("PSI: FSI irq received\n"); - break; case P9_PSI_IRQ_LPCHC: lpc_interrupt(psi->chip_id); break; case P9_PSI_IRQ_LOCAL_ERR: prd_psi_interrupt(psi->chip_id); break; - case P9_PSI_IRQ_GLOBAL_ERR: - printf("PSI: Global error irq received\n"); - break; case P9_PSI_IRQ_EXTERNAL: if (platform.external_irq) platform.external_irq(psi->chip_id); + else + psi_p9_mask_unhandled_irq(is, isn); break; case P9_PSI_IRQ_LPC_SIRQ0: case P9_PSI_IRQ_LPC_SIRQ1: @@ -575,6 +595,9 @@ static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) case P9_PSI_IRQ_PSU: p9_sbe_interrupt(psi->chip_id); break; + + default: + psi_p9_mask_unhandled_irq(is, isn); } } diff --git a/hw/xive.c b/hw/xive.c index 76b41a9ee95f..7f894f2b1bb3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2732,6 +2732,13 @@ static char *xive_source_name(struct irq_source *is, uint32_t isn) return s->orig_ops->name(is, isn); } +void xive_source_mask(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + xive_update_irq_mask(s, isn - s->esb_base, true); +} + static const struct irq_source_ops xive_irq_source_ops = { .get_xive = xive_source_get_xive, .set_xive = xive_source_set_xive, diff --git a/include/xive.h b/include/xive.h index 4100e7127784..b88cdabea40b 100644 --- a/include/xive.h +++ b/include/xive.h @@ -512,4 +512,6 @@ void *xive_get_trigger_port(uint32_t girq); struct irq_source; void __xive_source_eoi(struct irq_source *is, uint32_t isn); +void xive_source_mask(struct irq_source *is, uint32_t isn); + #endif /* __XIVE_H__ */ From patchwork Thu Sep 5 10:50:42 2019 Content-Type: text/plain; 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Thu, 05 Sep 2019 03:51:00 -0700 (PDT) Received: from wafer.ozlabs.ibm.com.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id 2sm4728985pfa.43.2019.09.05.03.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 03:51:00 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Sep 2019 20:50:42 +1000 Message-Id: <20190905105042.27526-4-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190905105042.27526-1-oohall@gmail.com> References: <20190905105042.27526-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v3 4/4] hw/psi: Remove explicit external IRQ policy X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Rather than having an explicit policy use the presence of a platform defined external interrupt handler to determine whether we should direct the interrupt to OPAL or not. This lets us remove a pile of comments about why the policy is necessary and the comments about why we need to un-set it on P8+ Signed-off-by: Oliver O'Halloran Reviewed-by: Cédric Le Goater --- v3: Replaced the policy check with this. We can't check what to set the policy to in astbmc_early_init() since that's run inside the platform's probe function. As a result the platform structure has not been populated yet and there's no way to determine what the policy should be. --- hw/psi.c | 14 ++++++-------- include/psi.h | 12 ------------ platforms/astbmc/common.c | 3 --- platforms/astbmc/garrison.c | 11 ----------- platforms/astbmc/p8dnu.c | 11 ----------- 5 files changed, 6 insertions(+), 45 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index d466f5a807e9..bc170bbcff13 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -29,7 +29,6 @@ static LIST_HEAD(psis); static u64 psi_link_timer; static u64 psi_link_timeout; static bool psi_link_poll_active; -static bool psi_ext_irq_policy = EXTERNAL_IRQ_POLICY_LINUX; static void psi_activate_phb(struct psi *psi); @@ -471,8 +470,8 @@ static uint64_t psi_p8_irq_attributes(struct irq_source *is, uint32_t isn) if (psi->no_lpc_irqs && idx == P8_IRQ_PSI_LPC) return IRQ_ATTR_TARGET_LINUX; - if (idx == P8_IRQ_PSI_EXTERNAL && - psi_ext_irq_policy == EXTERNAL_IRQ_POLICY_LINUX) + /* Only direct external interrupts to OPAL if we have a handler */ + if (idx == P8_IRQ_PSI_EXTERNAL && !platform.external_irq) return IRQ_ATTR_TARGET_LINUX; attr = IRQ_ATTR_TARGET_OPAL | IRQ_ATTR_TYPE_LSI; @@ -625,6 +624,10 @@ static uint64_t psi_p9_irq_attributes(struct irq_source *is __unused, if (is_lpc_serirq) return lpc_get_irq_policy(psi->chip_id, idx - P9_PSI_IRQ_LPC_SIRQ0); + /* Only direct external interrupts to OPAL if we have a handler */ + if (idx == P9_PSI_IRQ_EXTERNAL && !platform.external_irq) + return IRQ_ATTR_TARGET_LINUX | IRQ_ATTR_TYPE_LSI; + return IRQ_ATTR_TARGET_OPAL | IRQ_ATTR_TYPE_LSI; } @@ -649,11 +652,6 @@ static const struct irq_source_ops psi_p9_irq_ops = { .name = psi_p9_irq_name, }; -void psi_set_external_irq_policy(bool policy) -{ - psi_ext_irq_policy = policy; -} - static void psi_init_p8_interrupts(struct psi *psi) { uint32_t irq; diff --git a/include/psi.h b/include/psi.h index 9836e354a31b..ee1e0a7ae2ec 100644 --- a/include/psi.h +++ b/include/psi.h @@ -247,18 +247,6 @@ extern void psi_irq_reset(void); extern void psi_enable_fsp_interrupt(struct psi *psi); extern void psi_fsp_link_in_use(struct psi *psi); -/* - * Must be called by the platform probe() function as the policy - * is established before platform.init - * - * This defines whether the external interrupt should be passed to - * the OS or handled locally in skiboot. Return true for skiboot - * handling. Default if not called is Linux. - */ -#define EXTERNAL_IRQ_POLICY_LINUX false -#define EXTERNAL_IRQ_POLICY_SKIBOOT true -extern void psi_set_external_irq_policy(bool policy); - extern struct lock psi_lock; #endif /* __PSI_H */ diff --git a/platforms/astbmc/common.c b/platforms/astbmc/common.c index 85043f3b91e7..15ac231fbdae 100644 --- a/platforms/astbmc/common.c +++ b/platforms/astbmc/common.c @@ -465,9 +465,6 @@ void astbmc_early_init(void) /* Hostboot forgets to populate the PSI BAR */ astbmc_fixup_psi_bar(); - /* Send external interrupts to me */ - psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_SKIBOOT); - if (ast_sio_init()) { if (ast_io_init()) { astbmc_fixup_uart(); diff --git a/platforms/astbmc/garrison.c b/platforms/astbmc/garrison.c index 1b0f865c54e0..caf6113687be 100644 --- a/platforms/astbmc/garrison.c +++ b/platforms/astbmc/garrison.c @@ -258,17 +258,6 @@ static bool garrison_probe(void) /* Lot of common early inits here */ astbmc_early_init(); - /* - * Override external interrupt policy -> send to Linux - * - * On Naples, we get LPC interrupts via the built-in LPC - * controller demuxer, not an external CPLD. The external - * interrupt is for other uses, such as the TPM chip, we - * currently route it to Linux, but we might change that - * later if we decide we need it. - */ - psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_LINUX); - /* Fixups until HB get the NPU bindings */ dt_create_npu(); diff --git a/platforms/astbmc/p8dnu.c b/platforms/astbmc/p8dnu.c index a76fbd9dc7bb..e223d158bd97 100644 --- a/platforms/astbmc/p8dnu.c +++ b/platforms/astbmc/p8dnu.c @@ -307,17 +307,6 @@ static bool p8dnu_probe(void) /* Lot of common early inits here */ astbmc_early_init(); - /* - * Override external interrupt policy -> send to Linux - * - * On Naples, we get LPC interrupts via the built-in LPC - * controller demuxer, not an external CPLD. The external - * interrupt is for other uses, such as the TPM chip, we - * currently route it to Linux, but we might change that - * later if we decide we need it. - */ - psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_LINUX); - /* Fixups until HB get the NPU bindings */ dt_create_npu();