From patchwork Thu Nov 9 09:20:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836243 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXd2d6sRlz9t5c for ; Thu, 9 Nov 2017 20:21:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 93EC8C22055; Thu, 9 Nov 2017 09:21:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E29C3C21EEC; Thu, 9 Nov 2017 09:21:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 76F90C21C29; Thu, 9 Nov 2017 09:21:23 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:21:23 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:20:40 +0800 Message-Id: <1510219240-79081-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 10/18] net: gmac_rockchip: Add rk3328 gmac support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: The GMAC2IO in the RK3328 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3328-specific logic necessary to reuse this driver. [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.134 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.134 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted The GMAC2IO in the RK3328 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3328-specific logic necessary to reuse this driver. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 22e3941..f24c347 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -86,6 +87,39 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } +static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3328_grf_regs *grf; + int clk; + enum { + RK3328_GMAC_CLK_SEL_SHIFT = 11, + RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), + RK3328_GMAC_CLK_SEL_125M = 0 << 11, + RK3328_GMAC_CLK_SEL_25M = 3 << 11, + RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3328_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3328_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3328_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); + + return 0; +} + static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3368_grf *grf; @@ -199,6 +233,50 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_RMII_MODE_SHIFT = 9, + RK3328_RMII_MODE_MASK = BIT(9), + + RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, + RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), + + RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), + RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), + + RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), + RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), + }; + enum { + RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), + + RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3328_RMII_MODE_MASK | + RK3328_GMAC_PHY_INTF_SEL_MASK | + RK3328_RXCLK_DLY_ENA_GMAC_MASK | + RK3328_TXCLK_DLY_ENA_GMAC_MASK, + RK3328_GMAC_PHY_INTF_SEL_RGMII | + RK3328_RXCLK_DLY_ENA_GMAC_MASK | + RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); + + rk_clrsetreg(&grf->mac_con[0], + RK3328_CLK_RX_DL_CFG_GMAC_MASK | + RK3328_CLK_TX_DL_CFG_GMAC_MASK, + pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); +} + static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3368_grf *grf; @@ -347,6 +425,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = { .set_to_rgmii = rk3288_gmac_set_to_rgmii, }; +const struct rk_gmac_ops rk3328_gmac_ops = { + .fix_mac_speed = rk3328_gmac_fix_mac_speed, + .set_to_rgmii = rk3328_gmac_set_to_rgmii, +}; + const struct rk_gmac_ops rk3368_gmac_ops = { .fix_mac_speed = rk3368_gmac_fix_mac_speed, .set_to_rgmii = rk3368_gmac_set_to_rgmii, @@ -365,6 +448,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = { static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, + { .compatible = "rockchip,rk3328-gmac", + .data = (ulong)&rk3328_gmac_ops }, { .compatible = "rockchip,rk3368-gmac", .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", From patchwork Thu Nov 9 09:22:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836246 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXd5K55HDz9t5c for ; Thu, 9 Nov 2017 20:23:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5922CC220D5; Thu, 9 Nov 2017 09:23:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5DFB7C21FC9; Thu, 9 Nov 2017 09:23:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1FDBDC2201B; Thu, 9 Nov 2017 09:23:30 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:23:30 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:22:48 +0800 Message-Id: <1510219368-79203-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 12/18] rockchip: dts: rk3328: Add gmac2io support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Add basic dts configuration for rk3328 gmac2io. Signed-off-by: David Wu --- Changes in v2: - New patch [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.130 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.130 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted Add basic dts configuration for rk3328 gmac2io. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch arch/arm/dts/rk3328.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 0bab1e3..5de1059 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -456,6 +456,25 @@ status = "disabled"; }; + gmac2io: ethernet@ff540000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff540000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, + <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, + <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, + <&cru PCLK_MAC2IO>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC2IO_A>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; From patchwork Thu Nov 9 09:24:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836248 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXd8j6mc4z9t5Q for ; Thu, 9 Nov 2017 20:26:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A9E0DC220F4; Thu, 9 Nov 2017 09:26:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.2 required=5.0 tests=ALL_TRUSTED, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EF147C22113; Thu, 9 Nov 2017 09:26:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 19605C22098; Thu, 9 Nov 2017 09:25:49 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:25:49 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:24:58 +0800 Message-Id: <1510219498-79331-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 14/18] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Clean the iomux definitions at grf_rk322x.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. After that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu --- [...] Content analysis details: (6.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.133 listed in psbl.surriel.com] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.133 listed in bl.mailspike.net] 0.8 UPPERCASE_50_75 message body is 50-75% uppercase 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted Clean the iomux definitions at grf_rk322x.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. After that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 ------------------------ arch/arm/mach-rockchip/rk322x-board-spl.c | 20 +- arch/arm/mach-rockchip/rk322x-board.c | 16 + drivers/pinctrl/rockchip/pinctrl_rk322x.c | 453 +++++++++++++++++++++++ 4 files changed, 488 insertions(+), 456 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h index c0c0d84..52e5a0a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h @@ -88,461 +88,6 @@ struct rk322x_sgrf { unsigned int busdmac_con[4]; }; -/* GRF_GPIO0A_IOMUX */ -enum { - GPIO0A7_SHIFT = 14, - GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, - GPIO0A7_GPIO = 0, - GPIO0A7_I2C3_SDA, - GPIO0A7_HDMI_DDCSDA, - - GPIO0A6_SHIFT = 12, - GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, - GPIO0A6_GPIO = 0, - GPIO0A6_I2C3_SCL, - GPIO0A6_HDMI_DDCSCL, - - GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, - GPIO0A3_GPIO = 0, - GPIO0A3_I2C1_SDA, - GPIO0A3_SDIO_CMD, - - GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, - GPIO0A2_GPIO = 0, - GPIO0A2_I2C1_SCL, - - GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, - GPIO0A1_GPIO = 0, - GPIO0A1_I2C0_SDA, - - GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, - GPIO0A0_GPIO = 0, - GPIO0A0_I2C0_SCL, -}; - -/* GRF_GPIO0B_IOMUX */ -enum { - GPIO0B7_SHIFT = 14, - GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, - GPIO0B7_GPIO = 0, - GPIO0B7_HDMI_HDP, - - GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, - GPIO0B6_GPIO = 0, - GPIO0B6_I2S_SDI, - GPIO0B6_SPI_CSN0, - - GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, - GPIO0B5_GPIO = 0, - GPIO0B5_I2S_SDO, - GPIO0B5_SPI_RXD, - - GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, - GPIO0B3_GPIO = 0, - GPIO0B3_I2S1_LRCKRX, - GPIO0B3_SPI_TXD, - - GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, - GPIO0B1_GPIO = 0, - GPIO0B1_I2S_SCLK, - GPIO0B1_SPI_CLK, - - GPIO0B0_SHIFT = 0, - GPIO0B0_MASK = 3, - GPIO0B0_GPIO = 0, - GPIO0B0_I2S_MCLK, -}; - -/* GRF_GPIO0C_IOMUX */ -enum { - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_HDMI_CECSDA, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_UART0_RSTN, - GPIO0C1_CLK_OUT1, -}; - -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_SDIO_PWREN, - GPIO0D6_PWM11, - - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_PWM2, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_PWM1, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_PWM0, -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A7_SHIFT = 14, - GPIO1A7_MASK = 1, - GPIO1A7_GPIO = 0, - GPIO1A7_SDMMC_WRPRT, -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_SDMMC_CMD, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, - GPIO1B6_GPIO = 0, - GPIO1B6_SDMMC_PWREN, - - GPIO1B4_SHIFT = 8, - GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, - GPIO1B4_GPIO = 0, - GPIO1B4_SPI_CSN1, - GPIO1B4_PWM12, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, - GPIO1B3_GPIO = 0, - GPIO1B3_UART1_RSTN, - GPIO1B3_PWM13, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART1_SIN, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C7_SHIFT = 14, - GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, - GPIO1C7_GPIO = 0, - GPIO1C7_NAND_CS3, - GPIO1C7_EMMC_RSTNOUT, - - GPIO1C6_SHIFT = 12, - GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, - GPIO1C6_GPIO = 0, - GPIO1C6_NAND_CS2, - GPIO1C6_EMMC_CMD, - - - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_SDMMC_D3, - GPIO1C5_JTAG_TMS, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_SDMMC_D2, - GPIO1C4_JTAG_TCK, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_SDMMC_D1, - GPIO1C3_UART2_SIN, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , - GPIO1C2_GPIO = 0, - GPIO1C2_SDMMC_D0, - GPIO1C2_UART2_SOUT, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_SDMMC_DETN, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, - GPIO1C0_GPIO = 0, - GPIO1C0_SDMMC_CLKOUT, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_NAND_D7, - GPIO1D7_EMMC_D7, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_NAND_D6, - GPIO1D6_EMMC_D6, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_NAND_D5, - GPIO1D5_EMMC_D5, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_NAND_D4, - GPIO1D4_EMMC_D4, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_NAND_D3, - GPIO1D3_EMMC_D3, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_NAND_D2, - GPIO1D2_EMMC_D2, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_NAND_D1, - GPIO1D1_EMMC_D1, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, - GPIO1D0_GPIO = 0, - GPIO1D0_NAND_D0, - GPIO1D0_EMMC_D0, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_NAND_DQS, - GPIO2A7_EMMC_CLKOUT, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_NAND_WP, - GPIO2A5_EMMC_PWREN, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_NAND_RDY, - GPIO2A4_EMMC_CMD, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_NAND_RDN, - GPIO2A4_SPI1_CSN1, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_NAND_WRN, - GPIO2A4_SPI1_CSN0, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_NAND_CLE, - GPIO2A1_SPI1_TXD, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_NAND_ALE, - GPIO2A0_SPI1_RXD, -}; - -/* GRF_GPIO2B_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_GMAC_RXER, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_GMAC_CLK, - GPIO2B6_MAC_LINK, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_GMAC_TXEN, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_GMAC_MDIO, - - GPIO2B3_SHIFT = 6, - GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, - GPIO2B3_GPIO = 0, - GPIO2B3_GMAC_RXCLK, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_GMAC_CRS, - - GPIO2B1_SHIFT = 2, - GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, - GPIO2B1_GPIO = 0, - GPIO2B1_GMAC_TXCLK, - - - GPIO2B0_SHIFT = 0, - GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, - GPIO2B0_GPIO = 0, - GPIO2B0_GMAC_RXDV, - GPIO2B0_MAC_SPEED_IOUT, -}; - -/* GRF_GPIO2C_IOMUX */ -enum { - GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, - GPIO2C7_GPIO = 0, - GPIO2C7_GMAC_TXD3, - - GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, - GPIO2C6_GPIO = 0, - GPIO2C6_GMAC_TXD2, - - GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, - GPIO2C5_GPIO = 0, - GPIO2C5_I2C2_SCL, - GPIO2C5_GMAC_RXD2, - - GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, - GPIO2C4_GPIO = 0, - GPIO2C4_I2C2_SDA, - GPIO2C4_GMAC_RXD3, - - GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, - GPIO2C3_GPIO = 0, - GPIO2C3_GMAC_TXD0, - - GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, - GPIO2C2_GPIO = 0, - GPIO2C2_GMAC_TXD1, - - GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, - GPIO2C1_GPIO = 0, - GPIO2C1_GMAC_RXD0, - - GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, - GPIO2C0_GPIO = 0, - GPIO2C0_GMAC_RXD1, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_GMAC_MDC, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3, - GPIO2D0_GPIO = 0, - GPIO2D0_GMAC_COL, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_DRV_VBUS1, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_PWM10, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, - GPIO3C1_GPIO = 0, - GPIO3C1_DRV_VBUS, -}; - -/* GRF_GPIO3D_IOMUX */ -enum { - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, - GPIO3D2_GPIO = 0, - GPIO3D2_PWM3, -}; - -/* GRF_CON_IOMUX */ -enum { - CON_IOMUX_GMAC_SHIFT = 15, - CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT, - CON_IOMUX_UART1SEL_SHIFT = 11, - CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, - CON_IOMUX_UART2SEL_SHIFT = 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - CON_IOMUX_EMMCSEL_SHIFT = 7, - CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, - CON_IOMUX_PWM3SEL_SHIFT = 3, - CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, - CON_IOMUX_PWM2SEL_SHIFT = 2, - CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, - CON_IOMUX_PWM1SEL_SHIFT = 1, - CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, - CON_IOMUX_PWM0SEL_SHIFT = 0, - CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, -}; - /* GRF_MACPHY_CON0 */ enum { MACPHY_CFG_ENABLE_SHIFT = 0, diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 35f4f97..f7c6045 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -30,7 +30,25 @@ DECLARE_GLOBAL_DATA_PTR; void board_debug_uart_init(void) { -static struct rk322x_grf * const grf = (void *)GRF_BASE; + static struct rk322x_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, + }; + enum { + CON_IOMUX_UART2SEL_SHIFT= 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + }; + /* Enable early UART2 channel 1 on the RK322x */ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK | GPIO1B2_MASK, diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index d443114..4655662 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -58,6 +58,22 @@ int board_init(void) /* Enable early UART2 channel 1 on the RK322x */ #define GRF_BASE 0x11000000 struct rk322x_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, + }; + enum { + CON_IOMUX_UART2SEL_SHIFT= 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + }; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK | GPIO1B2_MASK, diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c index 576b037..28d9996 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -17,6 +17,459 @@ DECLARE_GLOBAL_DATA_PTR; +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + GPIO0A7_HDMI_DDCSDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + GPIO0A6_HDMI_DDCSCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + GPIO0A3_SDIO_CMD, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B7_SHIFT = 14, + GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, + GPIO0B7_GPIO = 0, + GPIO0B7_HDMI_HDP, + + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S1_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S_MCLK, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_HDMI_CECSDA, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_RSTN, + GPIO0C1_CLK_OUT1, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDIO_PWREN, + GPIO0D6_PWM11, + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 1, + GPIO1A7_GPIO = 0, + GPIO1A7_SDMMC_WRPRT, +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_SDMMC_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_SDMMC_PWREN, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_SPI_CSN1, + GPIO1B4_PWM12, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_UART1_RSTN, + GPIO1B3_PWM13, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_NAND_CS3, + GPIO1C7_EMMC_RSTNOUT, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_SDMMC_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_SDMMC_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_SDMMC_D1, + GPIO1C3_UART2_SIN, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_SDMMC_D0, + GPIO1C2_UART2_SOUT, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_SDMMC_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_SDMMC_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SPI1_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SPI1_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_SPI1_TXD, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI1_RXD, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_GMAC_CLK, + GPIO2B6_MAC_LINK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_GMAC_TXCLK, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_GMAC_RXDV, + GPIO2B0_MAC_SPEED_IOUT, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + GPIO2C4_GMAC_RXD3, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_GMAC_COL, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_DRV_VBUS1, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_PWM10, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_DRV_VBUS, +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_PWM3, +}; + +/* GRF_CON_IOMUX */ +enum { + CON_IOMUX_GMACSEL_SHIFT = 15, + CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT, + CON_IOMUX_GMACSEL_1 = 1, + CON_IOMUX_UART1SEL_SHIFT = 11, + CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, + CON_IOMUX_UART2SEL_SHIFT = 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + CON_IOMUX_EMMCSEL_SHIFT = 7, + CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, + CON_IOMUX_PWM3SEL_SHIFT = 3, + CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, + CON_IOMUX_PWM2SEL_SHIFT = 2, + CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, + CON_IOMUX_PWM1SEL_SHIFT = 1, + CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, + CON_IOMUX_PWM0SEL_SHIFT = 0, + CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, +}; + struct rk322x_pinctrl_priv { struct rk322x_grf *grf; }; From patchwork Thu Nov 9 09:28:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836252 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXdG92B06z9t5c for ; Thu, 9 Nov 2017 20:31:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E7DFAC221F8; Thu, 9 Nov 2017 09:30:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A579BC22159; Thu, 9 Nov 2017 09:30:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3B2F6C22193; Thu, 9 Nov 2017 09:29:07 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:29:07 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:28:19 +0800 Message-Id: <1510219699-79514-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 17/18] net: gmac_rockchip: Add support for the RK3228 GMAC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: The GMAC in the RK3228 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.133 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.133 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted The GMAC in the RK3228 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index f24c347..a573740 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,39 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); } +static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk322x_grf *grf; + int clk; + enum { + RK3228_GMAC_CLK_SEL_SHIFT = 8, + RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), + RK3228_GMAC_CLK_SEL_125M = 0 << 8, + RK3228_GMAC_CLK_SEL_25M = 3 << 8, + RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3228_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3228_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3228_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); + + return 0; +} + static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3288_grf *grf; @@ -213,6 +247,50 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) return 0; } +static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_RMII_MODE_SHIFT = 10, + RK3228_RMII_MODE_MASK = BIT(10), + + RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, + RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), + + RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), + RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), + + RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), + RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), + }; + enum { + RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), + + RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3228_RMII_MODE_MASK | + RK3228_GMAC_PHY_INTF_SEL_MASK | + RK3228_RXCLK_DLY_ENA_GMAC_MASK | + RK3228_TXCLK_DLY_ENA_GMAC_MASK, + RK3228_GMAC_PHY_INTF_SEL_RGMII | + RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); + + rk_clrsetreg(&grf->mac_con[0], + RK3228_CLK_RX_DL_CFG_GMAC_MASK | + RK3228_CLK_TX_DL_CFG_GMAC_MASK, + pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); +} + static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3288_grf *grf; @@ -420,6 +498,11 @@ const struct eth_ops gmac_rockchip_eth_ops = { .write_hwaddr = designware_eth_write_hwaddr, }; +const struct rk_gmac_ops rk3228_gmac_ops = { + .fix_mac_speed = rk3228_gmac_fix_mac_speed, + .set_to_rgmii = rk3228_gmac_set_to_rgmii, +}; + const struct rk_gmac_ops rk3288_gmac_ops = { .fix_mac_speed = rk3288_gmac_fix_mac_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii, @@ -446,6 +529,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = { }; static const struct udevice_id rockchip_gmac_ids[] = { + { .compatible = "rockchip,rk3228-gmac", + .data = (ulong)&rk3228_gmac_ops }, { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, { .compatible = "rockchip,rk3328-gmac", From patchwork Thu Nov 9 09:29:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836255 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXdLM2zmPz9t5c for ; Thu, 9 Nov 2017 20:35:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8E7DDC2212A; Thu, 9 Nov 2017 09:35:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DCF9BC2227C; Thu, 9 Nov 2017 09:33:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B616CC2229B; Thu, 9 Nov 2017 09:31:56 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:31:56 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:29:11 +0800 Message-Id: <1510219751-79573-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 18/18] config: evb-rk3229: Enable rk gmac configs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Add gmac config support for rk3229 evb. Signed-off-by: David Wu --- Changes in v2: - New patch [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.133 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.133 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted Add gmac config support for rk3229 evb. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch configs/evb-rk3229_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index b226f66..39469b4 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -31,6 +32,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y