From patchwork Fri Aug 9 17:14:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1144865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506604-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="WSElsDhE"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 464sMD0PNnz9sN4 for ; Sat, 10 Aug 2019 03:15:33 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=UzvgIUcACile J0Hqa1vU8onuu8nYjAaPYdpQUeFgB6P1jMdS5eypP+D3b+exMpuixWfA6+d3hiCT e38eHG8Tag9xC3Z8vDONe+5fzJrIxUQXbzUv/+QhB93RD2g6eCOp6Z+J2Zvvtn95 NNsWQULAtSWREx7qqpI35aHQramzAsY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=h+/3g8os9x1N5rccy3 tGq7nyqEQ=; b=WSElsDhEStyI1cH8KYKM05L7ahJkWM+FuHcNygQoPusidqi1TX XW1KNFYk08dZCu0cG2F5e3+Tk/Y4ByWqPucEhOCDsKZEbVzAYizAtU130tIMMwtt yvqtUGm4U2pXlNd4URqjiT88pqYV4xx5NpVPIEAdhkNCqJzdfCtx0UlfA= Received: (qmail 95282 invoked by alias); 9 Aug 2019 17:15:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 95105 invoked by uid 89); 9 Aug 2019 17:15:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=exploit X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Aug 2019 17:15:04 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id AB14A124078A; Fri, 9 Aug 2019 17:15:02 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool , Kewen Lin Subject: [PATCH] rs6000: vec-rotate-*.c fixes Date: Fri, 9 Aug 2019 17:14:55 +0000 Message-Id: <00c1a61a5fa9a374cd46708c17884621dc76ec7b.1565370392.git.segher@kernel.crashing.org> X-IsSubscribed: yes This fixes two minor problems with the new testcases. The first is that almost all other tests, including all vec* tests, for powerpc use names with dashes, not underscores. The more important one is the the vec-rotate-1.c and vec-rotate-3.c tests need the -maltivec flag. Committing to trunk. Segher 2019-08-09 Segher Boessenkool gcc/testsuite/ * gcc.target/powerpc/vec_rotate-1.c: Rename to ... * gcc.target/powerpc/vec-rotate-1.c: ... this. Add -maltivec option. * gcc.target/powerpc/vec_rotate-2.c: Rename to ... * gcc.target/powerpc/vec-rotate-2.c: ... this. * gcc.target/powerpc/vec_rotate-3.c: Rename to ... * gcc.target/powerpc/vec-rotate-3.c: ... this. Add -maltivec option. * gcc.target/powerpc/vec_rotate-4.c: Rename to ... * gcc.target/powerpc/vec-rotate-4.c: ... this. --- gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c | 39 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c | 18 +++++++++++ gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c | 40 +++++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c | 19 ++++++++++++ gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c | 39 ------------------------ gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c | 18 ----------- gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c | 40 ------------------------- gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c | 19 ------------ 8 files changed, 116 insertions(+), 116 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c new file mode 100644 index 0000000..6fe9627 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c @@ -0,0 +1,39 @@ +/* { dg-options "-O3 -maltivec" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count is const number. + + Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ + +#define N 256 +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> 9) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> 5) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5)); +} + +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c new file mode 100644 index 0000000..2359895 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c @@ -0,0 +1,18 @@ +/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ + +/* Check vectorizer can exploit vector rotation instructions on Power8, mainly + for the case rotation count is const number. + + Check for vrld which is available on Power8 and above. */ + +#define N 256 +unsigned long long sud[N], rud[N]; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c new file mode 100644 index 0000000..3730562 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c @@ -0,0 +1,40 @@ +/* { dg-options "-O3 -maltivec" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count isn't const number. + + Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ + +#define N 256 +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; +extern unsigned char rot_cnt; + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> rot_cnt) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> rot_cnt) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c new file mode 100644 index 0000000..75f08f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c @@ -0,0 +1,19 @@ +/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ + +/* Check vectorizer can exploit vector rotation instructions on Power8, mainly + for the case rotation count isn't const number. + + Check for vrld which is available on Power8 and above. */ + +#define N 256 +unsigned long long sud[N], rud[N]; +extern unsigned char rot_cnt; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c deleted file mode 100644 index f035a57..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c +++ /dev/null @@ -1,39 +0,0 @@ -/* { dg-options "-O3" } */ -/* { dg-require-effective-target powerpc_altivec_ok } */ - -/* Check vectorizer can exploit vector rotation instructions on Power, mainly - for the case rotation count is const number. - - Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ - -#define N 256 -unsigned int suw[N], ruw[N]; -unsigned short suh[N], ruh[N]; -unsigned char sub[N], rub[N]; - -void -testUW () -{ - for (int i = 0; i < 256; ++i) - ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8)); -} - -void -testUH () -{ - for (int i = 0; i < 256; ++i) - ruh[i] = (unsigned short) (suh[i] >> 9) - | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9)); -} - -void -testUB () -{ - for (int i = 0; i < 256; ++i) - rub[i] = (unsigned char) (sub[i] >> 5) - | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5)); -} - -/* { dg-final { scan-assembler {\mvrlw\M} } } */ -/* { dg-final { scan-assembler {\mvrlh\M} } } */ -/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c deleted file mode 100644 index 2359895..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c +++ /dev/null @@ -1,18 +0,0 @@ -/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ - -/* Check vectorizer can exploit vector rotation instructions on Power8, mainly - for the case rotation count is const number. - - Check for vrld which is available on Power8 and above. */ - -#define N 256 -unsigned long long sud[N], rud[N]; - -void -testULL () -{ - for (int i = 0; i < 256; ++i) - rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8)); -} - -/* { dg-final { scan-assembler {\mvrld\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c deleted file mode 100644 index 5e90ae6..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-options "-O3" } */ -/* { dg-require-effective-target powerpc_altivec_ok } */ - -/* Check vectorizer can exploit vector rotation instructions on Power, mainly - for the case rotation count isn't const number. - - Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ - -#define N 256 -unsigned int suw[N], ruw[N]; -unsigned short suh[N], ruh[N]; -unsigned char sub[N], rub[N]; -extern unsigned char rot_cnt; - -void -testUW () -{ - for (int i = 0; i < 256; ++i) - ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt)); -} - -void -testUH () -{ - for (int i = 0; i < 256; ++i) - ruh[i] = (unsigned short) (suh[i] >> rot_cnt) - | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt)); -} - -void -testUB () -{ - for (int i = 0; i < 256; ++i) - rub[i] = (unsigned char) (sub[i] >> rot_cnt) - | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt)); -} - -/* { dg-final { scan-assembler {\mvrlw\M} } } */ -/* { dg-final { scan-assembler {\mvrlh\M} } } */ -/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c deleted file mode 100644 index 75f08f0..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c +++ /dev/null @@ -1,19 +0,0 @@ -/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ - -/* Check vectorizer can exploit vector rotation instructions on Power8, mainly - for the case rotation count isn't const number. - - Check for vrld which is available on Power8 and above. */ - -#define N 256 -unsigned long long sud[N], rud[N]; -extern unsigned char rot_cnt; - -void -testULL () -{ - for (int i = 0; i < 256; ++i) - rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt)); -} - -/* { dg-final { scan-assembler {\mvrld\M} } } */