From patchwork Thu Aug 8 07:48:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143861 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="nyT8KUy2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640qX6gtXz9sN4 for ; Thu, 8 Aug 2019 17:48:40 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 602F7C21F2B; Thu, 8 Aug 2019 07:48:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C84EEC21E53; Thu, 8 Aug 2019 07:48:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 79EFAC21E1A; Thu, 8 Aug 2019 07:48:30 +0000 (UTC) Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) by lists.denx.de (Postfix) with ESMTPS id 96E66C21C29 for ; Thu, 8 Aug 2019 07:48:29 +0000 (UTC) Received-SPF: Pass (esa2.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa2.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa2.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa2.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa2.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: Vt2Zhxi86C07Xmk5VLw6CsyMOXZyJ+OClHYUhJD/EDOq+4FhOfDfVrGodKbGCFNG/vqt2tf56n n4E0+2nlOoZBGwg2khKTWp1FjrNYMnMpdDL3s10B+6/6kwdyOL9eQDsaoRTZtaB/HnUbKzF1A9 +HCtJ9dbDseBtF9fVWzjGIlS/JRjT+bqCESY5MFYH03XXFN48COod/gg9mQNLJreCpUnoDt6ZZ RmNjPKXilsNqyvWRLYiHSLRoVWb2eUB3zNr8yYEv/GjBdGtP4DUgvigUcLxK/G++ouBCOyxDwV 72o= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="44356086" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:25 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:25 -0700 Received: from NAM03-BY2-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:25 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aVi405AW7pZZZ4qzXYK//MCzFOnZcx4Z9NgQ4e2yT9qTAlpgvy9eKYOnCR77X1B9b+yj68G9ksJLnYI/dHpNpfH1rG6IQBClemoM6YCwulQF0lG4zIZha/IpsAdRD/X58aMR5nYTq+lJstTaI0ELe5M6gcE1UIfeMHWEbqGWy9B21UK+mFmK8A3vCGoKunAtxOcl015wSB2uql0qp52ebijhkH/rFVYuWv34uVYxQJChrtvibZ4sKTUSZ8H99VF3a298RSc3Lr9W3H1EBGsDBDYnZIvfSN2M8ToRFE/5z739dNSIUO6VgE3LJAq2UQNtcKh+tiVe//4yc+IACnMrQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R6Pdw8WebTbCvnJhh1JPqHHfpHzyz8ABwfghqlcw6LE=; b=i/wFT3I8K29gfEyAxMNAf11BP72H6/xCQm+jZi07hJJbOGenTujX0xb+oh+kmj56m6XT4c+Vvh8ROvYRXVMZdp/56ngVBySq95GB+y1Kdwv6T6vcoeHa3FJasYwxiRQAvC3WIX0Cwo27svhnNbvuPvMqVdP3AqUjDy81LWO2d5MP4TsxAU3nlQdj4rYkavinKs5+rFDA6nTnZ2QiM9SmHd5lRhaSh3bEV9CQAwwsn2GpFG8DM4Wq5PhELk5G4/WKvHCG24Y0BLvgG+KY84Wo6MZxOXSF0ooWVGf8wwpKyxUS5c9mh1o+8ZjhIlfSo9lTSaB1iAjtpIDdWELnQCzRZA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R6Pdw8WebTbCvnJhh1JPqHHfpHzyz8ABwfghqlcw6LE=; b=nyT8KUy2DG2JEpoomcFL7w+SIGbsgjmhhXAZLEw9vOQxUmLfU6UxiCrOR/+TXFSVkGW+coHmm0jqK0H6iCVh8FBOAyOQpR7/5PeF71SZvWOgSho6ybYyrsNAniRUykjdzbRvoHJCjkEeuLZ4HMoyKVBFGiJGonNXp98d+WzDuss= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB1609.namprd11.prod.outlook.com (10.172.36.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2157.15; Thu, 8 Aug 2019 07:48:24 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:24 +0000 From: To: , , Thread-Topic: [PATCH 1/7] ARM: at91: Add the chip ID for SAMA5D2 LPDDR2 SiP Thread-Index: AQHVTb2ndZbZy445bEqc2zkMiEqaoQ== Date: Thu, 8 Aug 2019 07:48:23 +0000 Message-ID: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f9348c09-101f-4a3a-300d-08d71bd4ca40 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:DM5PR11MB1609; x-ms-traffictypediagnostic: DM5PR11MB1609: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2399; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(136003)(396003)(366004)(376002)(346002)(189003)(199004)(66556008)(2501003)(186003)(2906002)(86362001)(50226002)(66066001)(110136005)(6436002)(8936002)(478600001)(14454004)(316002)(52116002)(99286004)(2616005)(26005)(102836004)(386003)(476003)(486006)(6506007)(7736002)(6486002)(66946007)(2201001)(64756008)(305945005)(66446008)(81156014)(3846002)(4326008)(66476007)(81166006)(6116002)(25786009)(8676002)(5660300002)(53936002)(71200400001)(6512007)(71190400001)(256004)(107886003)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB1609; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GazWexoxpFpjF2FUdu1YByVFniEVQGRyLNk8zdkOpzgqzCk1/vkFJhbgCpq5pdkDPSyRi8KUZWequWzuYLiL9vrvIahlqaXroWJgnespmogoyQy8h8oE4ttqgK38n+LWNAMwRIMlglWXQreCq61fpOVU/fk5ovi5lzV6funzWmjkVQIF8FhgLefnuOBlp+bjphpPf3Ysmriut+gqIOCtRIxHIEWplu3TbE/Wkhz1IRqXRE08caFUIReQt6nNZjfA7qDmfp6aHERzHC+6PzAcpY+jiV8ltbRuaP3h7nMHYBN8M1OVZHZOOmuyZFVfdaAq59cpr8wYBeWV5M6j01QSNrZgFWOinDyXAwJIkA2eG2+J4y0iisyU9e0tSm/HD42tZQ9vjDMgV0u1cBxAMK352WsJsEmok9zXblvAIDwj6xc= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f9348c09-101f-4a3a-300d-08d71bd4ca40 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:23.8494 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /v07+mP94vzbdUAaC8InR6+jSUNmQAkKzIjDcQOhPvjoRAywjDegs53ZMKLa6LaNG2DgHKH6Iwp1dtZ2CydvYPbpNxCKOsTV/dAytAfZbA8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1609 Cc: Nicolas.Ferre@microchip.com Subject: [U-Boot] [PATCH 1/7] ARM: at91: Add the chip ID for SAMA5D2 LPDDR2 SiP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nicolas Ferre The SAMA5D2 LPDDR2 SiP (System in Package) is added for SoC identification. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/armv7/sama5d2_devices.c | 8 ++++++++ arch/arm/mach-at91/include/mach/sama5d2.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index 59a0c44..9e9d026 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -57,8 +57,16 @@ char *get_cpu_name(void) return "SAMA5D27 512M bits DDR2 SDRAM"; case ARCH_EXID_SAMA5D27C_D1G: return "SAMA5D27 1G bits DDR2 SDRAM"; + case ARCH_EXID_SAMA5D27C_LD1G: + return "SAMA5D27 1G bits LPDDR2 SDRAM"; + case ARCH_EXID_SAMA5D27C_LD2G: + return "SAMA5D27 2G bits LPDDR2 SDRAM"; case ARCH_EXID_SAMA5D28C_D1G: return "SAMA5D28 1G bits DDR2 SDRAM"; + case ARCH_EXID_SAMA5D28C_LD1G: + return "SAMA5D28 1G bits LPDDR2 SDRAM"; + case ARCH_EXID_SAMA5D28C_LD2G: + return "SAMA5D28 2G bits LPDDR2 SDRAM"; } } diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index c7d9bb5..d1b2e01 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -220,7 +220,11 @@ #define ARCH_EXID_SAMA5D225C_D1M 0x00000053 #define ARCH_EXID_SAMA5D27C_D5M 0x00000032 #define ARCH_EXID_SAMA5D27C_D1G 0x00000033 +#define ARCH_EXID_SAMA5D27C_LD1G 0x00000061 +#define ARCH_EXID_SAMA5D27C_LD2G 0x00000062 #define ARCH_EXID_SAMA5D28C_D1G 0x00000013 +#define ARCH_EXID_SAMA5D28C_LD1G 0x00000071 +#define ARCH_EXID_SAMA5D28C_LD2G 0x00000072 /* Checked if defined in ethernet driver macb */ #define cpu_is_sama5d2 _cpu_is_sama5d2 From patchwork Thu Aug 8 07:48:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143866 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="q/c6jUBj"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640tP3Ll5z9sDB for ; Thu, 8 Aug 2019 17:51:09 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 156E7C21F2B; Thu, 8 Aug 2019 07:49:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B2763C21F32; Thu, 8 Aug 2019 07:48:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7536C21E53; Thu, 8 Aug 2019 07:48:36 +0000 (UTC) Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) by lists.denx.de (Postfix) with ESMTPS id E6263C21F0C for ; Thu, 8 Aug 2019 07:48:32 +0000 (UTC) Received-SPF: Pass (esa1.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa1.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa1.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa1.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa1.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: g/Rm75IEDmmyFnQ8PCbxG6spZcLYjgPi9pxKmrb8jKvuEOSe2JtDSmOYRoyLJ9W5yhyh8C/hut XLBqbBiCcnpI8jWjo/NqiC2jyT9V5UEwnilZpH2ew5vU5eACw/pWk9dj0OM/25UjjJyN2G1wr4 lRxwQ3/QGVBew+M4V1l/7rUSfzo69lgbaqTR03sRwa9jsOf4VWvJFaEJpRqTiusKcva72aIs5r d5Ft23OTpvgFRykVV14mkPJtxBFB6Y9Ujxx8/Ffi5srECLYWPiS1XoPa7GtIn7stoW58shHYXy 4Ec= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="45809492" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:28 -0700 Received: from NAM03-BY2-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:28 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hNfAK1BsFBGUVStQUPm3Q3Pv9E0K5f/smg0pTi2HlZ1L6tbSxlwr+UhOLq86Q5m+buyvBR/Zr26YQ7WU8RGlRic1pYIdsfTMwmMqp6cbURJMrfnLtcCcg3EJCcQKCIgEQ1sEml2pXyTcoH0w/KZ96hrhuaYalxQd0PlAg2SLZ2rsFApI0LJJ99oQd3dvpbBWHwcckjBq3yLgWTUPQAFTpWp4f7fdZMCQ4pEz4kaHDL/mS4x+CZgwpuh+8m8nEiS9EJaS9x0sMiNIn9RAaL5k8drwEwql94mOykOdTX5LEEwdMEr4tSgJcJnR26n+eUHex2nzMLuoz985pl5A8qkxaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=grWf6kPaYqebe026q5o6ncZLjYBRREQ12c53XrNB6Mk=; b=cjeTs4C/U7yHXWJ1sfDS2FPAGOILivMyUbLZ58HizsOwGsPN91FxNBbQpwB7fJ9V6ae5nPFHSFOJWWWtV0dgO24jHjXta7kMgiE6XKyMS5nq/XWr9pldnOWAuf7FUsSVeCHMolFgrLKHTzPsjVhLtT523U/V80TkwBUgn96PSyU5MP3FH6Ht28Iwh5hJ1jE1LHLeQSx3MGPs7j7kmIwfHmjSEs+SFgfEycFDWYnxTEV/avV2byY31JYPiN6psPZob5Wg2f8N0eV8ZvFLlOyRlD5qdxOuDdc+0nNKwFHfOqKrz1ugiXgH+nVRWwbhARtf+AnYNezZmylM6ijw8pyFXg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=grWf6kPaYqebe026q5o6ncZLjYBRREQ12c53XrNB6Mk=; b=q/c6jUBj4rS7o9AT/0eOaUitWKO6CEC5maxgsR1mBI+sJF3mpDA4U4q/B3xvVM7l+QgydJIn0nisB9CbORqwE5/kssN0kPXcWY97U5Eay+O0uQTRj7b2LvaVgtZrXAd/I8mMyzit+73VyFdi/QXKl2/qw2ftx94isL4RufbF7n8= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB1609.namprd11.prod.outlook.com (10.172.36.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2157.15; Thu, 8 Aug 2019 07:48:27 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:27 +0000 From: To: , , Thread-Topic: [PATCH 2/7] board: atmel: add sama5d27_wlsom1_ek board Thread-Index: AQHVTb2pDjbCWqt4QUu9x1SFElGhrA== Date: Thu, 8 Aug 2019 07:48:26 +0000 Message-ID: <1565250163-21502-2-git-send-email-eugen.hristev@microchip.com> References: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: af321ff2-9d16-4a42-18fd-08d71bd4cb42 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:DM5PR11MB1609; x-ms-traffictypediagnostic: DM5PR11MB1609: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(136003)(396003)(366004)(376002)(346002)(189003)(199004)(66556008)(2501003)(186003)(2906002)(86362001)(50226002)(66066001)(110136005)(6436002)(8936002)(478600001)(14454004)(30864003)(316002)(76176011)(52116002)(99286004)(2616005)(26005)(102836004)(386003)(11346002)(476003)(486006)(6506007)(7736002)(6486002)(66946007)(2201001)(446003)(64756008)(305945005)(66446008)(81156014)(3846002)(4326008)(66476007)(81166006)(6116002)(25786009)(8676002)(5660300002)(53936002)(71200400001)(6512007)(71190400001)(14444005)(256004)(107886003)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB1609; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: homQnnKehUv1r6jv1Igx8+FkwUaRvUJ13XByLkq48AknCROJ+Y9ZczlWMccq0W8dPm7nVFSrPet6AONDK7ap4khXWaDPNvZp0sDaOkUlwoTFVNQKF9E+9CSUZUcufMt8PzCO3KN3mqcWn6s8uB1/FkJwpYZNhZpWQt5mzJbN4lSXQtaFT4kxv2YL5XSs0ZPZLmdVtVz4tPtZVRemzgHTwXdOLY2pbfWzHe5NC8sh0NPkvoYeRgYevYq7jmmzjT7lrs2fwiWhWWmMYy0wworVUDxeohGW9k9WM7NXioBsbD/0U2DjBsg1Bxa4md9sBKno/1wJAGdWwnq4Bg9A2fOzfYXsU6MzPbQW+gxPmzhcibhAJeTwx41HQvFUoYm1ipaUgYtj3K+KVJMVgfJxVPw+6+3GpI9CcTCwXhoSYbGoEsE= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: af321ff2-9d16-4a42-18fd-08d71bd4cb42 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:26.9350 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7LiU/w51dQrnYQHglVX3aAZi2g1xZ+l0TwOtw8xmfVWIuDhlRFF0mAc4iAEfR/USGCPlnztae152ePe9ezRebj0SezqeJtNMpPkdb0je1JI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1609 Cc: Nicolas.Ferre@microchip.com Subject: [U-Boot] [PATCH 2/7] board: atmel: add sama5d27_wlsom1_ek board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nicolas Ferre Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP. Signed-off-by: Nicolas Ferre [eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10 Signed-off-by: Eugen Hristev --- arch/arm/dts/Makefile | 3 + arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi | 38 ++++++++++ arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 84 ++++++++++++++++++++++ arch/arm/dts/sama5d27_wlsom1.dtsi | 56 +++++++++++++++ arch/arm/mach-at91/Kconfig | 15 ++++ board/atmel/sama5d27_wlsom1_ek/Kconfig | 15 ++++ board/atmel/sama5d27_wlsom1_ek/MAINTAINERS | 7 ++ board/atmel/sama5d27_wlsom1_ek/Makefile | 7 ++ .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 80 +++++++++++++++++++++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 72 +++++++++++++++++++ include/configs/sama5d27_wlsom1_ek.h | 34 +++++++++ 11 files changed, 411 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi create mode 100644 arch/arm/dts/at91-sama5d27_wlsom1_ek.dts create mode 100644 arch/arm/dts/sama5d27_wlsom1.dtsi create mode 040000 board/atmel/sama5d27_wlsom1_ek create mode 100644 board/atmel/sama5d27_wlsom1_ek/Kconfig create mode 100644 board/atmel/sama5d27_wlsom1_ek/MAINTAINERS create mode 100644 board/atmel/sama5d27_wlsom1_ek/Makefile create mode 100644 board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c create mode 100644 configs/sama5d27_wlsom1_ek_mmc_defconfig create mode 100644 include/configs/sama5d27_wlsom1_ek.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b437f75..6ab2366 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -717,6 +717,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ at91-sama5d27_som1_ek.dtb +dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \ + at91-sama5d27_wlsom1_ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \ at91-sama5d2_icp.dtb diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi new file mode 100644 index 0000000..48ab217 --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_wlsom1_ek-u-boot.dts - Device Tree file for SAMA5D27 WLSOM1 EK + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + }; +}; + +&sdmmc0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&sfr { + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdmmc0_cmd_dat_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdmmc0_ck_cd_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0_default { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts new file mode 100644 index 0000000..21986ec --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ +/dts-v1/; +#include "sama5d27_wlsom1.dtsi" + +/ { + model = "Microchip SAMA5D27 WLSOM1 EK"; + compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5"; + + chosen { + stdout-path = &uart0; + }; + + onewire_tm: onewire { + gpios = <&pioA PIN_PC9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + + ahb { + sdmmc0: sdio-host@a0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + status = "okay"; + }; + + apb { + macb0: ethernet@f8008000 { + status = "okay"; + }; + + uart0: serial@f801c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + status = "okay"; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + pinmux = , + , + , + ; + bias-disable; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = ; + bias-pull-up; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d27_wlsom1.dtsi b/arch/arm/dts/sama5d27_wlsom1.dtsi new file mode 100644 index 0000000..3d27570 --- /dev/null +++ b/arch/arm/dts/sama5d27_wlsom1.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1 + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +/ { + model = "Microchip SAMA5D27 WLSOM1"; + compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5"; + + memory { + reg = <0x20000000 0x10000000>; + }; + + ahb { + apb { + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + + ethernet-phy@0 { + reg = <0x0>; + }; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c3b21b7..24994d4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -180,6 +180,20 @@ config TARGET_SAMA5D27_SOM1_EK processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM in a single package. +config TARGET_SAMA5D27_WLSOM1_EK + bool "SAMA5D27 WLSOM1 EK board" + select SAMA5D2 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + help + The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package), + a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless + module providing bluetooth and wifi is also embedded. + The SAMA5D2 SiP integrates the ARM Cortex-A5 + processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM + in a single package. + config TARGET_SAMA5D2_ICP bool "SAMA5D2 Industrial Connectivity Platform (ICP)" select CPU_V7A @@ -292,6 +306,7 @@ source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" +source "board/atmel/sama5d27_wlsom1_ek/Kconfig" source "board/atmel/sama5d2_icp/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" diff --git a/board/atmel/sama5d27_wlsom1_ek/Kconfig b/board/atmel/sama5d27_wlsom1_ek/Kconfig new file mode 100644 index 0000000..4b192b0 --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D27_WLSOM1_EK + +config SYS_BOARD + default "sama5d27_wlsom1_ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d27_wlsom1_ek" + +endif diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS new file mode 100644 index 0000000..59671ac --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D27 WLSOM1 EK BOARD +M: Nicolas Ferre +M: Eugen Hristev +S: Maintained +F: board/atmel/sama5d27_wlsom1_ek/ +F: include/configs/sama5d27_wlsom1_ek.h +F: configs/sama5d27_wlsom1_ek_mmc_defconfig diff --git a/board/atmel/sama5d27_wlsom1_ek/Makefile b/board/atmel/sama5d27_wlsom1_ek/Makefile new file mode 100644 index 0000000..cf827ae --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +# +# Author: Nicolas Ferre + +obj-y += sama5d27_wlsom1_ek.o diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c new file mode 100644 index 0000000..483ec82 --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig new file mode 100644 index 0000000..6b11fcb --- /dev/null +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f00000 +CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h new file mode 100644 index 0000000..cc41560 --- /dev/null +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D27 WLSOM1 EK Board. + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#endif + +#endif From patchwork Thu Aug 8 07:48:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143864 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="0vU70H3U"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640sr05Xqz9sDB for ; Thu, 8 Aug 2019 17:50:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B838DC21C29; Thu, 8 Aug 2019 07:48:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E579EC21F51; Thu, 8 Aug 2019 07:48:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B6268C21F24; Thu, 8 Aug 2019 07:48:39 +0000 (UTC) Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) by lists.denx.de (Postfix) with ESMTPS id 5B8E6C21F0C for ; Thu, 8 Aug 2019 07:48:36 +0000 (UTC) Received-SPF: Pass (esa3.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa3.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa3.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa3.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa3.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: +Mhr/uLj89H+dM5Uqfy5pQ6194kpjOys9627VTY0BXNk2udH5pDRYKSEJEXCynZCpPt05UN+F1 MrmwesfXhW7vfMBU+gFoui9kV8YrzHDyNhzcUWn8dLCwx304+jBmazRnUfYKooHntia47nI9Ey s2PU8PJGjgakdJUutQTNKaCPmz+UvdyW8Aa96jC7lfzK+UInGtIExIEnaEppCMBgnC0yhxea2X xKG9by0nkFDYu7D8quDk67xWJUYvy6JvxlkF4ZGZOUWBBfx4puCFEJlJMo24oRR47rcJdhBEEr tbc= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="44406259" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:31 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:29 -0700 Received: from NAM03-BY2-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:29 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MpV+tfVBELSleGGXX6o1pLhE3Ke/epyXZh5Iq1TwCrqkxH4aycE2ErwPr6n2FNcfH91rQk+9PvtRs/VW2W2FU1umakloV6/Ur12WlaV916L6ILrnhdtIUm3hcc6l2UPz992QA2y9Yc297fJ39S2kXpURanRlQ7MMdvBFZvCgSCTNhU4VPKqp8E5WmLutye9OhSquJQb/CNQmGmLFeOIqzEmBl4Yot3GoYtXQOrI7dBzueRNh81j/oFRnNqiGzkUkfMPejoaKf0fHqQ68BQfG1xPMEgwB2e85MrfmE5Ei6dI7ht6fb4bMct0KHqWqrkKoohaUypTq9NCAHstRiGrPGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W45x2jJnvUA9cAhUJ84KgDVuWrLd2ovBZXrq0MhKNvI=; b=g9YlmSwGFPY1YE7k5oAWYq63m8NcDUMlGnOc1Au4YkCgLVLJf4f9OYXL4yTec+XL3fIHhLmnCBKX2QSmTQ7NnXae8IAVy0LFL++LdzUeF0Q/3WAhgldXY7GHCMf2dPuPgQNVz0aeuAX++jg5o7WeCJd9rHy2ghroA2qyB9XcaHFe+irFbP6wxDGPvnEnJI89B8vDHBgGP81tbi/TnvjDorLXwv7a+4pIT9Bonric2TDYdotQOtgtlgDxfOR6yvMRH4OHW9TGjgcnV527bWtdpfTYCk1KCS4ofoSlFINba8gyQIOPsmZdo6xaTvGkmgHTipRJhwajnbN6KYLg8I6rXg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W45x2jJnvUA9cAhUJ84KgDVuWrLd2ovBZXrq0MhKNvI=; b=0vU70H3UfbupLTVLrph417/QBIem0fNT5WiAj017b6G1rSEYLkRMsJtXNfQ4TZkdCCxrYqHIyC4eJxhgSEG6Tlt/XjFnW1RjQQ2Y/71YxgiKsGTgZKLmYvVDZvC4dUPvBsJfrItwSb8+mLpU/w14Rmb+4zsCZKlnu/pi3Hjl2cw= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB1609.namprd11.prod.outlook.com (10.172.36.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2157.15; Thu, 8 Aug 2019 07:48:28 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:28 +0000 From: To: , , Thread-Topic: [PATCH 3/7] ARM: at91: sfr: convert to Kconfig Thread-Index: AQHVTb2q5edylIVD8kmCM1EE6CbmHQ== Date: Thu, 8 Aug 2019 07:48:28 +0000 Message-ID: <1565250163-21502-3-git-send-email-eugen.hristev@microchip.com> References: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f65672d1-2bff-4553-b906-08d71bd4cd0c x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:DM5PR11MB1609; x-ms-traffictypediagnostic: DM5PR11MB1609: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6108; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(136003)(396003)(366004)(376002)(346002)(189003)(199004)(66556008)(2501003)(186003)(2906002)(86362001)(50226002)(66066001)(110136005)(6436002)(8936002)(478600001)(14454004)(316002)(76176011)(52116002)(99286004)(2616005)(26005)(102836004)(386003)(11346002)(476003)(486006)(6506007)(7736002)(6486002)(66946007)(2201001)(446003)(64756008)(305945005)(66446008)(81156014)(3846002)(4326008)(66476007)(81166006)(6116002)(25786009)(8676002)(5660300002)(53936002)(71200400001)(6512007)(71190400001)(256004)(107886003)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB1609; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wx4AS882AUQ8j26ekLVPKIg6csQI2b06046GiX7rl2GXCVrCh6fJLf/xekTshlZRnVlnnd7+bJ4JD8ovZdy4ltqe3wn5luU4bamWeK6efttKKPze62bNp0XNxy9Reso7ylJzA4cIDb9+DX2oGH74/uCBPlvG6l28J2DVQQZP4J0YKgvUTUiyWCpN25pCbXMse3Pjuko5x+WS4kd/z+r2rQ4GgaYZdUoUygKpCH7VnP7vMckNLzZZW2DCQWLLtRWNIJXEPvoIYCylyVyFA5BHIKzrZe6w0N9iHbkH6VnTUMvx6oy+kPkNS0wF/loKbbSyKDGBfMIhVaQ8PtYdlVKrUbR+niiI31FG09tr2iutxCSAWY0Pn+V9LrMQrxNiD7B6f6hstNL53BrwLkD2dkC1ISSauVYBRhwbjhO2TJMNY6w= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f65672d1-2bff-4553-b906-08d71bd4cd0c X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:28.6123 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jHfs4aVUMYnCoelNCgTdwf0z2UeIXEJIHoXzpzWoCwluYen1zOmc+6DQ5fhCz33P6Y/pNEyxS/73wEAdbKc3i5ggki5qs0wD8oV7e3dVAJo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1609 Subject: [U-Boot] [PATCH 3/7] ARM: at91: sfr: convert to Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Eugen Hristev This converts the at91 sfr to Kconfig Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/Kconfig | 9 ++++++++- arch/arm/mach-at91/Makefile | 5 +++-- arch/arm/mach-at91/atmel_sfr.c | 3 +++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 24994d4..ad09731 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -46,6 +46,7 @@ config AT91SAM9X5 config SAMA5D2 bool select CPU_V7A + select ATMEL_SFR config SAMA5D3 bool @@ -54,6 +55,7 @@ config SAMA5D3 config SAMA5D4 bool select CPU_V7A + select ATMEL_SFR choice prompt "Atmel AT91 board select" @@ -173,6 +175,7 @@ config TARGET_SAMA5D27_SOM1_EK select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL + select ATMEL_SFR help The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package), a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM @@ -196,7 +199,7 @@ config TARGET_SAMA5D27_WLSOM1_EK config TARGET_SAMA5D2_ICP bool "SAMA5D2 Industrial Connectivity Platform (ICP)" - select CPU_V7A + select SAMA5D2 select SUPPORT_SPL select BOARD_EARLY_INIT_F select BOARD_LATE_INIT @@ -292,6 +295,10 @@ config TARGET_WB50N endchoice +config ATMEL_SFR + bool + default n + config SYS_SOC default "at91" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 045ac88..cbd0ed6 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,10 +7,11 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o -obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o +obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o obj-$(CONFIG_SAMA5D3) += bootparams_atmel.o mpddrc.o spl_atmel.o -obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o +obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o obj-y += spl.o +obj-$(CONFIG_ATMEL_SFR) += atmel_sfr.o endif obj-y += clock.o diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 2225115..07bd8ab 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -9,6 +9,7 @@ #include #include +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4) void redirect_int_from_saic_to_aic(void) { struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; @@ -26,3 +27,5 @@ void configure_2nd_sram_as_l2_cache(void) writel(1, &sfr->l2cc_hramc); } +#endif + From patchwork Thu Aug 8 07:48:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143868 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="ahpyZkl2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640vF4x9rz9sDB for ; Thu, 8 Aug 2019 17:51:53 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 62456C21F3C; Thu, 8 Aug 2019 07:50:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C0A9BC21F64; Thu, 8 Aug 2019 07:49:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 91889C21F52; Thu, 8 Aug 2019 07:48:41 +0000 (UTC) Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) by lists.denx.de (Postfix) with ESMTPS id 64F6EC21E76 for ; Thu, 8 Aug 2019 07:48:38 +0000 (UTC) Received-SPF: Pass (esa5.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa5.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa5.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa5.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa5.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: +HSUpwCixJB22pmw5W6UppjkvkMSlLcbHCc28aEX4/ROn98D3UtRBuYv4WNakCfs0oTr9HdA7u tIDa/WTImPTilyJpDqjWKd+P1ddzeRpMPODb+AU4ZZ4wbUP0XzPcJMcgPeJ85OhBFHWDLPViP2 UKnXuoeR0E+PHX7r+9tcFWMg2TK1oIp97PQ7HprSNEYwR7bpAZYxx/SkveG0NAcjCQBI30UqJK GFJKFuyT3fyJDYAaYQjuTSohJWOhC4cEuca9gwGFKseo+MsicPvO26M6TBLNxyb4zos/1WDNfK r7I= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="42865290" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:32 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:32 -0700 Received: from NAM01-BN3-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:31 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JIyO02a89BoCqMe/cxcMc5eBcLbgvJXM/Ni5Liai7tMsg2Ji967eWLfu4cz0Ssa9OrEIuL03z0FlAObdro1DDZYjLTs7aS84HE46yAvjfQC2D4BPRPAREi/uAT73U0OBrtEtQx4pmH9N+lKMnsstYx+EhXqiLfIm6/eP7HXDVImEDlbNrCCdOE/8JxUqHo/FYdCzqAelmcjFEpWZS2MMHZ5/OcbKYM/MrlDEwKFxNvKWybP4JVJgJI3DbrGlkShK/GQdfH9uRbDrMaG8S5A2XZhg3ICgF4aWmkaGSbvD8YPXnppH40oT90HjNqUmrUurXwBr/wEMhS9UjkZldrGFvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kTKjsCTdQWH+l0Yvfh+Y9bKsZMMv3I/3z3hL2wp+YDU=; b=UMc9Nb4OZzWX5KBpRiRP1n/rzH0zYpXGf94LOgY+odukVvmkoIy5kzhg8Xul5kwTxT2HzVlHdlGfKQbFgA+ydxY/mjp7BtGPgZaKd2XwCBcOVhmXhnBqtTEwMtqzF42Sh8C/yM7dlCSoY3NvG/Im+bwIgeEMtODb0i7YTM3S4V6cZuLR1KsKvayYCEBRwuU98bNpSr82pqdUJ44PiauOQO8pDge953wHdgRaiSgi3D9yiyqtYEmCGks5sTjO3E4ybQeJ6oN/YSYVKDpHxYNT87EqTsmaJcReyT97sIJ48MpT1IM0t84e67+gzZigYS/BiVlAYb7L+A8SeHelX5ILgQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=microchip.com;dmarc=pass action=none header.from=microchip.com;dkim=pass header.d=microchip.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kTKjsCTdQWH+l0Yvfh+Y9bKsZMMv3I/3z3hL2wp+YDU=; b=ahpyZkl2LLvL0e6/9J2mLmOCjiU+xDWQUcVMuy8QWXP8v9e1QTqu+8Ltv0HsIjrXaTChBA98o5Jm90qW+MFZVgg75t0UbbglNl8CvBWxsWOm4WDwUotvmB/Vm9bde7YXcsHLtOvksfYOUdJIVgivoXgX8C603bHM14koHgliUbE= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB0075.namprd11.prod.outlook.com (10.164.155.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Thu, 8 Aug 2019 07:48:30 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:30 +0000 From: To: , , Thread-Topic: [PATCH 4/7] ARM: at91: sfr: implement DDR input buffers open function Thread-Index: AQHVTb2rwo7th3K9s0+of0AUPJfkLQ== Date: Thu, 8 Aug 2019 07:48:30 +0000 Message-ID: <1565250163-21502-4-git-send-email-eugen.hristev@microchip.com> References: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0bd4a592-ffd3-452e-ab7e-08d71bd4cdf8 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:DM5PR11MB0075; x-ms-traffictypediagnostic: DM5PR11MB0075: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(376002)(396003)(346002)(39860400002)(366004)(136003)(199004)(189003)(71190400001)(6512007)(2616005)(446003)(486006)(107886003)(2906002)(476003)(99286004)(6486002)(11346002)(6436002)(66066001)(53936002)(6116002)(86362001)(2201001)(3846002)(71200400001)(66556008)(66476007)(64756008)(66446008)(50226002)(66946007)(7736002)(316002)(25786009)(8676002)(478600001)(305945005)(5660300002)(256004)(4326008)(8936002)(186003)(386003)(6506007)(52116002)(81166006)(81156014)(36756003)(26005)(110136005)(76176011)(14454004)(2501003)(102836004); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB0075; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: m61YpQbM+yMopla64AAWUrUL63CHJ0jiFrUAtkOkweRnkf3IogRkDEhpcZb8lcux5gcIdGncipRBWwMNBan983NOz9qynH8DuEaVPmMh4OCdOAhY/qwqmVgsHaRaHuw6sAAmZntyG9rzfHy3W2Zu/WVxXl2Zl1XiLi5tyYe6K/emzBUABDP5+ufvKZNzlEDf9er7Iz+oEuMJH4MOWSoXfEIX2Fpt27t8/OPUob6hxyN+eTVkGChyHyqzEcyT/wXn/BiVk4pXsthf5qBOb/SQRglLKn/al4BqhlE6e4uGw6Y19OO8lw7TZ65p3wZFvD3UYNiELAKQx2usWVFYHI7u5PUEV+QzrJq1GKhC3h1Mk+H6LgDjIhkuC8N7lmUZetGZ8f4N6HwpRPc+MyT8t87Zft1L9Umum4nFtjTJLulNndk= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0bd4a592-ffd3-452e-ab7e-08d71bd4cdf8 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:30.0766 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jrlTGQzLVyOesyEtDa5CmejDtK7KE8r/XXNHnHpxGQ7QEu3BC90B4C6kl6UuqsFGLNsr6NaxUsO5jQZwdeew3D3ra1o59qBERKewACEo0WM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0075 Subject: [U-Boot] [PATCH 4/7] ARM: at91: sfr: implement DDR input buffers open function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Eugen Hristev Add a function in SFR implementation that will open the DDR input buffers. This can be called at DRAM initialization time. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/atmel_sfr.c | 11 +++++++++++ arch/arm/mach-at91/include/mach/at91_common.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 07bd8ab..13cfba0 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -29,3 +29,14 @@ void configure_2nd_sram_as_l2_cache(void) } #endif +void configure_ddrcfg_input_buffers(bool open) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + if (open) + writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, + &sfr->ddrcfg); + else + writel(0, &sfr->ddrcfg); +} + diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index df7d0e7..e929b5e 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -35,6 +35,9 @@ void at91_disable_wdt(void); void matrix_init(void); void redirect_int_from_saic_to_aic(void); void configure_2nd_sram_as_l2_cache(void); +#ifdef CONFIG_ATMEL_SFR +void configure_ddrcfg_input_buffers(bool open); +#endif int at91_set_ethaddr(int offset); int at91_video_show_board_info(void); From patchwork Thu Aug 8 07:48:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143862 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="fx9KcMMr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640rx43htz9sDB for ; Thu, 8 Aug 2019 17:49:53 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 176FCC21E1A; Thu, 8 Aug 2019 07:48:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5CCBFC21F4E; Thu, 8 Aug 2019 07:48:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D4302C21F31; Thu, 8 Aug 2019 07:48:37 +0000 (UTC) Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) by lists.denx.de (Postfix) with ESMTPS id CAF6BC21E53 for ; Thu, 8 Aug 2019 07:48:33 +0000 (UTC) Received-SPF: Pass (esa2.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa2.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa2.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa2.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa2.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: Yi2N146JR99i73m76MD7+GLy3CYEdH7rxM8v64G8ENwlTuAJrxyEnk1Sy24ctGmdMNyDZA1Cf5 XlvSt4igJWSPuFvvotWRsWBOpHGVHrlu0Fo2vv1Yc2qccPRf5oR1Ske3DSi8grxLoy3z+5CgLL oHiVo9Nyyq76/Ch1KcLslredC/61FDiUBkct98153dUKNYorUqLeIofRls6I66TNXV213WV8iI ncwlwtk+UK5rXi+ksQA7qtE1PxPzOXkJSn7yLtZf8snS8fSp11qiQFByoCd2Lk3HBQN+sEjnVZ MFI= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="44356104" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:33 -0700 Received: from NAM01-BN3-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:33 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Tvnb9MrLV75AAenygHwOAIP/E1Mi1iBKsLE3C5GK4fCClVSYL3D2KPK2GovADmt2ePAH84KqtfLeSRALHuDDBHL2Zsaj3DMlUZN536sOOeF8FHhUfmU0iREFote0M5HXcb+ECg4ywnwj0rf3WwLJvVnJHMjuqKaHpSE6TYj6sdVd/YdRFXyQMFjGpNhZjiq3Xy2m4hvizVj+4qrwc0XVTmcihH0BuZ5qP9yY5lIvc2V8hF2gVQQz8zcnquvry3b7iU2hXk432scO26w9OoBMClCom60lnytG02mU5zqeKAwuKGyX3EXdsvaHppiDljF9frjTbA5fdctIC+btAcY2XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HbVs3l+Kh8EdHJW49UdDQTfo2vUe1lHIDkoqaxyY8Vk=; b=F5STXEwUMnpiDxr5TIAUdekoVIurweoXNEc48nFWBKqX87BUv4qQbBevAcDW6GkCIKOYh5qoScZj5lRk9sbwVaLmP0dp9hRCVBZe+xAnh8HAaDADEBp9RvqFhjfW8kY3OIjK01OlB98obXPBl3YQzW67aUp5h0tkn77E6jyA2TKKGAWOFzsLZBdhsmrwHwYsV2hj9+VTL7KxdMuba7XNz5gy3uIcxIQxoTDKnFSJZelO/eyvx28V+6m8XhTooeoRUQDMc5DE9nwPCLm92qOnO1FakblSV6jLJ5qTov6zngBSY5v+w7h5RX6PxgBD9ouHGKsnGUkYzBQ2EOMNF0nqyA== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=microchip.com;dmarc=pass action=none header.from=microchip.com;dkim=pass header.d=microchip.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HbVs3l+Kh8EdHJW49UdDQTfo2vUe1lHIDkoqaxyY8Vk=; b=fx9KcMMrLlr0kmoS1bJenClJK6VoJGmKbgH4GFeXpgEASG7AYvqs8+PGevTnPVjZPwdt+9Y2ViUiQPrsfWKbiU3NCe6xqGY/CrvY/NJwFmHZmgsVlz7izNffPaZr3xzKhbpa8BU45Jzr9Lh1Z5Q6ayZmctDbFR54X5TSuHnkpFs= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB0075.namprd11.prod.outlook.com (10.164.155.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Thu, 8 Aug 2019 07:48:32 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:32 +0000 From: To: , , Thread-Topic: [PATCH 5/7] board: laird: wb50n: use configure_ddrcfg_input_buffers Thread-Index: AQHVTb2sLDnrrsGWdk+MHHHhRWKO2g== Date: Thu, 8 Aug 2019 07:48:31 +0000 Message-ID: <1565250163-21502-5-git-send-email-eugen.hristev@microchip.com> References: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c370c2f5-3078-4e8e-3e90-08d71bd4cee3 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:DM5PR11MB0075; x-ms-traffictypediagnostic: DM5PR11MB0075: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:341; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(979002)(376002)(396003)(346002)(39860400002)(366004)(136003)(199004)(189003)(71190400001)(6512007)(2616005)(446003)(486006)(107886003)(2906002)(476003)(99286004)(6486002)(11346002)(6436002)(66066001)(53936002)(6116002)(86362001)(2201001)(3846002)(71200400001)(66556008)(66476007)(64756008)(66446008)(50226002)(66946007)(7736002)(316002)(25786009)(8676002)(478600001)(305945005)(5660300002)(256004)(4326008)(8936002)(186003)(386003)(6506007)(52116002)(81166006)(81156014)(36756003)(26005)(110136005)(76176011)(14454004)(2501003)(102836004)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB0075; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: CA1r6gB6LpZ6t3rkJm/0A3rQOnwyc2/PxNVwPrrmfGxYwXSwc3+JwAG4ITB5Qtrio4smA2n4Ce9hSVfXE2FcMT9BSaj5Drh7qUEmRJuwmu6dWGmt8C01XTo7C/Zeq7PuHSdrmp103hB4QJeWAob8VhQ5kJ9rX+CehxGHWF3M0rW8GrQjY0QYEnzFQ2yVTLE/A7DwMsQCbi+3HhPiP2RC4A2actPfonYmo1+r6voHtYUJnuEX0/9nvCtNzydjMtuLNPFbDH0vRATYP4qTnj1qqrVBWKgDq1Z10l2OGV99Kw8SWdlgxq1Q69ms/b6cL294aD8QeIZ4NyM2K0/ALMYlci8TlNHC2y3EmAKlUJkVJKUklzgZX8rQ2cMr9mcLyUh+5b7dpO1h4V7qGGZVuoER8H8Zt3tP8DAOTu6dy/RqipI= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c370c2f5-3078-4e8e-3e90-08d71bd4cee3 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:31.8758 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iLqRSw3BacJiHNjqlcU9Fbp7cb6i4pVcU3wPdRwSrSsxcRnWHdm8R/lC39oZK1L7WptDcqSW2ZPnTAPHSDuIQIaS/O7tlN/Gr0cdIXho6t8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0075 Subject: [U-Boot] [PATCH 5/7] board: laird: wb50n: use configure_ddrcfg_input_buffers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Eugen Hristev Replace code with new function configure_ddrcfg_input_buffers from SFR mach driver. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/Kconfig | 1 + board/laird/wb50n/wb50n.c | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index ad09731..ce0b1b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -292,6 +292,7 @@ config TARGET_WB50N select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL + select ATMEL_SFR endchoice diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c index 89d3795..1598e5c 100644 --- a/board/laird/wb50n/wb50n.c +++ b/board/laird/wb50n/wb50n.c @@ -172,13 +172,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; struct atmel_mpddrc_config ddr2; ddr2_conf(&ddr2); - writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, - &sfr->ddrcfg); + configure_ddrcfg_input_buffers(true); /* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); From patchwork Thu Aug 8 07:48:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143865 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="mTmbl0Ad"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640t21JM9z9sDB for ; Thu, 8 Aug 2019 17:50:50 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C9E85C21C29; Thu, 8 Aug 2019 07:49:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 98FDFC21F4D; Thu, 8 Aug 2019 07:49:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6C034C21F04; Thu, 8 Aug 2019 07:48:41 +0000 (UTC) Received: from esa6.microchip.iphmx.com (esa6.microchip.iphmx.com [216.71.154.253]) by lists.denx.de (Postfix) with ESMTPS id 1BCF9C21F3C for ; Thu, 8 Aug 2019 07:48:37 +0000 (UTC) Received-SPF: Pass (esa6.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa6.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa6.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa6.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa6.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: S3zPYLxaNl7ODGgYRsRfje/TAdPOhjffs6r8nl6eearnjSn/FjX+6uZudvvCWtZ/JClJQJnFRZ WgkSDFidtAk7I0Q0h9fGcJFHvnHBQ20EbkJUmI5f4YD1nPvDItVIYCxY5oKXLLQX0++++gVQ1f vYrW1UJqoh4J54eSBbdPRF3Lj4A100rhT2QBW/vrFJfsq5+CsPNT0wzykJLttzRtWKu93Ab2Pj XHlHdFvpZ6HRL+qhr9AbeLkWyi/Q87mCV7OvPZamjKVh/k+/Rg1UX1crE9gBNe0FBfld9ris6j /0w= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="41487512" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:36 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:36 -0700 Received: from NAM01-BN3-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:35 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WGVhcJibF2kAIsgJJ/TXG68pgXYkcbg3XejsuQxDgO4CdGW0TI9of/yuzwyUNY6O1eMmr06iEt2xIYrsyGu40XKSzo++UiG95nQO6MDg6b71hmu9mwoxpyO0rXJgh0fEXXkgJSez0BKEi3N/Rf3glzmh95KHoZTy2PYsogbLcuou63CFWwRLYYDvf2ZQHXVChT+LpTguE1RXnLyXPWFADqB/6MX9kNW2Y9ADw+ZcUmrBdwDrP5MHT7UFF0/UUlb6ecEXO0/G4kXJ330yPgXMxuE7Y+KMtlkiUXK1dMJjHnA+QrfswSQVRk8plLeECinGkrxAl86YURS2jqLu8d00Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0KJQIJ2mLAQjVAOzoFUj+DYoQu1CDp0BOFyLj91xyQQ=; b=jelmMym9Yl3NRJ/izAiPRMgJbZyFhVDzKfQ9IBcn6Zb7yJbUDsXXcHLmL8D5KR570MkPM4URsEaVzyJKCqeiA1iNjg3/TtViKPld/ijzUX+j+wHTd8SuLj6AF19RuJm27W5ilyXKqGl6IUjWhsU+1kjCN1w6Jzb7ueR+vbiB7hDmg7g99HYbfC5isSyxkFcfGzn0+pHfDq43HZibgGgP5DMPNJSmurIZLGhLtGfFFUsTlSLThLh3TNi4nB52zMK64P4e0LaYG0rY/YAuBtUjbgGteCbxbpN/pFqgU8IfPOSiXEo+7OZbm5iK0lbNzmL2gZw/oA73+iLJa2WFMNfFKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=microchip.com;dmarc=pass action=none header.from=microchip.com;dkim=pass header.d=microchip.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0KJQIJ2mLAQjVAOzoFUj+DYoQu1CDp0BOFyLj91xyQQ=; b=mTmbl0Adu+Z/y3H501Nd84O+zkNhSZtE9KX9ffF6jBiVIil5SjGtVsVRGfxFh+GxzGb1DUI+y35yfDuxnCg9OGCOxqB7ZlB9zxuDbqaYUBNpd7zr4BNbMWvkPlBh/Y91619WO67KLnEEBJYR5wPrTyGvnEuKVw1+au5JxslV+Cg= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB0075.namprd11.prod.outlook.com (10.164.155.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Thu, 8 Aug 2019 07:48:34 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:34 +0000 From: To: , , Thread-Topic: [PATCH 6/7] ARM: at91: mpddrc: add lpddr2 initialization procedure Thread-Index: AQHVTb2uS9vtrUpwmESFZggFdc/Bkg== Date: Thu, 8 Aug 2019 07:48:34 +0000 Message-ID: <1565250163-21502-6-git-send-email-eugen.hristev@microchip.com> References: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 561a5abe-bfcf-4220-a966-08d71bd4d05b x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:DM5PR11MB0075; x-ms-traffictypediagnostic: DM5PR11MB0075: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2043; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(376002)(396003)(346002)(39860400002)(366004)(136003)(199004)(189003)(71190400001)(6512007)(2616005)(446003)(486006)(107886003)(2906002)(476003)(99286004)(6486002)(11346002)(6436002)(66066001)(53936002)(6116002)(86362001)(2201001)(3846002)(71200400001)(66556008)(66476007)(64756008)(66446008)(50226002)(66946007)(7736002)(316002)(25786009)(8676002)(478600001)(305945005)(5660300002)(14444005)(256004)(4326008)(8936002)(186003)(386003)(6506007)(52116002)(81166006)(81156014)(36756003)(26005)(110136005)(76176011)(14454004)(2501003)(102836004); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB0075; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: H8qHugt7pk/XaPHLcVv2Rc8jhAQtUrwl4npPLAZ2WTjUXxgzdPfJv4GzZmLCRdowlMY94IgYboPkmKx+qsPGR8VuRMGc2fG6l0Vr9jFd6DMCwnaQ3U9tKG7S4k3wu4SuwFtgKLymtgiJQgOWBrMdhTx/HasiSnP9Fng05mGkrPBiRp+NPWG6jYb5nElR2N2zbSOeQoa3RyNeUJDs/4xYBavM3xwaeZXBxF4HwqHr+rfgegnvbxrsrmr85AN3XjbC5q/flkii1CJjj2qI9pDdO0D2jwKma9PHt35azdCTxne8Ifp9VP+vi18IGRS9xW9IJBrttnZmZHVtWg2jlofn2eGbFKQKATZIvKLuAu2aBfpcnzMYVYeYi5kQJ4QAYljYvLAxSgYbaoAugRPkrPFr5MK23ndj4EY0MCNHWbipHt0= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 561a5abe-bfcf-4220-a966-08d71bd4d05b X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:34.3557 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1jnJ/tv4CAzqGoERq7ND9+YefKFFLeDnfl/zjlD3wQ2ey0srqLmlpsoaTUfkv7y/OGhHBAIh/WPQA1jzlf3JmJPh9EAUM7GUepEekY7dSas= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0075 Subject: [U-Boot] [PATCH 6/7] ARM: at91: mpddrc: add lpddr2 initialization procedure X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Eugen Hristev Implement the lpddr2 initialization procedure for at91 mpddrc multi-port ddram controller. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 23 ++++ arch/arm/mach-at91/mpddrc.c | 162 +++++++++++++++++++++++++ 2 files changed, 185 insertions(+) diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 45a76a6..40ec87e 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -18,6 +18,9 @@ struct atmel_mpddrc_config { u32 tpr1; u32 tpr2; u32 md; + u32 lpddr23_lpr; + u32 cal_mr4; + u32 tim_cal; }; /* @@ -61,6 +64,10 @@ int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); +int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value); + int ddr3_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); @@ -74,6 +81,11 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 +#define ATMEL_MPDDRC_MR_MRS(v) (((v) & 0xFF) << 0x8) + +/* Bit field in refresh timer register */ +#define ATMEL_MPDDRC_RTR_ADJ_REF (0x1 << 16) +#define ATMEL_MPDDRC_RTR_MR4VALUE(v) (((v) & 0x7) << 20) /* Bit field in configuration register */ #define ATMEL_MPDDRC_CR_NC_MASK 0x3 @@ -157,6 +169,7 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM 0x7 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) @@ -206,4 +219,14 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3 +/* Bit field in LPDDR2 - LPDDR3 Low Power Register */ +#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x) (((x) & 0xf) << 24) + +/* Bit field in CAL_MR4 Calibration and MR4 Register */ +#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x) (((x) & 0xffff) << 0) +#define ATMEL_MPDDRC_CAL_MR4_MR4R(x) (((x) & 0xffff) << 16) + +/* Bit field in TIM_CAL Timing Calibration Register */ +#define ATMEL_MPDDRC_CALR_ZQCS(x) (((x) & 0xff) << 0) + #endif diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index 81ccd6a..3df0ea7 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -10,6 +10,7 @@ #include #include #include +#include #define SAMA5D3_MPDDRC_VERSION 0x140 @@ -18,6 +19,7 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr, u32 ram_address) { writel(mode, &mpddr->mr); + dmb(); writel(0, ram_address); } @@ -227,3 +229,163 @@ int ddr3_init(const unsigned int base, return 0; } + +int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base; + u32 reg; + + writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr); + + writel(mpddr_value->tim_cal, &mpddr->tim_cal); + + /* 1. Program the memory device type */ + writel(mpddr_value->md, &mpddr->md); + + /* + * 2. Program features of the LPDDR2-SDRAM device and timing parameters + */ + writel(mpddr_value->cr, &mpddr->cr); + + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* 3. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * 3bis. Add memory barrier then Perform a write access to + * any low-power DDR2-SDRAM address to acknowledge the command. + */ + + dmb(); + writel(0, ram_address); + + /* 4. A pause of at least 100 ns must be observed before a single toggle */ + udelay(1); + + /* 5. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* 6. A pause of at least 200 us must be observed before a Reset Command */ + udelay(200); + + /* 7. A Reset command is issued to the low-power DDR2-SDRAM. */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(63), ram_address); + + /* + * 8. A pause of at least tINIT5 must be observed before issuing + * any commands + */ + udelay(1); + + /* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */ + reg = readl(&mpddr->cr); + reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET; + reg |= ATMEL_MPDDRC_CR_ZQ_RESET; + writel(reg, &mpddr->cr); + + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(10), ram_address); + + /* + * 9bis: The ZQ Calibration command is now issued. + * Program the type of calibration in the MPDDRC_CR: set the + * ZQ field to the SHORT value. + */ + reg = readl(&mpddr->cr); + reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET; + reg |= ATMEL_MPDDRC_CR_ZQ_SHORT; + writel(reg, &mpddr->cr); + + /* + * 10: A Mode Register Write command with 1 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(1), ram_address); + + /* + * 11: A Mode Register Write command with 2 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(2), ram_address); + + /* + * 12: A Mode Register Write command with 3 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(3), ram_address); + + /* + * 13: A Mode Register Write command with 16 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(16), ram_address); + + /* + * 14: In the DDR Configuration Register, open the input buffers. + */ +#ifdef CONFIG_ATMEL_SFR + configure_ddrcfg_input_buffers(true); +#endif + + /* 15. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * 16: A Mode Register Write command with 5 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(5), ram_address); + + /* + * 17: A Mode Register Write command with 6 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(6), ram_address); + + /* + * 18: A Mode Register Write command with 8 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(8), ram_address); + + /* + * 19: A Mode Register Write command with 0 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(0), ram_address); + + /* + * 20: A Normal Mode command is provided. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* 21: In the DDR Configuration Register, close the input buffers. */ +#ifdef CONFIG_ATMEL_SFR + configure_ddrcfg_input_buffers(false); +#endif + + /* + * 22: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register. + */ + writel(mpddr_value->rtr, &mpddr->rtr); + + /* 23. Configre CAL MR4 register */ + writel(mpddr_value->cal_mr4, &mpddr->cal_mr4); + + return 0; +} From patchwork Thu Aug 8 07:48:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1143863 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="x5zSOrRa"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4640sW0xqDz9sDB for ; Thu, 8 Aug 2019 17:50:23 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C998EC21F60; Thu, 8 Aug 2019 07:49:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24505C21F41; Thu, 8 Aug 2019 07:49:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ED7F3C21F60; Thu, 8 Aug 2019 07:48:42 +0000 (UTC) Received: from esa6.microchip.iphmx.com (esa6.microchip.iphmx.com [216.71.154.253]) by lists.denx.de (Postfix) with ESMTPS id 084B3C21F31 for ; Thu, 8 Aug 2019 07:48:38 +0000 (UTC) Received-SPF: Pass (esa6.microchip.iphmx.com: domain of Eugen.Hristev@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa6.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="Eugen.Hristev@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa6.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa6.microchip.iphmx.com; envelope-from="Eugen.Hristev@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa6.microchip.iphmx.com; spf=Pass smtp.mailfrom=Eugen.Hristev@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: ivK39P/kIMclN4y964FJxQZ5TNmbbcEAmv7jyPK4xtGGLmZK58hdMONe36o/95I7Z5sLid9Mt7 A4ShXipOHHGYudtxhdh5Pv60BYRSg723K7SWlguHsWpwHUJ16nDmw7nG9DJuMKW6a7icAWRvbN rqncx+uEsPfLnXhWsE/CrciEI7oVX2LPcKCWIRR4ALKhKcH2XupSj3OhxCq4m1c5MzNtxn/qt/ Tadozu9+BD1eLa6ALvvVfWEf3oAhtDDEBaoxDAcXnJOoPOfF+rMgKmsFH0DHLjGX2Ge9lY7AIb Spg= X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="41487513" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Aug 2019 00:48:38 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Aug 2019 00:48:37 -0700 Received: from NAM01-BN3-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 8 Aug 2019 00:48:37 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=maT0IgT2E4f9NvCU83o0Do9fd3HlLxnL9CjmqbE+xgCtn9u2J0WGq1owSPTmr5xx74sEg7jYXvUCcB18g2OR4HiVdJlqPv4knA+v1PdKFBG72c0jCoq18K1t0RVRk1x49+7qovfdFpJ1FcuTqS9swgt0fsv1al5zahn3+KwS1Tgvag3fF4MorWhWeY8Yh0ouSo39qWY9HHZ6mAMFMg4HItkGXUGCRDhA1ZMbeCwjKQvIQzwM/laV4a/Z9jxv+/p1X0FmptgSOa4PA9LxkySqWhaV04ckPWHHJ1EpeiHY+8lehOjOy3F4F629BFKlQujLVbfwc56TgPnRFTHv3nXQVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8PSnjB+LVj2ssMsvI27D2Vs25Mnzr6xL7hMA5Ma2rLs=; b=jML5wolZN6EaVe1ZEOK3lPWkmmn46x0UOvnss73+hmluglqs2jOCwY7GWDOQGOl6o184xaXWTV/yZe2erTjEEfZc+HsS71s/VdwoJfrGP4vSt/eLSxRl5ePzHLxUA4wHTDxyomHoZp/44sPZ03LfNpMeM4Hrn/wixstV0Ug9AVcZAHSAwX+e1s9Po0HXWLMG4/h7Qbx2FokH9QcWbKJoU8g47fNI4lxbp0l6CPfDwb8jxtKSQ3E31F77UEecqzZ/8APYY2gwEaI8pP0d/LiSNK5aaiZGk7GDQd61cM8cl0yxVMYxkxvV+hgUpD/AUNM39pcun0Msw9Yr3WRVePESlA== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=microchip.com;dmarc=pass action=none header.from=microchip.com;dkim=pass header.d=microchip.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8PSnjB+LVj2ssMsvI27D2Vs25Mnzr6xL7hMA5Ma2rLs=; b=x5zSOrRa+zJFwaAKljQeqqqFCo8eeSnhTT7xx9nr5xOQStXvJpTJF4dBczpjhHPe1rrAkfRsuQpKVzpB/YEZNQMmk7UlVTCbRB7X2YoESxVbk6m9DZtyeZf/zjfvJ4/Qg5tJlKlJZjLbjAwTcvxfVkXz0aMDwiuHIIVMenHXWkk= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB0075.namprd11.prod.outlook.com (10.164.155.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Thu, 8 Aug 2019 07:48:36 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::c457:dc57:6e6f:f4f3%10]) with mapi id 15.20.2157.015; Thu, 8 Aug 2019 07:48:36 +0000 From: To: , , Thread-Topic: [PATCH 7/7] board: atmel: sama5d2_wlsom1_ek: add SPL support Thread-Index: AQHVTb2v1Y0+tGuKE0uU7QjXs0zFFQ== Date: Thu, 8 Aug 2019 07:48:35 +0000 Message-ID: <1565250163-21502-7-git-send-email-eugen.hristev@microchip.com> References: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1565250163-21502-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P190CA0005.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:2b::18) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3c3574f4-f95d-4f1e-3aa4-08d71bd4d173 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:DM5PR11MB0075; x-ms-traffictypediagnostic: DM5PR11MB0075: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3044; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(376002)(396003)(346002)(39860400002)(366004)(136003)(199004)(189003)(71190400001)(6512007)(2616005)(446003)(486006)(107886003)(2906002)(476003)(99286004)(6486002)(11346002)(6436002)(66066001)(53936002)(6116002)(86362001)(2201001)(3846002)(71200400001)(66556008)(66476007)(64756008)(66446008)(50226002)(66946007)(7736002)(316002)(25786009)(8676002)(478600001)(305945005)(5660300002)(14444005)(256004)(4326008)(8936002)(186003)(386003)(6506007)(52116002)(81166006)(81156014)(36756003)(26005)(110136005)(76176011)(14454004)(2501003)(102836004); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB0075; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: uwhZcqPRDk8PH2WJ/qEYTYoLhsETWO7gnJgoczEMQSZF3WUAp4h2oAA4tWqPTWIvyHKFIPszcIAYd7nMIohbMWH0tesRREPylWxYcw1Z0kDHEYLQrZE47Ub0VlCwXgVQfYSOABBCqhSmEO2T3xA1wp5p6KlIEMJtcamSZnxJ5I1iLiJi8EVVq66XNZGzhWLGQvavsCKgDYvcWPTteExMs601I0XiiTpNM97XoeY2tFifv3TLITZxlqvQhE4gDm2qwQh2HaVJcmxaaSBfoEb19qciIqke/jpX7bToYzTHZqNTFXzgEKGeKXH4npnQvJfQIYioNHya29oKA8VS4kG7kam/H/oe27E7+4msYWs99XrxUkjHak7XFlxv1Pkg3yAjJE6vRN1tCFrS+yOkEB7sP/Zrys7bMycX54wYNCqqgF8= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3c3574f4-f95d-4f1e-3aa4-08d71bd4d173 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2019 07:48:35.9819 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7lAdrR8W8j1FQZKTalDgzs6ps6Cxs3yKu09lmaqGtQf5WAdvjPiEyzi/DoYro1ufRMwBQXB8Pg1dhT78vujcMF8Bfy6mZq8B3XHoP+8XQ0c= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0075 Subject: [U-Boot] [PATCH 7/7] board: atmel: sama5d2_wlsom1_ek: add SPL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Eugen Hristev Add support for SPL for this board: DRAM initialization, PMC initialization, MMC boot. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/Kconfig | 1 + .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 147 +++++++++++++++++++++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 25 +++- include/configs/sama5d27_wlsom1_ek.h | 16 ++- 4 files changed, 185 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index ce0b1b4..1434328 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -189,6 +189,7 @@ config TARGET_SAMA5D27_WLSOM1_EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A + select SUPPORT_SPL help The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package), a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 483ec82..3663ae4 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -78,3 +78,150 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif +} + +void spl_display_print(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ZQ_SHORT | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3); + + /* + * The AD220032D average time between REFRESH commands (Trefi): 3.9us + * 3.9us * 164MHz = 639.6 = 0x27F. + */ + ddrc->rtr = 0x27f; + /* Enable Adjust Refresh Rate */ + ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF; + + ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); + + ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15); + + /* + * According to the sama5d2 datasheet and the following values: + * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s + * Warning: note that the values T driftrate and V driftrate are dependent on + * the application environment. + * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s + * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize + * this timer to 0xFFFE. + */ + ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE); + + /* + * MR4 Read interval is dependent on the application environment. + * Here, we want to maximize this value as temperature is supposed + * to vary slowly in the application chosen. + * If Trefi is 3.9us, we have: + * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads. + */ + ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + ddrc_conf(&ddrc_config); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(40) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 6b11fcb..d7329a2 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -2,12 +2,20 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 -CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y @@ -15,9 +23,13 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DISPLAY_PRINT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -31,9 +43,15 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_UTMI=y CONFIG_AT91_H32MX=y @@ -56,6 +74,7 @@ CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ATMEL=y @@ -64,9 +83,11 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_W1=y CONFIG_W1_GPIO=y CONFIG_W1_EEPROM=y CONFIG_W1_EEPROM_DS24XXX=y CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index cc41560..6bcbc06 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -19,16 +19,28 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* NAND flash */ -#undef CONFIG_CMD_NAND +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif #endif