From patchwork Thu Aug 8 06:19:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1143843 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 463ysn29kDz9sDB for ; Thu, 8 Aug 2019 16:20:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731149AbfHHGU2 (ORCPT ); Thu, 8 Aug 2019 02:20:28 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:30299 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730305AbfHHGU2 (ORCPT ); Thu, 8 Aug 2019 02:20:28 -0400 X-IronPort-AV: E=Sophos;i="5.64,360,1559487600"; d="scan'208";a="23652843" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 08 Aug 2019 15:20:25 +0900 Received: from localhost.localdomain (unknown [10.166.17.210]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5143141CA0D5; Thu, 8 Aug 2019 15:20:25 +0900 (JST) From: Yoshihiro Shimoda To: linus.walleij@linaro.org, geert+renesas@glider.be Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 1/3] pinctrl: sh-pfc: add new flags into struct sh_pfc_pin_config Date: Thu, 8 Aug 2019 15:19:01 +0900 Message-Id: <1565245143-15018-2-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565245143-15018-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1565245143-15018-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org To clean/modify the code up later, this patch just adds new flags "mux_set" and "gpio_enabled" into the struct sh_pfc_pin_config. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- drivers/pinctrl/sh-pfc/pinctrl.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 2824be4..864da24 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -27,6 +27,8 @@ struct sh_pfc_pin_config { u32 type; + bool mux_set; + bool gpio_enabled; }; struct sh_pfc_pinctrl { @@ -364,7 +366,15 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, for (i = 0; i < grp->nr_pins; ++i) { ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) - break; + goto done; + } + + /* All group pins are configured, mark the pins as mux_set */ + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + cfg->mux_set = true; } done: @@ -405,6 +415,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, } cfg->type = PINMUX_TYPE_GPIO; + cfg->gpio_enabled = true; ret = 0; @@ -426,6 +437,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); cfg->type = PINMUX_TYPE_NONE; + cfg->gpio_enabled = false; spin_unlock_irqrestore(&pfc->lock, flags); } From patchwork Thu Aug 8 06:19:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1143845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 463ysn6Z40z9sNy for ; Thu, 8 Aug 2019 16:20:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730305AbfHHGU2 (ORCPT ); Thu, 8 Aug 2019 02:20:28 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:4488 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731145AbfHHGU2 (ORCPT ); Thu, 8 Aug 2019 02:20:28 -0400 X-IronPort-AV: E=Sophos;i="5.64,360,1559487600"; d="scan'208";a="23432816" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 08 Aug 2019 15:20:25 +0900 Received: from localhost.localdomain (unknown [10.166.17.210]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5E89541CA0B5; Thu, 8 Aug 2019 15:20:25 +0900 (JST) From: Yoshihiro Shimoda To: linus.walleij@linaro.org, geert+renesas@glider.be Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 2/3] pinctrl: sh-pfc: remove incomplete flag "cfg->type" Date: Thu, 8 Aug 2019 15:19:02 +0900 Message-Id: <1565245143-15018-3-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565245143-15018-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1565245143-15018-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The old commit c58d9c1b26e3 ("sh-pfc: Implement generic pinconf support") broke the cfg->type flag to PINMUX_TYPE_FUNCTION because sh_pfc_pinconf_set() didn't call sh_pfc_reconfig_pin(). Now if we fix the cfg->type condition, it gets worse because: - Some drivers might be deferred so that .set_mux() will be called multiple times. - In such the case, the sh-pfc driver returns -EBUSY even if the group is the same, and then that driver fails to probe. Since the pinctrl subsystem already has such conditions according to @set_mux and @gpio_request_enable, this patch just remove the incomplete flag from sh-pfc/pinctrl.c. Fixes: c58d9c1b26e3 ("sh-pfc: Implement generic pinconf support") Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- drivers/pinctrl/sh-pfc/pinctrl.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 864da24..ab2aa93 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -26,7 +26,6 @@ #include "../pinconf.h" struct sh_pfc_pin_config { - u32 type; bool mux_set; bool gpio_enabled; }; @@ -354,16 +353,6 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, spin_lock_irqsave(&pfc->lock, flags); for (i = 0; i < grp->nr_pins; ++i) { - int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - - if (cfg->type != PINMUX_TYPE_NONE) { - ret = -EBUSY; - goto done; - } - } - - for (i = 0; i < grp->nr_pins; ++i) { ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) goto done; @@ -395,14 +384,6 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - if (cfg->type != PINMUX_TYPE_NONE) { - dev_err(pfc->dev, - "Pin %u is busy, can't configure it as GPIO.\n", - offset); - ret = -EBUSY; - goto done; - } - if (!pfc->gpio) { /* If GPIOs are handled externally the pin mux type need to be * set to GPIO here. @@ -414,7 +395,6 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, goto done; } - cfg->type = PINMUX_TYPE_GPIO; cfg->gpio_enabled = true; ret = 0; @@ -436,7 +416,6 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, unsigned long flags; spin_lock_irqsave(&pfc->lock, flags); - cfg->type = PINMUX_TYPE_NONE; cfg->gpio_enabled = false; spin_unlock_irqrestore(&pfc->lock, flags); } @@ -450,7 +429,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; int idx = sh_pfc_get_pin_index(pfc, offset); const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; unsigned int dir; int ret; @@ -470,8 +448,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, if (ret < 0) goto done; - cfg->type = new_type; - done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; @@ -794,13 +770,11 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) for (i = 0; i < pfc->info->nr_pins; ++i) { const struct sh_pfc_pin *info = &pfc->info->pins[i]; - struct sh_pfc_pin_config *cfg = &pmx->configs[i]; struct pinctrl_pin_desc *pin = &pmx->pins[i]; /* If the pin number is equal to -1 all pins are considered */ pin->number = info->pin != (u16)-1 ? info->pin : i; pin->name = info->name; - cfg->type = PINMUX_TYPE_NONE; } return 0; From patchwork Thu Aug 8 06:19:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1143846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 463ysp4dLLz9sP3 for ; Thu, 8 Aug 2019 16:20:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731151AbfHHGU3 (ORCPT ); Thu, 8 Aug 2019 02:20:29 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:30299 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731147AbfHHGU3 (ORCPT ); Thu, 8 Aug 2019 02:20:29 -0400 X-IronPort-AV: E=Sophos;i="5.64,360,1559487600"; d="scan'208";a="23652846" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 08 Aug 2019 15:20:25 +0900 Received: from localhost.localdomain (unknown [10.166.17.210]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6BEBD41CA0B9; Thu, 8 Aug 2019 15:20:25 +0900 (JST) From: Yoshihiro Shimoda To: linus.walleij@linaro.org, geert+renesas@glider.be Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 3/3] pinctrl: sh-pfc: Rollback to mux if requires when the gpio is freed Date: Thu, 8 Aug 2019 15:19:03 +0900 Message-Id: <1565245143-15018-4-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565245143-15018-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1565245143-15018-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org R-Car PWM controller requires the gpio to output zero duty, this patch allows to roll it back from gpio to mux when the gpio is freed. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- drivers/pinctrl/sh-pfc/pinctrl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index ab2aa93..c9bdca5 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -26,6 +26,7 @@ #include "../pinconf.h" struct sh_pfc_pin_config { + unsigned int mux_mark; bool mux_set; bool gpio_enabled; }; @@ -353,6 +354,16 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, spin_lock_irqsave(&pfc->lock, flags); for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + /* + * This driver cannot manage both gpio and mux when the gpio + * pin is already enabled. So, this function failed. + */ + if (cfg->gpio_enabled) + return -EBUSY; + ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) goto done; @@ -364,6 +375,7 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; cfg->mux_set = true; + cfg->mux_mark = grp->mux[i]; } done: @@ -417,6 +429,9 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); cfg->gpio_enabled = false; + /* If mux is already set, this configures it here */ + if (cfg->mux_set) + sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); spin_unlock_irqrestore(&pfc->lock, flags); }