From patchwork Sun Aug 4 17:23:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141812 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="H6HNSIHI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 461npJ5y05z9sMr for ; Mon, 5 Aug 2019 03:24:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6A192C21D8E; Sun, 4 Aug 2019 17:24:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1747BC21D65; Sun, 4 Aug 2019 17:24:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 73A92C21D83; Sun, 4 Aug 2019 17:24:21 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id D9894C21C51 for ; Sun, 4 Aug 2019 17:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939441; bh=LNSkSBfAEc6wPGEU0YLiKKmmWssKDA2Us1Jou9ICXE8=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=H6HNSIHIsfhkhYCF5QylpOawNy8D2y9CxYBNlv8eqyj2S1EBSnQ5r+7deO8zUNQa+ Xi4/HoC/p/LOKyVjuhmoCIsqpD1FFlyt+xpagLQXMd3ZqxanVmhPmgOvEG348D4iWm 5FzOXL7pd3+btL3N8VvrJyDapYkZj3SR+h/UcMmo= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0Lu7ty-1iJJOp01n4-011Pd7; Sun, 04 Aug 2019 19:24:01 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:37 +0200 Message-Id: <20190804172342.5225-2-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:rrZE51PNbtXT3ri8Ue2IaK/pRfAl/nBcIvcx/pdq44goFehotA1 cnlRzV43C5rjWzN3GO6e+Ztg2xDunvae9987oKdeP29ASqSuSmiGJiW8PuCR054VerUrT9A a3HGpqiuHDXSSsI5RPycjB/AVFeF9FYekD/gp2nMjOMrhkXfhs0scWhpd3mY4kKkPEdqyHp LsFR5oNvUSxJEEI+XnWaw== X-UI-Out-Filterresults: notjunk:1; V03:K0:vt4UiGpHFbU=:zY17w9qzJ7Xr1pNZwnTxAK 00CqTSBNhyNzufSf+DsJCvRwprfrRqGwgzPGqnD9sm8RhMzbutxfkkn602VEaWDwhBGPhwlgj A60fVNjUDalz0M0b8yFxlcEmRwvvfeUdeLgdjEqvBPKhS524nDJr4y7s7c1WIxmULUbLekvQe +kHo4huxcoDBELnXsXpARdqKUOOmXVaxxcsD5watw9v8owIyYyDb4ZyC6M343PO9XcMFb72Ir ZAkMkstP7KDbW9ibeEKT5Q/1KlcH8tt9yyntMVkdtl2ZAgxcdsUCH2++PPSua0FDYo1nEN+E4 cHykaFFI17QUhoyoifwINKLvtu7TDJz/tXGLOk3u0qS1kXKJW1auOtRFcp5FiUkERrY7Qy8Uk PqO9t/YfTtTERuoHZbqzR0Ir7FT7Q/5QqI0hCN/EDEZwKlXAzzYBGm+jon0DzdbOY/rUJ8MOQ NnrRdDbICLiaORfQvFV35OzEHosTxhSONllDWz2Nv3SBzCzZgMQwcgK3mGlx5bkcQDiJQORWN cnaT6vh102Z37vepeXZDVqSq1Sngck3yFhvXthkYeE2xWugczCPd0D99JVFXg864+dsadF0Uo 9g5btWnfLhrlTHRKVUk61aEeDFz2jg1hqMc2cZ/NfFDIp40ZicBEHS+1iKRXN9Y3upQmM5H0W zjL7DYvpCJH+SHZPzJv0C9H8Lx572dHkJHqZVjg8NaEKs0mNKRNCxaT+tSBh2WDrtHJ591Zsg 2XmjBCO3PEY8o6cWXLCdy64+hDG1aJji5nSQHwHEqo7Pq2+eVSYGPA4LbblLUXbFxGy5Dq/Au gbiJdc6Z7+Uo9EpXGtiaWjRh4Y6IUR1bSmlDPAmAVVzeFTCwQFeSvG0NR3wYqP98vITlW6n4C RbeddLNMdLH/PBmV3AWTle1QBPows5FG9s/7cfvFwR8xLi59LR7z1BjZfrINLeh9Lh8epz7AK v7GKFULfj0s52mNcCxfQMS9jTKOxtvoClm9Q2A5Py+f32SF8cAi86ebA6G5c0k3spmc973hNc 1bINdp4PNhDvlxFZsgejqhUCZAINrac68i1+a95qDm8Z9Dk7kZASxTWDuomp56hZlHUJGFkAC Iam009znkzyVEO2hB6P1ETYcR0xIWWNIJEL37eLfDVFA92O4srNlR5EWA== Subject: [U-Boot] [PATCH v2 1/6] pci: mediatek: add PCIe controller support for MT7623 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds PCIe controller support for MT7623. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Ryder Lee --- drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_mediatek.c | 292 ++++++++++++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 drivers/pci/pcie_mediatek.c -- 2.17.1 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 3fe38f7315..6f19471ae7 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -145,4 +145,12 @@ config PCI_MVEBU Say Y here if you want to enable PCIe controller support on Armada XP/38x SoCs. +config PCIE_MEDIATEK + bool "MediaTek PCIe controller" + depends on DM_PCI + depends on ARCH_MEDIATEK + help + Say Y here if you want to enable PCIe controller support on + MediaTek SoCs. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index b5ebd50c85..7093d63918 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ pcie_layerscape_gen4_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o +obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c new file mode 100644 index 0000000000..3f24060d26 --- /dev/null +++ b/drivers/pci/pcie_mediatek.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek PCIe host controller driver. + * + * Copyright (c) 2017-2019 MediaTek Inc. + * Author: Ryder Lee + * Honghui Zhang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCIe shared registers */ +#define PCIE_SYS_CFG 0x00 +#define PCIE_INT_ENABLE 0x0c +#define PCIE_CFG_ADDR 0x20 +#define PCIE_CFG_DATA 0x24 + +/* PCIe per port registers */ +#define PCIE_BAR0_SETUP 0x10 +#define PCIE_CLASS 0x34 +#define PCIE_LINK_STATUS 0x50 + +#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) +#define PCIE_PORT_PERST(x) BIT(1 + (x)) +#define PCIE_PORT_LINKUP BIT(0) +#define PCIE_BAR_MAP_MAX GENMASK(31, 16) + +#define PCIE_BAR_ENABLE BIT(0) +#define PCIE_REVISION_ID BIT(0) +#define PCIE_CLASS_CODE (0x60400 << 8) +#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ + ((((regn) >> 8) & GENMASK(3, 0)) << 24)) +#define PCIE_CONF_ADDR(regn, bdf) \ + (PCIE_CONF_REG(regn) | (bdf)) + +/* MediaTek specific configuration registers */ +#define PCIE_FTS_NUM 0x70c +#define PCIE_FTS_NUM_MASK GENMASK(15, 8) +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) + +#define PCIE_FC_CREDIT 0x73c +#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) +#define PCIE_FC_CREDIT_VAL(x) ((x) << 16) + +struct mtk_pcie_port { + void __iomem *base; + struct list_head list; + struct mtk_pcie *pcie; + struct reset_ctl reset; + struct clk sys_ck; + struct phy phy; + u32 slot; +}; + +struct mtk_pcie { + void __iomem *base; + struct clk free_ck; + struct list_head ports; +}; + +static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct mtk_pcie *pcie = dev_get_priv(udev); + + writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); + + return 0; +} + +static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, mtk_pcie_config_address, + bdf, offset, valuep, size); +} + +static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, mtk_pcie_config_address, + bdf, offset, value, size); +} + +static const struct dm_pci_ops mtk_pcie_ops = { + .read_config = mtk_pcie_read_config, + .write_config = mtk_pcie_write_config, +}; + +static void mtk_pcie_port_free(struct mtk_pcie_port *port) +{ + list_del(&port->list); + free(port); +} + +static int mtk_pcie_startup_port(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie = port->pcie; + u32 slot = PCI_DEV(port->slot << 11); + u32 val; + int err; + + /* assert port PERST_N */ + val = readl(pcie->base + PCIE_SYS_CFG); + val |= PCIE_PORT_PERST(port->slot); + writel(val, pcie->base + PCIE_SYS_CFG); + + /* de-assert port PERST_N */ + val = readl(pcie->base + PCIE_SYS_CFG); + val &= ~PCIE_PORT_PERST(port->slot); + writel(val, pcie->base + PCIE_SYS_CFG); + + /* 100ms timeout value should be enough for Gen1/2 training */ + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, + !!(val & PCIE_PORT_LINKUP), 100000); + if (err) + return -ETIMEDOUT; + + /* disable interrupt */ + val = readl(pcie->base + PCIE_INT_ENABLE); + val &= ~PCIE_PORT_INT_EN(port->slot); + writel(val, pcie->base + PCIE_INT_ENABLE); + + /* map to all DDR region. We need to set it before cfg operation. */ + writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, + port->base + PCIE_BAR0_SETUP); + + /* configure class code and revision ID */ + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); + + /* configure FC credit */ + writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), + pcie->base + PCIE_CFG_ADDR); + val = readl(pcie->base + PCIE_CFG_DATA); + val &= ~PCIE_FC_CREDIT_MASK; + val |= PCIE_FC_CREDIT_VAL(0x806c); + writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), + pcie->base + PCIE_CFG_ADDR); + writel(val, pcie->base + PCIE_CFG_DATA); + + /* configure RC FTS number to 250 when it leaves L0s */ + writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + val = readl(pcie->base + PCIE_CFG_DATA); + val &= ~PCIE_FTS_NUM_MASK; + val |= PCIE_FTS_NUM_L0(0x50); + writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + writel(val, pcie->base + PCIE_CFG_DATA); + + return 0; +} + +static void mtk_pcie_enable_port(struct mtk_pcie_port *port) +{ + int err; + + err = clk_enable(&port->sys_ck); + if (err) + goto exit; + + err = reset_assert(&port->reset); + if (err) + goto exit; + + err = reset_deassert(&port->reset); + if (err) + goto exit; + + err = generic_phy_init(&port->phy); + if (err) + goto exit; + + err = generic_phy_power_on(&port->phy); + if (err) + goto exit; + + if (!mtk_pcie_startup_port(port)) + return; + + pr_err("Port%d link down\n", port->slot); +exit: + mtk_pcie_port_free(port); +} + +static int mtk_pcie_parse_port(struct udevice *dev, u32 slot) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port; + char name[10]; + int err; + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + snprintf(name, sizeof(name), "port%d", slot); + port->base = dev_remap_addr_name(dev, name); + if (!port->base) + return -ENOENT; + + snprintf(name, sizeof(name), "sys_ck%d", slot); + err = clk_get_by_name(dev, name, &port->sys_ck); + if (err) + return err; + + err = reset_get_by_index(dev, slot, &port->reset); + if (err) + return err; + + err = generic_phy_get_by_index(dev, slot, &port->phy); + if (err) + return err; + + port->slot = slot; + port->pcie = pcie; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int mtk_pcie_probe(struct udevice *dev) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port, *tmp; + ofnode subnode; + int err; + + INIT_LIST_HEAD(&pcie->ports); + + pcie->base = dev_remap_addr_name(dev, "subsys"); + if (!pcie->base) + return -ENOENT; + + err = clk_get_by_name(dev, "free_ck", &pcie->free_ck); + if (err) + return err; + + /* enable top level clock */ + err = clk_enable(&pcie->free_ck); + if (err) + return err; + + dev_for_each_subnode(subnode, dev) { + struct fdt_pci_addr addr; + u32 slot = 0; + + if (!ofnode_is_available(subnode)) + continue; + + err = ofnode_read_pci_addr(subnode, 0, "reg", &addr); + if (err) + return err; + + slot = PCI_DEV(addr.phys_hi); + + err = mtk_pcie_parse_port(dev, slot); + if (err) + return err; + } + + /* enable each port, and then check link status */ + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + mtk_pcie_enable_port(port); + + return 0; +} + +static const struct udevice_id mtk_pcie_ids[] = { + { .compatible = "mediatek,mt7623-pcie", }, + { } +}; + +U_BOOT_DRIVER(pcie_mediatek) = { + .name = "pcie_mediatek", + .id = UCLASS_PCI, + .of_match = mtk_pcie_ids, + .ops = &mtk_pcie_ops, + .probe = mtk_pcie_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pcie), +}; From patchwork Sun Aug 4 17:23:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141815 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Sun, 4 Aug 2019 17:24:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939442; bh=I6b8s5auITPMbmv+bDy6BzX11CQ1cVnUSYE8RxHxh2s=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=lqxWY24w0il5OMun9eR2Mv1enUnEtQZLNhCm880cP4DA1FpWKUg2abhH2XzbClKGl DsBPkort7hbtFaD0qcPo+TNJHCufMOe0ZbmBcc5taN/qDBurNR7/YcC2zF2WhztwEB 7t/5FLrWq9HaT3HKaxnytkVDFiyMIIbAN340u7VM= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0LzKQf-1iP4YV2FeL-014QAk; Sun, 04 Aug 2019 19:24:02 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:38 +0200 Message-Id: <20190804172342.5225-3-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:HFxjuGph+D+Errcj4o3pl1c/4IkJm950tL+ZgjmIfU8GjQDXuPf kJTAOTlkDusK+LQBysffvaR2AE4Jino2Z963COWeMrP/XzkIb89fEvSYTpRAeYJ7M3hlKe6 Gsgzwo3WBFb85ON6yeLNlkmwfcUXAzic79KlsL0UEJGH4e6Z6wodwipDPEbyhClOrvCqMQQ YBU9OMMIi1vhk4hKUeTIw== X-UI-Out-Filterresults: notjunk:1; V03:K0:JxkFsnl+o4k=:1HNkZ8VECjWL8+wugvVzQ8 0/4VE3QcETZX3/+5VABErBOeGF/OB6sEjsbWjOIF4PQf2A8Z3SZxvyDR4CgZsenZomxtyV603 WsKM1FeLctwHOAvI3TCwVfU35jJ27wuutVd7QhCzOCOTuuNuUWL9UTkInG+v73XsB+s0+wl1Q r09YVKzLT/3b7T1P8leUNwO6VdiJXB2Xkqgh6Me4r6c2m8b0ALxU5Mwo3B7Ca/Br2f5tN02xP 1RSogiPrAwZi18gQpkzBUZzMst3BhfV4RrbTTM2g0wdS2x5l4y+WVADNF/jzqAU6RX0sV6zse qAq7lRFQxBQiDcF8PViAgEeqzjmSwCFTPdpecFBtDJlk2AlZTQ/av8X4DNar7+rS57S/e7hcM vd0duesBXz4My54293b4VD7FnEguzzbd4Vmx7DCOdSj23n3/cD7nUr/b21N+KZVD7kMgRsYqe s9DniUBvMlW3z2RfY4Rf/cBMESzIO0vBJrCJ2oQaJdCoAAjFKpTXpky4LvlKbmt3xaGata+L+ CRz4arKOKpDyn5nbN1QdVvhdhqW4jkC4NFba32pfq++b1Ctd5WahQgdHqZxWWYbKBBN8s9G6B hlGMoQY2r/Di02Ow794jBBO/IMCygs6xQCxFM7OEH0u4aGpnRd/pEKxlo3gVu1dsUAb0F/UUy zdo+hFRutDoMzo3sDNPfLH33lXSOLfohBBHTV8V+MCGcH0wDYo85TEERLYbqBRDfQDX3p+11r nIx1d0kvczcmK4PiQT+4NodDz0/RWsPPazWWMBLWju/GRBlUTRDd6T8Bem+Gh6Q10cZI7FtGX CFMBjaWioBnaaj100GDGwJlr9Y0PFvtidABlPWVPqC+9pMvH8AZXsmkMK5QvnRYbWBsLSPpsR 4bMoiFMGQqVFxLf1hF1HwPG6vNHWo+Mb+piLiJXewnXxrEln74+Nrr56AkqznZXloEnXIB69P rPiTHfrXsk6ohqDSDU05K3dK40pb9QmWccIII/Zr0Q8MaQXjOuyJVrRmILkNOHtRXU3nqPw2q /HHTPcZuxlEeEjEwN2R3V/ZqpLX0JZnlvoWozQKXpbwj4/oELxGBd6ErlnegBB3sDLRkMJ3Y8 KUAEkjkCno0vFgIdHCPfO1TsH5TZdqggprvtGOEGpT6lHgoTq6v0wL36w== Subject: [U-Boot] [PATCH v2 2/6] phy: mediatek: add MediaTek T-PHY support for PCIe X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Ryder Lee --- drivers/phy/Kconfig | 11 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-mtk-tphy.c | 388 +++++++++++++++++++++++++++++++++++++ 3 files changed, 400 insertions(+) create mode 100644 drivers/phy/phy-mtk-tphy.c -- 2.17.1 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 957efb3984..2099dd9547 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -190,4 +190,15 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config PHY_MTK_TPHY + bool "MediaTek T-PHY Driver" + depends on PHY + depends on ARCH_MEDIATEK + help + MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and + SATA, and meanwhile supports two version T-PHY which have + different banks layout, the T-PHY with shared banks between + multi-ports is first version, otherwise is second veriosn, + so you can easily distinguish them by banks layout. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 90646ca55b..15b4d58a2d 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o +obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c new file mode 100644 index 0000000000..422e727c22 --- /dev/null +++ b/drivers/phy/phy-mtk-tphy.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 - 2019 MediaTek Inc. + * Author: Chunfeng Yun + * Ryder Lee + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* version V1 sub-banks offset base address */ +/* banks shared by multiple phys */ +#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ +#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ +/* u3/pcie/sata phy banks */ +#define SSUSB_SIFSLV_V1_U3PHYD 0x000 +#define SSUSB_SIFSLV_V1_U3PHYA 0x200 + +#define U3P_U3_CHIP_GPIO_CTLD 0x0c +#define P3C_REG_IP_SW_RST BIT(31) +#define P3C_MCU_BUS_CK_GATE_EN BIT(30) +#define P3C_FORCE_IP_SW_RST BIT(29) + +#define U3P_U3_CHIP_GPIO_CTLE 0x10 +#define P3C_RG_SWRST_U3_PHYD BIT(25) +#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) + +#define U3P_U3_PHYA_REG0 0x000 +#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) +#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) + +#define U3P_U3_PHYA_REG1 0x004 +#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) +#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) + +#define U3P_U3_PHYA_DA_REG0 0x100 +#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) +#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) +#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) +#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) +#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) + +#define U3P_U3_PHYA_DA_REG4 0x108 +#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) +#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) +#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) + +#define U3P_U3_PHYA_DA_REG5 0x10c +#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) +#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) +#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) +#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) + +#define U3P_U3_PHYA_DA_REG6 0x110 +#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG7 0x114 +#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG20 0x13c +#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) +#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG25 0x148 +#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) +#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) + +#define U3P_U3_PHYD_RXDET1 0x128 +#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) +#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) + +#define U3P_U3_PHYD_RXDET2 0x12c +#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) +#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) + +struct u3phy_banks { + void __iomem *spllc; + void __iomem *chip; + void __iomem *phyd; /* include u3phyd_bank2 */ + void __iomem *phya; /* include u3phya_da */ +}; + +struct mtk_phy_instance { + void __iomem *port_base; + const struct device_node *np; + + struct u3phy_banks u3_banks; + + /* reference clock of anolog phy */ + struct clk ref_clk; + u32 index; + u8 type; +}; + +struct mtk_tphy { + void __iomem *sif_base; + struct mtk_phy_instance **phys; + int nphys; +}; + +static void pcie_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + u32 tmp; + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); + tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); + tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); + + /* ref clk drive */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); + tmp &= ~P3A_RG_CLKDRV_AMP; + tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); + tmp &= ~P3A_RG_CLKDRV_OFF; + tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); + + /* SSC delta -5000ppm */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); + tmp &= ~P3A_RG_PLL_DELTA1_PE2H; + tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); + tmp &= ~P3A_RG_PLL_DELTA_PE2H; + tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); + + /* change pll BW 0.6M */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); + tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); + tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); + tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); + tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); + tmp &= ~P3A_RG_PLL_IR_PE2H; + tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); + tmp &= ~P3A_RG_PLL_BP_PE2H; + tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); + + /* Tx Detect Rx Timing: 10us -> 5us */ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); + tmp &= ~P3D_RG_RXDET_STB2_SET; + tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); + tmp &= ~P3D_RG_RXDET_STB2_SET_P3; + tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); + + /* wait for PCIe subsys register to active */ + udelay(3000); +} + +static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *bank = &instance->u3_banks; + u32 tmp; + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); + tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); + tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); +} + +static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + +{ + struct u3phy_banks *bank = &instance->u3_banks; + u32 tmp; + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); + tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); + tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); +} + +static void phy_v1_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_PCIE: + u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; + u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; + break; + default: + return; + } +} + +static int mtk_phy_init(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + int ret; + + /* we may use a fixed-clock here */ + ret = clk_enable(&instance->ref_clk); + if (ret && ret != -ENOSYS) + return ret; + + switch (instance->type) { + case PHY_TYPE_PCIE: + pcie_phy_instance_init(tphy, instance); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_phy_power_on(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + pcie_phy_instance_power_on(tphy, instance); + + return 0; +} + +static int mtk_phy_power_off(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + pcie_phy_instance_power_off(tphy, instance); + + return 0; +} + +static int mtk_phy_exit(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + clk_disable(&instance->ref_clk); + + return 0; +} + +static int mtk_phy_xlate(struct phy *phy, + struct ofnode_phandle_args *args) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = NULL; + const struct device_node *phy_np = ofnode_to_np(args->node); + u32 index; + + if (!phy_np) { + dev_err(phy->dev, "null pointer phy node\n"); + return -EINVAL; + } + + if (args->args_count < 1) { + dev_err(phy->dev, "invalid number of cells in 'phy' property\n"); + return -EINVAL; + } + + for (index = 0; index < tphy->nphys; index++) + if (phy_np == tphy->phys[index]->np) { + instance = tphy->phys[index]; + break; + } + + if (!instance) { + dev_err(phy->dev, "failed to find appropriate phy\n"); + return -EINVAL; + } + + phy->id = index; + instance->type = args->args[1]; + if (!(instance->type == PHY_TYPE_USB2 || + instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_PCIE || + instance->type == PHY_TYPE_SATA)) { + dev_err(phy->dev, "unsupported device type\n"); + return -EINVAL; + } + + phy_v1_banks_init(tphy, instance); + + return 0; +} + +static const struct phy_ops mtk_tphy_ops = { + .init = mtk_phy_init, + .exit = mtk_phy_exit, + .power_on = mtk_phy_power_on, + .power_off = mtk_phy_power_off, + .of_xlate = mtk_phy_xlate, +}; + +static int mtk_tphy_probe(struct udevice *dev) +{ + struct mtk_tphy *tphy = dev_get_priv(dev); + ofnode subnode; + int index = 0; + + dev_for_each_subnode(subnode, dev) + tphy->nphys++; + + tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys), + GFP_KERNEL); + if (!tphy->phys) + return -ENOMEM; + + tphy->sif_base = dev_read_addr_ptr(dev); + if (!tphy->sif_base) + return -ENOENT; + + dev_for_each_subnode(subnode, dev) { + struct mtk_phy_instance *instance; + fdt_addr_t addr; + int err; + + instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); + if (!instance) + return -ENOMEM; + + addr = ofnode_get_addr(subnode); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + instance->port_base = map_sysmem(addr, 0); + instance->index = index; + instance->np = ofnode_to_np(subnode); + tphy->phys[index] = instance; + index++; + + err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk); + if (err) + return err; + } + + return 0; +} + +static const struct udevice_id mtk_tphy_id_table[] = { + { .compatible = "mediatek,generic-tphy-v1", }, + { } +}; + +U_BOOT_DRIVER(mtk_tphy) = { + .name = "mtk-tphy", + .id = UCLASS_PHY, + .of_match = mtk_tphy_id_table, + .ops = &mtk_tphy_ops, + .probe = mtk_tphy_probe, + .priv_auto_alloc_size = sizeof(struct mtk_tphy), +}; From patchwork Sun Aug 4 17:23:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141817 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="EiVkBArX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 461ns26dNZz9sMr for ; Mon, 5 Aug 2019 03:27:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A432BC21DCA; Sun, 4 Aug 2019 17:25:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A6B26C21E08; Sun, 4 Aug 2019 17:25:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4E4B1C21DFD; Sun, 4 Aug 2019 17:24:38 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lists.denx.de (Postfix) with ESMTPS id D077AC21E18 for ; Sun, 4 Aug 2019 17:24:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939444; bh=fUI0hYG88ARs2nUIjumiLMHryqThJg+zR291mNfBy0I=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=EiVkBArX+4tuTMcFfARoK9ptx84F8XLR5KgxFjLginjN0L2CBZHx2uoq8TfK+DNvJ VPGKgQiEWRyibbz8IlpC3kpgJugOurPjU5YipbmmyUV2y1gw4Yr9JzVt20WpFPchWe 3qVjtn3e7Ab+Owzm56GMdw2axMIbKNk2/I/XH2PY= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MY75A-1hq0mp3Y8G-00UoN9; Sun, 04 Aug 2019 19:24:04 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:39 +0200 Message-Id: <20190804172342.5225-4-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:sorMS/NEG3tNj9Bclr1oNajG9Qe0rnIWWRELIwUSC79DguvvMY/ Cn83dF9KB9kUoNG10rKUtT7ZO3Qwn6bDKKSQK+oOqAIkaEKeMW9Hvq0evyB57S2BRjXuj+X 6sWZDU7NRmxy9binZ/+VdhlKz26pJNQi00q1+qdJHDhzuMx0NxvW6eZBNaewGUfR9vklKhQ 2s2v3eypiYZr5v7bRjp7A== X-UI-Out-Filterresults: notjunk:1; V03:K0:RWGLY8KFp+I=:OnOLuYth4cADz8ROc6Cmij hXTJe69OGsY+JbCXXGhGE6GdAQzHTtip8fSw0wmFmyJADl488RvY2dB5a1dR64EzsRrKCWS3B lfsJGWNIDyxaJBIkznkepcOtAJmWj3/EM53eHDArRw2dNqYP0OhkZKdD8g42cqjcGAf8YYZYL A2f+WgkZjSas+1UWkLgJSfSnHWjFWYkH462oh3MwzanWhILeeq/zcjLOt33R8zUeigEWcgd9D RXkaOWXKX2ujceiFWOPqo+DEyWURoywbVMt8zXTkkjYCXYV8JqjG3P9qNssK8iU2FRas3VsRF IBu6QhhVCt9Ao4sV2zgrstU9QUT0Gd+uiHAPx6hrhdvyWqP4RrBwsGTtgsdPj0WKy2T3E0D0q EmzEYpBpoVFr7ThFBmKMHjTIakgxqZKB98R/WKCbIGOjtQiz+0kwFwdszbDWlveq6EVepy+R2 jHhujRNvXwGB4k6zfY6zkauXca4KqbcQmAXE05TzDrZ0jVjU4nntja+vTrJoGKNYZe7g18f56 920G1mFEe/WpRdD9dNRlhCHZmF+/Enp12BbLk3A/S6WIqeMECqH31cNkcVqBv7kuYP1HMi6L5 sc3XhcTIzWsYkUA4Av6ppVP58fea0lwKvXMWUT3IfVra2F2tW9I1bJTFsRH+4uZ8AZYrB3S25 y5od9QxEImhfs75PNZiLZPBZKAu6WTXgbhg68WRieM8eiekCSQXuQ/uLw/W6OAhlJcJCs0Wtk 3XSsabz3AHSyoctIy40tX8wtWqqn4XuQuAS5STQrVZ3bxyJLAHsXIoV92Q9/PZ0LMje2lREWP HpVi7McglGugZVh2quSGDFEaSV4n3ui71NE+Sp1JrdLCD16S45n4OGHGYhB2P6V3bLXyPZTo8 xc0rRcReM+u07Z3WuBSoftsgQ6y2F87d+K/Kr+ZlcNpBTVuPKVtXpuY1undER5Sqa81QxSiyF bOhcaTLxcO1qARJKHGym0KHZ/ek8HRl0IIbx3mSufxk4p/sJ6dTpV1Mt5apZulbYeDOshP2Fu C5rKATFpD2D9oGmU3pK5MImfR4GcZumy1zD3uUHYvf++iaXSGxusHsDTZ3kBgyvRWxHk9X6xg Dm5JV5HCwiHNSCroiV/hOdG1WbD+uc9p7awUQZsuI7EgPniH/ceTmc6uA== Subject: [U-Boot] [PATCH v2 3/6] arm: dts: add PCIe controller for MT7623 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds PCIe and its PHY nodes for MT7623. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Ryder Lee --- arch/arm/dts/mt7623.dtsi | 128 +++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 29 +++++ 2 files changed, 157 insertions(+) -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 64079c61bf..3a868ea2ee 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "skeleton.dtsi" @@ -255,6 +256,133 @@ #reset-cells = <1>; }; + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0x1a149900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0x1a14a900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index 51628bb639..b0c86219b6 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -172,6 +172,13 @@ }; }; + pcie_default: pcie-default { + mux { + function = "pcie"; + groups = "pcie0_0_perst", "pcie1_0_perst"; + }; + }; + uart0_pins_a: uart0-default { mux { function = "uart"; @@ -201,6 +208,28 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From patchwork Sun Aug 4 17:23:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141816 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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Sun, 4 Aug 2019 17:24:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939445; bh=MQC4bhU7TnVA5Fa449T8MyVyw+e4tcmSvMapt5aJR3o=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=cW2HteaVeu1VJEY6VdKPAL7xlrykWe+ZV1zZ00WU8X3DqdFvTabY9uwJKbOgVFwNI iu5MhipvN0QmOtOnE2EOAXzLH6rHT5rgJQFMu1Ju82dF5x2E2NSqiYSdYW6ukxlvjw EcoDBsOdoKd9qj2NrkhQymcWdwCmcOpsNM1V2NTk= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0LeNGL-1ihhs00Dtt-00qB4w; Sun, 04 Aug 2019 19:24:05 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:40 +0200 Message-Id: <20190804172342.5225-5-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:YZIcn/BfPUj5VFQJBj0RAJV4MtPVsNAfMmN+8Lh0rwnt4AvCKi9 KIqYAoBDZi3ZKqticBL0VEze24LjuBoDiA2rUSEygobhOsd+JDMRU9Et3uEdbYDvlJNXxu/ PVHNWqudtBtoCa1iufLXJJMJhlCgjcfIiMgFjZyBhkzzIqB7I1gk8q7RO7mGMpjZJpfLgMf 78OnRnSw6Qo00IubQaeWA== X-UI-Out-Filterresults: notjunk:1; V03:K0:p5W4eV9mViU=:zw51zTR5yAyzn3ppO+3Vau 7kFX0h1pp7oLuBD1kMGBjMEw4XGuO8VoPHvNmLQtturnLFO9ALqEzzVqiN+0PwcqN2Ybaj7tc hDerD4geZZ04F/yB4CorjVmnI+jQdv1cqdxIWCKHOS2JPFaOwzLRmTpA8/gm5DFkb5vs1JaqZ Gg+ZvnfmU6p4nghmRMYM8+9CkhPjj9dSlWi/yRmC2T2IiAXugGafP99+Ojxkm0YZug3fmRkk9 E1ZGPBhJYQcv4e4sCE0Oh7ohAlhL3Ok5fPtzQayaAGsneUv3Y7LJgTJYRnM9Ye8P1je+ewO3W 9yX9nJ10EgJAyQpdMvFUGIb2QoYy8zJrDU/ERg3PJ6tjaB3S7zENhESPEIK0mWtoCEI4KyhBT 9Ux2d7RbheSa9IlJxAbVS734uUyWRClwNogh4cjyqLJUU+yy0fzDYKYKPQsiuHjtVXQLu6EEn GBS2ymfpcCg3Qd00d+NfXxhK/c81QyYmybFv+hIXRi26L1drN6lX3lp8U/9oPLm4hemW7X1e4 jSnxEoilkuGUUQLUtrADojzIAvHfk+myke0YLnf4lqS7ycrT2TMpVx7BXAjUYyqly9sHaUBff eCBIvp+ueNq+Ux3uv6naiQf+6D5WyUSb9jk4ZORKS+7UA4bCWVNXtfdmOd8iB2sn0RKWDai93 IENLhhD6aaBevnjwUkA5PNfJPRZ++a4WkUdrGql0Jw+6il7vXr+VAVIhIzgjjcZAje6pmJpc0 GEXhJxM/lkWruVuOY+i5GiKpjsBBNuIpNrZCiCG/bS83Ut8RartYefz8khHdoxxpqUIsJcVUj q2ivoGsJ7ZjyG7vXhLIbGvQ5unIdxpSOp6ax6WoYjvlAD8jn/zaoQWiAx+C8RwuCZHRLGcjmb 2M0ph4qPTqu7Hm2Rc/BeRuzjUay4PuF8C5BJ+yZTCihqQYr8xg//4KWHFLy3ca6/NUJW0V65z 8Q/h8t3tU2vaQ79lSHa7p9KWgyt12X0kx4zJ1UI1rCvyNMnM9UJt/B7CKNKDecbzQ4qkdHPEn 7Vbx7W/yg0rdCObCG3Sl3YEbGha/Id3JSKpr8gOIZu5npD9yN+igXxVov6G/7VOgjneHbytqU O3+kNko7KiG/Hy/nLUvrKi1+dGd2OTqVPhPf+IVoMi5Mjv7lI/tjfMIVQ== Subject: [U-Boot] [PATCH v2 4/6] arm: dts: split mtk-reset.h into per-chip header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Ryder Lee --- arch/arm/dts/mt7623.dtsi | 2 +- arch/arm/dts/mt7629.dtsi | 2 +- .../reset/{mtk-reset.h => mt7623-reset.h} | 4 +-- include/dt-bindings/reset/mt7629-reset.h | 36 +++++++++++++++++++ 4 files changed, 39 insertions(+), 5 deletions(-) rename include/dt-bindings/reset/{mtk-reset.h => mt7623-reset.h} (88%) create mode 100644 include/dt-bindings/reset/mt7629-reset.h -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 3a868ea2ee..1135b1e1ae 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index ecbd29d7ae..3c9eab9770 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mt7623-reset.h similarity index 88% rename from include/dt-bindings/reset/mtk-reset.h rename to include/dt-bindings/reset/mt7623-reset.h index 78fcdab009..a859a5b26a 100644 --- a/include/dt-bindings/reset/mtk-reset.h +++ b/include/dt-bindings/reset/mt7623-reset.h @@ -6,11 +6,9 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* ETHSYS */ +/* ETHSYS resets */ #define ETHSYS_PPE_RST 31 -#define ETHSYS_EPHY_RST 24 #define ETHSYS_GMAC_RST 23 -#define ETHSYS_ESW_RST 16 #define ETHSYS_FE_RST 6 #define ETHSYS_MCM_RST 2 #define ETHSYS_SYS_RST 0 diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 0000000000..8f1634f7a6 --- /dev/null +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe Subsystem resets */ +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ From patchwork Sun Aug 4 17:23:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141813 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="IwbRPLcu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 461nr01rwCz9sMr for ; Mon, 5 Aug 2019 03:26:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C39A9C21D9A; Sun, 4 Aug 2019 17:24:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 891E0C21DFD; Sun, 4 Aug 2019 17:24:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 20D08C21E15; Sun, 4 Aug 2019 17:24:21 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id 14587C21C8B for ; Sun, 4 Aug 2019 17:24:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939446; bh=HxP5tcqcUefN0ugK7J2Ywf2BNVQvNGUaXV7kwm37JFw=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=IwbRPLcuOOY1Ek1lWqn44pJHs53LhqjXFVEVbBhIqkKyTCjf5UDdrt0TlXPBKUFsn 6yQGbt9UMwD8pPYO5XNv0ir7HgABckdslxYDi074a6t4WGj9HTw9agJQqYNQkxUV7u mt22zhmex1VmKtDUAJl5GSF/pt+Ft/J74LxhD1I4= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MaIw0-1hf0JS1VaS-00Jr4N; Sun, 04 Aug 2019 19:24:06 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:41 +0200 Message-Id: <20190804172342.5225-6-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:bBwqG3gv1nk4hrjrt42igBakG+zBG/rfXa/8IsfTTq9fFUeHExA dpxo1nPPq4wgihsr98BU7bhSqLy5mORXtvAnbm6ZTTYSwYgNwWpyDef2N3/7U2QhdP1Gk8a 8SV1T62ZgENmvHE61PGKoNHTwfHIM66GUt60bJT0NF6gRQXVpcpKyh1pC4xH5mpXIJcdOQu QjsN9qWT8Ctt7/RGhar4g== X-UI-Out-Filterresults: notjunk:1; V03:K0:o1JzBeGeoAs=:OvF4erIQXAZscP6bAoH8r4 FcG840ogyWeYuBOwU3lIcdXLeDxgcdxauanjXOTAZAfPCt/gX1MCIdBleTJasfiBVjocEw/Ti F8g0KVFV6FMOo+CgpH5h4XkIxmIanKUjizRWht7hL+pytt7qBWNfNoD44meZ6WpoamJg1oJGm qJVuvXsd7W2lJhfwka7Ctqky5pCg1FdieRblVjDmvdTI22fnq+geeGMbLyJFaePHWPtKwOZO3 SyqCZSru3D3U9zlf1BrOJcTRUt1kVA1sPC/7sOv9ejNG+C8VoDkb9W0P3SV8YjSsfEpm5Wu8z vp6trSRBaD7xCWBRN75xSn6KoNAuJwdPfoJXdeTdj+0G2bfs//1OABeD8q52n4DM5jHLqPe6r KAhrs7p8JKLa9Tb83CWLWxN4ATFonXYjbzNjWGpnmpnT123C2QiQqLWMO+bX4JcsnSXd8uOx5 wbcbvQSK7/k4ZGY6AYbHF97BOCol0Ft0Yux7G5qiw6Tt4zt8RhGP6gvzXi6s9VfPDz0yBPvdo 2vHbKjW6ldzeMldecDz2n5F+TkYaNB5zqFn296lV9T3n16YXCGOdukmWRo/bzKge5k9BnXGCg 4Bj2xqYMnhK0hlEHQ4Y5zJ1JX057oDiI1+FHKLPnDJJmjeGT968b+2zRp0anAORU2qFW9ySzp Hzeyw24Pzc8FMqJ1fWrEr9rvGYisjC6CYUrLmr+lylOJb0wUnvO9BP6t8fYC9wXqIwrI+fSvT fFOB+ly4B7kcEDcN3IHZLrykxjuBW4Kck3QYg8WU/P4z7m9sCIHGDBb0MQErTLDNhBBbpzodk tvGxLbwH4DTgJnlRMDpXJxPtZq8eQi+bQEE9bXUGT7PK+IY6OTm6GLj6B7b5wMRSTMIZBownm suyVzM0KLR0ALwpfa4vzVsS8QYTw5nwaLviDZA3Q0KinZqSJV8cGyNLisyRNpK0Tn0hGHzU55 QRq81VcSm60tWLWhsKSlTb08VIFwtR1tz59Lpcveuodmrqs7/yH83nqnAE0FC7NwMHqpqSSWw FUl/Mqb8EfcNr503L9dXc5A3IvuzbTUPqTc2FTE4s4srKyzbR54f9JbHNWmgXJTUbNu1PJvv1 mMOmZU5/lIMLYzDi7l52MED9RDrf/LD83Zn/H0poiXvw+SGgvmfDTT9Vg== Subject: [U-Boot] [PATCH v2 5/6] ahci-pci: ASM1061 report wrong class, but support AHCI. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci-pci.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 1ca439d3fa..11ec98b56f 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -35,6 +35,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, + { PCI_DEVICE(0x1b21, 0x0611) }, {}, }; From patchwork Sun Aug 4 17:23:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141814 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 4 Aug 2019 17:24:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1A223C21DA1; Sun, 4 Aug 2019 17:24:24 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lists.denx.de (Postfix) with ESMTPS id D6A9EC21C93 for ; Sun, 4 Aug 2019 17:24:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939447; bh=9cW6ABMbNlSfMLUaCwad0MWdqvcLupFFgPZLP/Dt5wo=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=YKGAGYTpP72kpfzGfukU/2RC03UlHoJ4Yc+ZbTsFEi6FfYcg3vpUWcZhGOVM9biEx JB5rWZWzC5jOLFh+huVgEwPdr4IMNk64oLeCoeNucygOJ/HUo11wkyvlU3Iav5t6X3 DVEDXlgyKAWj3ZNFoeNZJMyQObIy+CHP6+o/krg8= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MeQ43-1hhScC2ryJ-00Q9vw; Sun, 04 Aug 2019 19:24:07 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:42 +0200 Message-Id: <20190804172342.5225-7-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:XlIjazcevcVHH+7rZ/vwAu1T+NxsgaajI0mJvBzeKbyKvIXmNR9 ypguZfic5TdYp4T9/duyXhAHfG4ISpfjzcaVNeSdFZ+moZ1zzHaxqPH+iYtRqu87PjbSJ5j l6OeP/SY9uhcahzaOyhYt3NfGFopiNem0joKvjA4lZyEXxtuip9SJeOED3hUGTr9LhBdER1 eKvq75o7XrFlU9CRsi3TQ== X-UI-Out-Filterresults: notjunk:1; V03:K0:r/tQqNZbnCc=:yCb3Px/cUrq4nkb3vA5gRO W2SQXMNXdEB6y78tCpgf0yXVykImVWVHdBybMQftSW0CjdmZhZR1MT2pfMt8nwmhNHT1VVo42 HD9zzczwgvUKJ20Io6bdwf9OdcaMgLJyhAVlHQvhIHaiGCDC+sOGemVBy5+TrJsB8TIbL7nlf O9WJp/Lfaa/dpW75r/T57w4GEy2PHke53jjRBxAptgSv8zytgMqFo67VOOzDK7s63bs8EGsa+ UVten6lgz3DoXnIV0R6pkAyD7iG0AXmpH1Bcmlx4fP9EwCNBfpvTWGqiUqq2ayEzs5pjzy4UV kgDtRXhRToBpIVJU7ELVhAPGtqXNL1dFLYoueSLUS8omLzHTs7vfKz4ocjd4zWEsEEJX28smw 48JzDaFT++HocOeLQUEX3sUcZao8ZGW+1Ia9H8Z7e0L53n805kl/2v8v4HoGkstJm8uYca/KY aVWX4fR1IIGCa8qcJxhQQKbHF3NzndRH41bXnlG6xwuiAvACvTn4cPEa0nAUw0ZmZfduQNP3c gjGINr13xnpW4JZV4wJXSi3oMPNJQH6hz7O7brbKnraWlqnU9jdAMUciFWCCeOrzUcvEFmtvU RqktXa8CPfv1Y45aN0yJY7yoGGmpwrxdl16qGuIZCokmd1ZFfk22m5kC86U3qN/c9iQGfCCmZ Im+6zHTTOGmjbzLdMrjvl0McLETwO+u0Vo5o3aXNOk5HgwKMY+H0z3iDEz2ZIEEmw371KDI7j EaeXnlo+7kDIGQXMcipsOeFpUU/mN/8fzkkrPNafVYE2aM7RV+haeej91RGrv1fyO5UbE5Bee iLsZxylwQvjMUdvwWR2frfUuPpsJ61fBTgcmG76cGWrPX3CsnbinACmt89sPCUI1wAbZwIm6h ARKW+oad+1pJ+qP+n+d6nrGlEyvtdvZbKT5szlMDoyT2/b/v7O7vi2aEj/ZwAaFc8GAUU5kbK vuZ/GeW5/7N0nbt5lIpNL6O3VEOjlvueVWItELVchZwZr9gmyMIkZ0NKD2UiRK7BfbYB7hN4G i/aAN6cqkm/edNLOgzyn+oNxzz8FQLr2IRT8Uo3UAg45XcyC5a+KyJwWJ1AXXOkqWRavpEtzk K8oc5EkZqeaZoHWrfFsVRpfqnsKZm16pPrA8mibLtV2SPoeg3oBr49kOA== Subject: [U-Boot] [PATCH v2 6/6] ata: ahci: Don't forget to clear upper address regs. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko In 32bits mode upper bits need to be set to 0, otherwise controller will try to DMA into not existing memory and stops with error. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index e3135bb75f..716f9c1c7e 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -593,10 +593,15 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((unsigned long)pp->cmd_slot, - port_mmio + PORT_LST_ADDR); + writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); +#ifndef CONFIG_PHYS_64BIT + writel_with_flush(0, port_mmio + PORT_LST_ADDR_HI); +#endif writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); +#ifndef CONFIG_PHYS_64BIT + writel_with_flush(0, port_mmio + PORT_FIS_ADDR_HI); +#endif #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio);