From patchwork Wed Jul 31 11:51:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1139700 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="ivAw2mM6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45zBd147Y3z9s00 for ; Wed, 31 Jul 2019 21:52:53 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C7F80C21DFB; Wed, 31 Jul 2019 11:52:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D70ADC21C38; Wed, 31 Jul 2019 11:52:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2A3C3C21C3F; Wed, 31 Jul 2019 11:52:11 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lists.denx.de (Postfix) with ESMTPS id C6235C21C38 for ; Wed, 31 Jul 2019 11:52:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564573915; bh=HxP5tcqcUefN0ugK7J2Ywf2BNVQvNGUaXV7kwm37JFw=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=ivAw2mM6LjBZ3Y5P65WJ1B9Cl0kA57SmP/iMdkleFZNxspqnDFCty/6pWCY1W0s6C 5pqMLOabomMkWyi/QqNA7j/oZnfEsf1ohqoNZ5xJDGNj+MrTonToYT5sNb0nArjFy/ VvXTtKOVKM0KhTDNiHhTWga5TnN01s0WafiCDM/w= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.145.165]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MgsVY-1hfg6d13ke-00M32B; Wed, 31 Jul 2019 13:51:55 +0200 From: Frank Wunderlich To: Albert Aribaud , Bao Xiaowei , Bin Meng , Christian Gmeiner , Hou Zhiqiang , Marek Vasut , Mark Lee , Oleksandr Rybalko , Prabhakar Kushwaha , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Wed, 31 Jul 2019 13:51:42 +0200 Message-Id: <20190731115145.22095-2-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731115145.22095-1-frank-w@public-files.de> References: <20190731115145.22095-1-frank-w@public-files.de> X-Provags-ID: V03:K1:1pPOF1trXypBtPJXQec+uPwzrmO7N+alZzbcWdESvpEoOei2sxH PCHGPFew8khDfya6GG4Jf5764ttRWqHsZwJYKAtZ0vdwUjZDDqRCOEExWvhkUKuL4iFA2rJ 7iBTN+6va981qZTfn8T7IE9N3mbN36pSioFwedFbGN9Wh+BRYSiATFqZTu42Yf/NznOKAJV CFLb840pEN3G09VGH/WTA== X-UI-Out-Filterresults: notjunk:1; V03:K0:AB7A4+B5Nrw=:M8Na3Ffog40UWoazgOJgY+ rOcz/DrANgBxq7gfqNsc5VynTqp4y3yKVGQna3rZ3HiUNfP27cMGcmFQkGpgMGBcnD8IRs+qE 4wsjHWari3YaWjbWjtxK9vxqTshaoc4biHNRbX4TmPZWqfl0ig3p+Nik0l8sfTsEGPB7l7c2b F8zJ5IPF82o/Dz81ctA/b1Ndoyj+imiGzBds1FdKJ8quKfzxgmFnCuZ99Lyj1dWSq3P/WpfRf bUj1iw+5VBNR4/Dix2EgCdnwr0NY8hqEiYvUzWyUdj9t6wizkf+G32qDGpwe0P5Rx7vpF0gd3 MXMWw+JYaiRciy9J726vgLdprcT1yp3Q+c0MxtqYiieToxw42F91DrLUJeKtJFQcPs6qrq4te VkOQo8PwEBQKPHn2wRw0iy5e7M95XuXH8OZNxcEuiTkaHZ8371QKMtNri2imXkivvnMegRa3w EUJfGiwtSJQ2cWHcJRHlvYO7lmc8pa8zH2Ve3UAfno+xWcOfJXYDY1GDS1GcPVE9viU7pC72q W6c+9U1iRXErKeFIJOWhBOev5iq2oUfqnMCLc42Yj9Jst6Z2baZydQfv7x6zwbl5wAWDz+MR6 JO9BxinjhJiLOfCDPXQh7Y5MiyKeoXzlEabjSrspUE3CveXvZzwRQhKqd1Tm5ujiN2TkJiNuV ZPgzk6tOvhXKxpuEi9LQE3TYMb9AWGFtoChdIUNVKiikAVyxp7LWcrY0ZHjDvFxN+DtG4sH3D nW/Cv5ou8uo2lWbgw4/qNqEjtAyXDnfiuTdaLQ9Rv2v0AagydWf3l8Pd0B8Ugmljldo0pMLO4 EMxA0CYatp5mwzSbhRapWs/uI0U/zLCJ11kfYnbL3OqViuVD91RJbkT1ImDooIuCuO6MfZK0a vYBRag3gMnsAPMrTDojLihNcPBBNtU0k6deqE5igICsKm/SYyVcBVF4IdEs9m4RvNM7EM6G6S juT/CVZ0pB23nMrY+KhMbzCcG1cmrG9zdH8vvYIjSlneCRvhhnaL9vRDguW+NRE8a682miJJ5 CXGl4aASJvjsqTBxDSj8IuLXzFHnI5/jp3ev83Rq67RXI0zBmNXHUpNFm79I+tdKDtt/f/iO6 PoRxNejDm8Leek= Subject: [U-Boot] [PATCH 1/4] ahci-pci: ASM1061 report wrong class, but support AHCI. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci-pci.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 1ca439d3fa..11ec98b56f 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -35,6 +35,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, + { PCI_DEVICE(0x1b21, 0x0611) }, {}, }; From patchwork Wed Jul 31 11:51:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1139701 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="aeF7Flrr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45zBdv2yYvz9s00 for ; Wed, 31 Jul 2019 21:53:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E3CA6C21E26; Wed, 31 Jul 2019 11:52:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 096D8C21E34; Wed, 31 Jul 2019 11:52:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9D5AFC21E02; Wed, 31 Jul 2019 11:52:18 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lists.denx.de (Postfix) with ESMTPS id CCD78C21E1B for ; Wed, 31 Jul 2019 11:52:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564573917; bh=9cW6ABMbNlSfMLUaCwad0MWdqvcLupFFgPZLP/Dt5wo=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=aeF7FlrrmWoTWH0t20wnF7xcXM+jY1FMg/YZivwUyuMPrgMx6uyOHPxuHItqFYSN6 azs1eCihGzDo4zkmDc9sUtfDGQdJFVxsJF4eDJVPT5wY9GFL/jIPUsb6igU0bIw5n0 LWKziSUz3vGCX9M6pGOZJxLtoi3pAEbs6+za6Rww= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.145.165]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MRXVc-1hmItA3Zay-00Scbj; Wed, 31 Jul 2019 13:51:57 +0200 From: Frank Wunderlich To: Albert Aribaud , Bao Xiaowei , Bin Meng , Christian Gmeiner , Hou Zhiqiang , Marek Vasut , Mark Lee , Oleksandr Rybalko , Prabhakar Kushwaha , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Wed, 31 Jul 2019 13:51:43 +0200 Message-Id: <20190731115145.22095-3-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731115145.22095-1-frank-w@public-files.de> References: <20190731115145.22095-1-frank-w@public-files.de> X-Provags-ID: V03:K1:WLwXme2Y0SI6m7AB3dtHhJofxb+YWraucW3eI0xU96Gtbr9f1Pv aeSdbDruTHqjtSSIgAw0RG3A0FEeCUbDNYRM03QwDXwhrTOTWFsCv7hW6/3e4aVUB4WsTBr 2G+2pZ5Mk15kgGieP9ZOIBBmVqntHQ7NXh14HgGWD/18yDy/puTR1mqZdoJh7Y7zoZa7rUK 77CCYT6xdNvHvUx79CTeQ== X-UI-Out-Filterresults: notjunk:1; V03:K0:znIvqp2CCfk=:qPPWXo9lBJRh1Oaqkgn/hz 29LrOQFNsqh05Re0zjuWq3dl47YAPpaBInk3gR3/FbIZFJOGS4jnHgBEnJsGh5Xe3PZZEvSvu w4sum1Kwah9RQXa+NT9PqQSvMpqOsUNTORuvdSEsch5uNAGPRL4enwONu9wjaQPG4mSKLl78q p6gWDYJGu9LrXlfN4QPlONV63yDQSzH4iYjAAOo2riPj5xCgMimRmrne5Bw0mDRflFQe+liJb 8H5oPhaHQAsGmhq1cR3EAhKycdeaNMlSExNQKJKUweiutQjg9Lcb5/RLWNTUrDELmRQ0MCFKj 2DLiaCi1fs/AHXh1G4ihJmkkbPL2pG4r5K7MLdvuNAWYsCvC3KKj4iKilh/+BH+PL4pGKlhjr AsGYkUH6pPnvO59rLvPJXKqSzbB1g0T+1NUegH6YPP7E2SDsGl6HTfcVIylKBXf5OwUvnASKx 4qgpXq/f5n6u5Qj1Ar30XSsv5tHyizQbb3dWKvJN4ntInsSFRH7IA/a8eWsTkMQZ7oDedMGzG zYb1KLlDQpdF64yeySjyR6atUFrkPmzZLL1ssq+QW6Hs/CxD7eq4E/clPbVdAWIxVaCFRTMQb 2r1d2tSQV8nkMa33f82iZv2yTEdFNzlxjGCz+/Tp1qK4X2VL6/WFOo31qCcS3mUoGp6xoVgcw YUvGN7pbt6YtLh1BVLaoJeugGmit7qmToJ7fAC8vvpLmEQrY0mQyQGlvdqJSZtA5/qgr4lc+U XJJUgb+Ro2mDiCtEQeG4LhL+eMygMn4f1T+NYOShjf1Qlf8te7nfMDZXpbG5Lx8pdrhfDluCF 46bFAlM+N5NI8l4QspeEbyoGAG7g1nvy5YfH7uIwM/GvjG76RV/w/9/mcjv2/tep1T4Pvb1Iz NlX5tx7TD1cSGB36L6eNf0qsGip/u0wAV3VJH72vLJlJrbSar7uYtSr6XRQtskBo5fvlmw5gc TrnSQif3ZW22aL5cDCmIm6Blp06Yxh1dzJxM5rFBMnt26oIHl8l8FUEuTRIi4MSyEyo3O3PMf 2Qpt9J/VtV2FYr3EYBbzbbwOAXqJsFbjmcRl/PEFQlwABC0Wj0yhnesBK4FZGPz6E2Lpke8Ku c4iJGKd8nNGREU= Subject: [U-Boot] [PATCH 2/4] ata: ahci: Don't forget to clear upper address regs. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko In 32bits mode upper bits need to be set to 0, otherwise controller will try to DMA into not existing memory and stops with error. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index e3135bb75f..716f9c1c7e 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -593,10 +593,15 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((unsigned long)pp->cmd_slot, - port_mmio + PORT_LST_ADDR); + writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); +#ifndef CONFIG_PHYS_64BIT + writel_with_flush(0, port_mmio + PORT_LST_ADDR_HI); +#endif writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); +#ifndef CONFIG_PHYS_64BIT + writel_with_flush(0, port_mmio + PORT_FIS_ADDR_HI); +#endif #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio); From patchwork Wed Jul 31 11:51:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1139703 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="RFt1f+lW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45zBff6bv6z9s00 for ; Wed, 31 Jul 2019 21:54:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9AAABC21E1B; Wed, 31 Jul 2019 11:53:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BDDE2C21E4F; Wed, 31 Jul 2019 11:53:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AC3B8C21E4E; Wed, 31 Jul 2019 11:52:20 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lists.denx.de (Postfix) with ESMTPS id 583ADC21E0F for ; Wed, 31 Jul 2019 11:52:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564573918; bh=xXtH22TimIRCXyJ6/UquYlmbEHJHBppfamOuGdSdqsA=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=RFt1f+lWh5DwofU1rClkZ0490NJ5ryiWZnf3K9j1nlw0CGxPo933i476mxcpU5plI rMaRquN0/iDsQCMFceAMxCzSunJ0Ke5RHjbFpcD6YdD5x9GBh104vXONzegnlN6KIx CnqgBlx0Hx8qTfxxnojH6mGGhugQ0BdhV36Aq28w= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.145.165]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MVNWU-1hsNQO1pRm-00YeDN; Wed, 31 Jul 2019 13:51:58 +0200 From: Frank Wunderlich To: Albert Aribaud , Bao Xiaowei , Bin Meng , Christian Gmeiner , Hou Zhiqiang , Marek Vasut , Mark Lee , Oleksandr Rybalko , Prabhakar Kushwaha , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Wed, 31 Jul 2019 13:51:44 +0200 Message-Id: <20190731115145.22095-4-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731115145.22095-1-frank-w@public-files.de> References: <20190731115145.22095-1-frank-w@public-files.de> X-Provags-ID: V03:K1:QJV8U5ggU4FeW7QSbdByQ532D/tfj4zarmGCrH6shzR1skkQVdT MQK5i1VoWxphF6Ic1jdJDWS7IpHA4780QxclDeMfBZp+Z64LH9oaXM1OgBPeTzEhvZ97Wva dLAqiiFTOVVxEt1t0h+OWyoomy1N214WvdW2seomvTmDx4HwdnNiIDyn78wZgDcdvPq7myE N7Q9KTnj+NwI4KmFf6BMg== X-UI-Out-Filterresults: notjunk:1; V03:K0:+n05y2VhhFI=:TYLuDIPC5b48kVWdgGdsDA WY6hpg+XGApGonRzOgzga9XXs4ihB/ENy852HWZQ9JPA2bzNBTj7ztlw4QitjZ/YOc2JblcMl 1yZxhgmGoQITc6kVPXgP0fCjZJmGQL3SP4wNg6WfZ8DDLoIXzcSMcdBQNUfTckx6RGdxU9YR6 Md0O9oHGYPfqnm2EsyQ3SacFOLxicpSRpk/NlD8fuW5LK8zeyhARQ66s0b7fdLx3bMBauIwHH 7PMwl5EQwm++EsMGYY5UitiDggiI4HkdMw2mB0uGK8BeJMKmmYGKvBdV9zxy0tT9c5XyvLs9i UtM2nD1lQ9HERy7qWvPSNCphZ1k2KoremQErMvDUWKQzgmOIxW9SBs8Y57Cc+RzQH2O9RcybW BuJB3sqovqyw4bLsRrxDtcdtF/qSf4JEGwB3d0h5UpshFPRstGEBrP181B0PIQVmwV9Kr1Uml /5Sz27mor25fYjF3ZhZ9JGK0TEorRwpEoqC3x6AkuDBYmGk8fIWrFLwzbl0aR/XSecT6F+cNw tuOLueDn5SADIudT0vEUJ9jS4j2nsoe5PflS0A10U1fvbbsSvMAJScOcEbmI/EQA0xgSPo2q7 v9hltb8ikHkcfQgCK69534l+1HgJitRzzG6rFSQCK8mtBKGYAYmqNK4WXz0cFjGhzN3tEoF5I DQtmBlJU08UqLkyZvOVjC4AQpMa1fuNdHjZkeGsKjdFP4eeA12OqdQ6utYtS5Crd7zYCSJ8zh 0p53JHyloOAdVefobAd8EGqoAndQ/NK2sre7ID2hof6JbyOOkaigWepi+6eGnX+ARbw6cKJHJ QdVhGrs+u0TFgr02J4AigiTzlXcxD98H/ziq9cPZc11ll+Zw6WHoY8tLUPScd8WZVr1I1MXxn LJxpk96CpDdoJhICPCXKt0qQNRMJBdHshFQjPc7IYN5dszkLdkUpxrT6g6zgGo0wg59KXECWy KxcWRPt+3QUj0Nr+/m3dStJdUpdyVE7SHZkdGXafhFis4wx8viX1jj8tvRwYJdCSZyOqqAC/n tScIM2jfIQ8KPyBbhYeVKpRTwI/lYIlVjqmZzpvFCk9uWUbROrOE7BPc6wf5aHYQ39QlbRUZX x1h5Q5207usNL8= Subject: [U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko this chip is used in MT7623 and some other Mediatek SoCs for pcie Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/pci/Kconfig | 6 + drivers/pci/Makefile | 1 + drivers/pci/pci-mt2701.c | 490 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 497 insertions(+) create mode 100644 drivers/pci/pci-mt2701.c -- 2.17.1 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 3fe38f7315..cfe8ba5e52 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -145,4 +145,10 @@ config PCI_MVEBU Say Y here if you want to enable PCIe controller support on Armada XP/38x SoCs. +config PCIE_MT2701 + bool "Mediatek 2701 PCI-E" + help + Say Y here if you want to enable PCIe controller support on + Mediatek MT7623 + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index b5ebd50c85..a4c4002b9c 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ pcie_layerscape_gen4_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o +obj-$(CONFIG_PCIE_MT2701) += pci-mt2701.o diff --git a/drivers/pci/pci-mt2701.c b/drivers/pci/pci-mt2701.c new file mode 100644 index 0000000000..5904f15330 --- /dev/null +++ b/drivers/pci/pci-mt2701.c @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Mediatek MT7623 SoC PCIE support + * + * Copyright (C) 2015 Mediatek + * Copyright (C) 2015 John Crispin + * Copyright (C) 2015 Ziv Huang + * Copyright (C) 2019 Oleksandr Rybalko + */ + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#define iowrite32(v, a) writel(v, a) +#define iowrite16(v, a) writew(v, a) +#define iowrite8(v, a) writeb(v, a) +#define ioread32(a) readl(a) +#define ioread16(a) readw(a) +#define ioread8(a) readb(a) + +#define RT_HIFSYS_BASE 0x1a000000 +#define RT_PCIE_BASE 0x1a140000 +#define RT_PCIE_IOWIN_BASE 0x1a160000 +#define RT_PCIE_IOWIN_SIZE 0x00010000 +#define RT_PCIE_MEMWIN_BASE 0x60000000 +#define RT_PCIE_MEMWIN_SIZE 0x10000000 + +#define RD(x) readl(RT_PCIE_BASE | (x)) +#define WR(x, v) writel(v, RT_PCIE_BASE | (x)) + +#define SYSCFG1 0x14 +#define RSTCTL 0x34 +#define RSTSTAT 0x38 +#define PCICFG 0x00 +#define PCIINT 0x08 +#define PCIENA 0x0c +#define CFGADDR 0x20 +#define CFGDATA 0x24 +#define MEMBASE 0x28 +#define IOBASE 0x2c + +#define BAR0SETUP 0x10 +#define IMBASEBAR0 0x18 +#define PCIE_CLASS 0x34 +#define PCIE_SISTAT 0x50 + +#define MTK_PCIE_HIGH_PERF BIT(14) +#define PCIEP0_BASE 0x2000 +#define PCIEP1_BASE 0x3000 +#define PCIEP2_BASE 0x4000 + +#define PHY_P0_CTL 0x9000 +#define PHY_P1_CTL 0xa000 +#define PHY_P2_CTL 0x4000 /* in USB space */ + +#define RSTCTL_PCIE0_RST BIT(24) +#define RSTCTL_PCIE1_RST BIT(25) +#define RSTCTL_PCIE2_RST BIT(26) +#define MAX_PORT_NUM 3 + +struct resource { + char *name; + u32 start; + u32 end; +}; + +struct mt_pcie { + char name[16]; +}; + +static struct mtk_pcie_port { + int id; + int enable; + u32 base; + u32 phy_base; + u32 perst_n; + u32 reset; + u32 interrupt_en; + int irq; + u32 link; +} mtk_pcie_port[] = { + { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) }, + { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) }, + { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) }, +}; + +struct mtk_pcie { + struct device *dev; + void __iomem *sys_base; /* HIF SYSCTL registers */ + void __iomem *pcie_base; /* PCIE registers */ + void __iomem *usb_base; /* USB registers */ + + struct resource io; + struct resource pio; + struct resource mem; + struct resource prefetch; + struct resource busn; + + u32 io_bus_addr; + u32 mem_bus_addr; + + struct clk *clk; + int pcie_card_link; +}; + +static const struct mtk_phy_init { + u32 reg; + u32 mask; + u32 val; +} mtk_phy_init[] = { + { 0xc00, 0x33000, 0x22000 }, + { 0xb04, 0xe0000000, 0x40000000 }, + { 0xb00, 0xe, 0x4 }, + { 0xc3C, 0xffff0000, 0x3c0000 }, + { 0xc48, 0xffff, 0x36 }, + { 0xc0c, 0x30000000, 0x10000000 }, + { 0xc08, 0x3800c0, 0xc0 }, + { 0xc10, 0xf0000, 0x20000 }, + { 0xc0c, 0xf000, 0x1000 }, + { 0xc14, 0xf0000, 0xa0000 }, + { 0xa28, 0x3fe00, 0x2000 }, + { 0xa2c, 0x1ff, 0x10 }, +}; + +/* + * Globals. + */ + +struct mtk_pcie pcie; +struct mtk_pcie *pcie0; + +static int mtk_pcie_probe(void); +static int mt_pcie_read_config(struct udevice *, pci_dev_t, uint, ulong *, + enum pci_size_t); +static int mt_pcie_write_config(struct udevice *, pci_dev_t, uint, ulong, + enum pci_size_t); + +#define mtk_foreach_port(p) \ + for ((p) = mtk_pcie_port; \ + (p) != &mtk_pcie_port[ARRAY_SIZE(mtk_pcie_port)]; (p)++) +#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) + +static void +mt7623_pcie_pinmux_set(void) +{ + u32 regValue; + + /* Pin208: PCIE0_PERST_N (3) */ + regValue = le32_to_cpu(ioread32(0x100059f0)); + regValue &= ~(BITS(9, 11)); + regValue |= 3 << 9; + iowrite32(regValue, 0x100059f0); + + /* Pin208: PCIE1_PERST_N (3) */ + regValue = le32_to_cpu(ioread32(0x100059f0)); + regValue &= ~(BITS(12, 14)); + regValue |= 3 << 12; + iowrite32(regValue, 0x100059f0); +} + +static void +sys_w32(struct mtk_pcie *pcie, u32 val, unsigned int reg) +{ + iowrite32(val, pcie->sys_base + reg); +} + +static u32 +sys_r32(struct mtk_pcie *pcie, unsigned int reg) +{ + return ioread32(pcie->sys_base + reg); +} + +static void +pcie_w32(struct mtk_pcie *pcie, u32 val, unsigned int reg) +{ + iowrite32(val, pcie->pcie_base + reg); +} + +static void +pcie_w16(struct mtk_pcie *pcie, u16 val, unsigned int reg) +{ + iowrite16(val, pcie->pcie_base + reg); +} + +static void +pcie_w8(struct mtk_pcie *pcie, u8 val, unsigned int reg) +{ + iowrite8(val, pcie->pcie_base + reg); +} + +static u32 +pcie_r32(struct mtk_pcie *pcie, unsigned int reg) +{ + return ioread32(pcie->pcie_base + reg); +} + +static u32 +pcie_r16(struct mtk_pcie *pcie, unsigned int reg) +{ + return ioread16(pcie->pcie_base + reg); +} + +static u32 +pcie_r8(struct mtk_pcie *pcie, unsigned int reg) +{ + return ioread8(pcie->pcie_base + reg); +} + +static void +pcie_m32(struct mtk_pcie *pcie, u32 mask, u32 val, unsigned int reg) +{ + u32 v; + + v = pcie_r32(pcie, reg); + v &= mask; + v |= val; + pcie_w32(pcie, v, reg); +} + +static void +mtk_pcie_configure_phy(struct mtk_pcie_port *port) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) { + void __iomem *phy_addr = (void __iomem *)port->phy_base + + mtk_phy_init[i].reg; + u32 val = ioread32(phy_addr); + + val &= ~mtk_phy_init[i].mask; + val |= mtk_phy_init[i].val; + iowrite32(val, phy_addr); + udelay(100); + } + mdelay(16); +} + +static void +mtk_pcie_configure_rc(struct mtk_pcie *pcie, struct mtk_pcie_port *port) +{ + ulong val = 0; + + mt_pcie_write_config(NULL, (port->id) << 3, PCI_BASE_ADDRESS_0, + 0x80000000, PCI_SIZE_32); + mt_pcie_read_config(NULL, (port->id) << 3, PCI_BASE_ADDRESS_0, &val, + PCI_SIZE_32); + + /* Configre RC Credit */ + val = 0; + mt_pcie_read_config(NULL, (port->id) << 3, 0x73c, &val, PCI_SIZE_32); + val &= ~(0x9fffUL) << 16; + val |= 0x806c << 16; + mt_pcie_write_config(NULL, (port->id) << 3, 0x73c, val, PCI_SIZE_32); + mt_pcie_read_config(NULL, (port->id) << 3, 0x73c, &val, PCI_SIZE_32); + + /* Configre RC FTS number */ + mt_pcie_read_config(NULL, (port->id) << 3, 0x70c, &val, PCI_SIZE_32); + val &= ~(0xff3) << 8; + val |= 0x50 << 8; + mt_pcie_write_config(NULL, (port->id) << 3, 0x70c, val, PCI_SIZE_32); + mt_pcie_read_config(NULL, (port->id) << 3, 0x70c, &val, PCI_SIZE_32); +} + +static void +mtk_pcie_preinit(struct mtk_pcie *pcie) +{ + struct mtk_pcie_port *port; + u32 val = 0; + int i; + + mt7623_pcie_pinmux_set(); + + /* PCIe RC Reset */ + val = 0; + mtk_foreach_port(port) + if (port->enable) + val |= port->reset; + sys_w32(pcie, sys_r32(pcie, RSTCTL) | val, RSTCTL); + mdelay(12); + sys_w32(pcie, sys_r32(pcie, RSTCTL) & ~val, RSTCTL); + mdelay(12); + + i = 100000; + while (i--) { + if (sys_r32(pcie, RSTSTAT) == 0) + break; + udelay(10); + } + + /* Configure PCIe PHY */ + + mtk_foreach_port(port) + if (port->enable) + mtk_pcie_configure_phy(port); + + /* PCIe EP reset */ + val = 0; + mtk_foreach_port(port) + if (port->enable) + val |= port->perst_n; + pcie_w32(pcie, pcie_r32(pcie, PCICFG) | val, PCICFG); + mdelay(12); + pcie_w32(pcie, pcie_r32(pcie, PCICFG) & ~val, PCICFG); + mdelay(200); + + /* check the link status */ + val = 0; + mtk_foreach_port(port) { + if (port->enable) { + if ((pcie_r32(pcie, port->base + PCIE_SISTAT) & 0x1)) + port->link = 1; + else + val |= port->reset; + } + } + sys_w32(pcie, sys_r32(pcie, RSTCTL) | val, RSTCTL); + mdelay(200); + + i = 100000; + while (i--) { + if (sys_r32(pcie, RSTSTAT) == 0) + break; + udelay(10); + } + + mtk_foreach_port(port) { + if (port->link) + pcie->pcie_card_link++; + } + printf("%s: PCIe Link count=%d\n", __func__, pcie->pcie_card_link); + if (!pcie->pcie_card_link) + return; + + pcie_w32(pcie, pcie->mem_bus_addr, MEMBASE); + pcie_w32(pcie, pcie->io_bus_addr, IOBASE); + + mtk_foreach_port(port) { + if (port->link) { + pcie_m32(pcie, 0xffffffff, port->interrupt_en, PCIENA); + pcie_w32(pcie, 0x7fff0001, port->base + BAR0SETUP); + pcie_w32(pcie, 0x80000000, port->base + IMBASEBAR0); + pcie_w32(pcie, 0x06040001, port->base + PCIE_CLASS); + } + } + mdelay(100); + + mtk_foreach_port(port) + if (port->link) + mtk_pcie_configure_rc(pcie, port); +} + +static void +mtk_pcie_fill_port(struct mtk_pcie *pcie) +{ + int i; + + for (i = 0; i < 2; i++) + mtk_pcie_port[i].phy_base += (u32)pcie->pcie_base; + + mtk_pcie_port[2].phy_base += (u32)pcie->usb_base; +} + +void +mt_pcie_init(void) +{ + /* Static instance of the controller. */ + static struct pci_controller pcc; + struct pci_controller *hose = &pcc; + + memset(&pcc, 0, sizeof(pcc)); + + /* PCI I/O space */ + pci_set_region(&hose->regions[0], RT_PCIE_IOWIN_BASE, + RT_PCIE_IOWIN_BASE, RT_PCIE_IOWIN_SIZE, PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], RT_PCIE_MEMWIN_BASE, + RT_PCIE_MEMWIN_BASE, RT_PCIE_MEMWIN_SIZE, + PCI_REGION_MEM); + + hose->region_count = 2; +} + +int +mtk_pcie_probe() +{ + pcie0 = &pcie; + + pcie0->io_bus_addr = RT_PCIE_IOWIN_BASE; + pcie0->mem_bus_addr = RT_PCIE_MEMWIN_BASE; + pcie0->sys_base = (u32 *)RT_HIFSYS_BASE; + pcie0->pcie_base = (u32 *)RT_PCIE_BASE; + + mtk_pcie_fill_port(pcie0); + + mtk_pcie_preinit(pcie0); + + return 0; +} + +/* Probe function. */ +void +pci_init_board(void) +{ + mtk_pcie_probe(); + mt_pcie_init(); +} + +static int +mt_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + u32 address = bdf | ((offset & 0xf00) << 16) | (offset & 0xfc); + + pcie_m32(pcie0, 0xf0000000, address, CFGADDR); + + switch (size) { + case PCI_SIZE_8: + *valuep = pcie_r8(pcie0, CFGDATA + (offset & 3)); + break; + case PCI_SIZE_16: + *valuep = pcie_r16(pcie0, CFGDATA + (offset & 2)); + break; + case PCI_SIZE_32: + *valuep = pcie_r32(pcie0, CFGDATA); + break; + } + + return 0; +} + +static int +mt_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + u32 address = bdf | ((offset & 0xf00) << 16) | (offset & 0xfc); + + pcie_m32(pcie0, 0xf0000000, address, CFGADDR); + + switch (size) { + case PCI_SIZE_8: + pcie_w8(pcie0, value, CFGDATA + (offset & 3)); + break; + case PCI_SIZE_16: + pcie_w16(pcie0, value, CFGDATA + (offset & 2)); + break; + case PCI_SIZE_32: + default: + pcie_w32(pcie0, value, CFGDATA); + break; + } + return 0; +} + +static int +mt_pcie_probe(struct udevice *dev) +{ + mtk_pcie_probe(); + mt_pcie_init(); + return 0; +} + +static const struct dm_pci_ops mt_pcie_ops = { + .read_config = mt_pcie_read_config, + .write_config = mt_pcie_write_config, +}; + +static const struct udevice_id mt_pcie_ids[] = { + { .compatible = "mediatek,mt7623-pcie" }, + { } +}; + +U_BOOT_DRIVER(pcie_mt2701) = { + .name = "pci_mt2701", + .id = UCLASS_PCI, + .of_match = mt_pcie_ids, + .ops = &mt_pcie_ops, + .probe = mt_pcie_probe, + .priv_auto_alloc_size = sizeof(struct mt_pcie), +}; From patchwork Wed Jul 31 11:51:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1139695 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="AeroNegp"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45zBcQ32Dpz9s00 for ; Wed, 31 Jul 2019 21:52:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A7B7FC21E1E; Wed, 31 Jul 2019 11:52:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6C7C7C21C6A; Wed, 31 Jul 2019 11:52:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A1EB3C21C3F; Wed, 31 Jul 2019 11:52:10 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lists.denx.de (Postfix) with ESMTPS id 45FD7C21C38 for ; Wed, 31 Jul 2019 11:52:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564573920; bh=e2TvaDP2DKF1UrlPndHzNi1S6AHD1xyVQOZ+P8rELwo=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=AeroNegpbL53ZuiDlIINIQh3xMYB+c9tkzMO30uUtQhb2dOvHrtoIMGyWNw8w/zfn GhhxQOEIV6T565r0ylu/uCEbyEROuzXnjbwEdrDteulNhnbOtj8KZJJBFfGFyj4Qs5 9ZjCtC90sUG4WVHyDGvf5Zlv8/5U7Tw5LxWLEzkE= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.145.165]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0M8MyE-1iFI3818Rm-00vvkX; Wed, 31 Jul 2019 13:52:00 +0200 From: Frank Wunderlich To: Albert Aribaud , Bao Xiaowei , Bin Meng , Christian Gmeiner , Hou Zhiqiang , Marek Vasut , Mark Lee , Oleksandr Rybalko , Prabhakar Kushwaha , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Wed, 31 Jul 2019 13:51:45 +0200 Message-Id: <20190731115145.22095-5-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731115145.22095-1-frank-w@public-files.de> References: <20190731115145.22095-1-frank-w@public-files.de> X-Provags-ID: V03:K1:mdpp5sG8u3g41s7QKrY9EQjhgQfd16Ag2nfn+P7VYTgM9TcNqvi e7w316xQPdH1prVcixMWD4xgLkbLdEmBlOU/+GPAWS1lA32JKqSpwbEMTZWbO0HTpxP9Sx8 mfu3Qww5r49YdouFeKkbbo7a21gvoUz1iM+AqIW00TKDzc50ViJ7Nj5GO/MlA+rlMWmByS3 HoCe56WOfxNvK2WCEfsqg== X-UI-Out-Filterresults: notjunk:1; V03:K0:BmRIMe/L+Uw=:TNDOlYpoRRbzZpOEY/hvnZ jPKe3W4Uqi8G4TzQC1RbV1v4yCbx6ZlaezJEU8R45kFztvZiD1bMFgSJWuIuwlWK2GuDi1fxY UsF/ViD/2F4VEjTvYyz6vspw4FVvqsn43dc8ShMC3r+m6Jd1/G0iSipAgTy3QBA+rvdNQTS+U vAFAcLqMi97PRl2uFq6gztY0pXyd1A2jU0MYWcIhe4qaGveAoR5Uv1+KFoVaTFa196n7sYakR K42/UtcWlKNw/T75v30mzEyTkWXiEI/1IfEvCwt0dl/8cBy1BXYA8L98jFE/dQfIn4N+SsZ0o IB15i5MWnL7Zzi97HqeuxWVHHZxNg433eAXfNCyZNfrvmqKcYwuiLqTHRR7ZYATt7RGVb1VXV 72fvgJQKfz3tevhk6nSLw4B4+z/2HLI55FwUQWEUKeRGRosk4QkctjZledCGmMjm5O81hEAKf eN+GnSQJFzf3xSXwWoDOhZCjtzX3O0MuOqNrDIodwo73pIXhwhFhOLZ7pMvgeqagHdJZ+xwnE OGy7foeQbIaekaK0qgq3DEBzeVHIle6vOz2E4Lv3h7NWW/lTGK8j/upD9+IjMZSpMxF80LHOY ViUGbCEHLxTejerBIC8Z2GrIJUyqb6YA0KvyqGDxM9eN1Din3q34fjyURmQtGC1aOINZVzw20 Le22Nbq9RVNkvfvytH+LWBa0wNincsGm8S4r/tbZD6O3tqA645qIydkkbeyszVQcCeH3RETv0 ej9qOBi9NmNTCk+0TZR7CEjQVscPo5jgLXN1zob4BQC9uCH6B7hdizBIaTAVXVTwuGb2GoHGc oltleQ5xOL2HINoUQJ6IRu+GFwH/n0hyk6xnsd1G3wEFOr/PVBTgoMaCIWAFP0U6lWZe0W0tg mxMzck0A09Ac83FjTCediCYY40TR+5M6QWb9YBnfDdkkDzUuydMclDCUbjUpOxYjLjmZS+U8Y KbEK/8loFhIwmSmS8hlg/IX+78jyHXjoxTiqJuPibtyBPk2+IXFdZYf+GMImLSQd+eD0W3aEH mDtZz05QvG+6Rm8bFESmC775d7xp2hclXU4GY8fXHWQEG90XbuZskMQEJ0+2+3bamlrMMuPxC Q4u+PfLoNqfkPE= Subject: [U-Boot] [PATCH 4/4] arm: dts: Add PCI-E controller for mt7623 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" this Patch adds pcie-controller node for mt7623 Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7623.dtsi | 108 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 64079c61bf..5d7c62bb8d 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -255,6 +255,114 @@ #reset-cells = <1>; }; + pcie: pcie-controller@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 + IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 + IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 + IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "okay"; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 + IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie@1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 + IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 + IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0x1a149900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0x1a14a900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>;