From patchwork Sun Jun 30 21:15:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1125015 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504030-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45cNb20jySz9s4V for ; Mon, 1 Jul 2019 07:15:48 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=kE71xbV6MHnFIAc+lsTEJ1AD9njfq7miMLSuWuohXrnOT4 uy/dUpN6oW1swCOkYnuW6tGoRL7IFCR0Rnc7iZLWsd/0C3J6iNuOt5YfT24mImUI sH5jhiqPVcdHEBpsRrhLi0Q5IKQLJhuExuj/rz9TInxNgLL7p8ju6/apwcBVY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=HStXpPXE3gHN7332VPeFOQwVBkU=; b=tJ8c6Z6EPdxtlKGL6JJg 2eLPlk8ik12GpcLyMBVxAzwr3tdawjaU1+zIKtRZ57AM36srnvcBFOpppqN/FSCf RFAqUzqrRk3isS6o1Cl3UAnmdrE+Rs7Ca/1uk7pOUpBg2DYGG+WPTrYLbaPEKJKa ulTvT0AMI2Fzv11VXBpi3K0= Received: (qmail 91514 invoked by alias); 30 Jun 2019 21:15:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91489 invoked by uid 89); 30 Jun 2019 21:15:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=ubizjak@gmail.com, ubizjakgmailcom, U*ubizjak, sk:ubizjak X-HELO: mail-io1-f52.google.com Received: from mail-io1-f52.google.com (HELO mail-io1-f52.google.com) (209.85.166.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 30 Jun 2019 21:15:36 +0000 Received: by mail-io1-f52.google.com with SMTP id s7so24075026iob.11 for ; Sun, 30 Jun 2019 14:15:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=lF4EOVSXGJv1itXkV7TpQhm2+759SuHrKA9KVKa3BXw=; b=H+5A0JRjv8GxjkWZeMNyL8ixFVn/4VlRTnyVsE/mHPJtxCiXI1HhUNYDEveLTgxvKA bT4Jraex/9NLzx4q6OQiLjczh86HnYs91lA/BdAZIpPBYVib0BSki4ePBgU8iLhcRPjB maiur+O2nNaPq3SUOuNOZIMauIhnGfihA21aIEtcaZkcMhj7EniVRYQCsWRP6w3D7ass D0XLA7VuqOnvy+HaaIi1NjN2pBaiwtAVEuO1jMGxmEwR3xaJ2C3TKSAZmjIvR5NJ00Bl 0s1rP9O6XG7oAKgU2/0kVCJeoj9/hh5gEipXwcmL1yLRbWihBrKxGGKf+nPKtmMZ5dMh v7eQ== MIME-Version: 1.0 From: Uros Bizjak Date: Sun, 30 Jun 2019 23:15:22 +0200 Message-ID: Subject: [PATCH, i386]: Move MMX abs pattern outside normal optabs namespace To: "gcc-patches@gcc.gnu.org" As explained on top of mmx.md, MMX patterns should be defined outside the normal optabs namespace. 2019-06-30 Uroš Bizjak * config/i386/sse.md (ssse3_abs2): Rename from abs2. (abs2): New expander. * config/i386/i386-builtin.def (__builtin_ia32_pabsb): Use CODE_FOR_ssse3_absv8qi2. (__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2. (__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386-builtin.def =================================================================== --- config/i386/i386-builtin.def (revision 272833) +++ config/i386/i386-builtin.def (working copy) @@ -830,11 +830,11 @@ /* SSSE3 */ BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI) BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 272834) +++ config/i386/sse.md (working copy) @@ -16584,7 +16584,7 @@ } }) -(define_insn "abs2" +(define_insn "ssse3_abs2" [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv") (abs:MMXMODEI (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))] @@ -16599,6 +16599,12 @@ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set_attr "mode" "DI,TI")]) +(define_insn "abs2" + [(set (match_operand:MMXMODEI 0 "register_operand") + (abs:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand")))] + "TARGET_MMX_WITH_SSE && TARGET_SSSE3") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; AMD SSE4A instructions