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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.46 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:35 +0200 Message-Id: <20190624222844.26584-2-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 01/10] hw/mips/gt64xxx_pci: Fix multiline comment syntax X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 64 +++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 29 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index f707e59c7a..c0924646b5 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -248,10 +248,11 @@ typedef struct GT64120State { } GT64120State; /* Adjust range to avoid touching space which isn't mappable via PCI */ -/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 - 0x1fc00000 - 0x1fd00000 */ -static void check_reserved_space (hwaddr *start, - hwaddr *length) +/* + * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 + * 0x1fc00000 - 0x1fd00000 + */ +static void check_reserved_space(hwaddr *start, hwaddr *length) { hwaddr begin = *start; hwaddr end = *start + *length; @@ -650,8 +651,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_SDRAM_B1: case GT_SDRAM_B2: case GT_SDRAM_B3: - /* We don't simulate electrical parameters of the SDRAM. - Accept, but ignore the values. */ + /* + * We don't simulate electrical parameters of the SDRAM. + * Accept, but ignore the values. + */ s->regs[saddr] = val; break; @@ -674,8 +677,10 @@ static uint64_t gt64120_readl (void *opaque, /* CPU Configuration */ case GT_MULTI: - /* Only one GT64xxx is present on the CPU bus, return - the initial value */ + /* + * Only one GT64xxx is present on the CPU bus, return + * the initial value. + */ val = s->regs[saddr]; break; @@ -685,17 +690,18 @@ static uint64_t gt64120_readl (void *opaque, case GT_CPUERR_DATALO: case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: - /* Emulated memory has no error, always return the initial - values */ + /* Emulated memory has no error, always return the initial values. */ val = s->regs[saddr]; break; /* CPU Sync Barrier */ case GT_PCI0SYNC: case GT_PCI1SYNC: - /* Reading those register should empty all FIFO on the PCI - bus, which are not emulated. The return value should be - a random value that should be ignored. */ + /* + * Reading those register should empty all FIFO on the PCI + * bus, which are not emulated. The return value should be + * a random value that should be ignored. + */ val = 0xc000ffee; break; @@ -705,8 +711,7 @@ static uint64_t gt64120_readl (void *opaque, case GT_ECC_MEM: case GT_ECC_CALC: case GT_ECC_ERRADDR: - /* Emulated memory has no error, always return the initial - values */ + /* Emulated memory has no error, always return the initial values. */ val = s->regs[saddr]; break; @@ -785,8 +790,10 @@ static uint64_t gt64120_readl (void *opaque, case GT_SDRAM_B1: case GT_SDRAM_B2: case GT_SDRAM_B3: - /* We don't simulate electrical parameters of the SDRAM. - Just return the last written value. */ + /* + * We don't simulate electrical parameters of the SDRAM. + * Just return the last written value. + */ val = s->regs[saddr]; break; @@ -949,20 +956,20 @@ static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) slot = (pci_dev->devfn >> 3); switch (slot) { - /* PIIX4 USB */ - case 10: + /* PIIX4 USB */ + case 10: return 3; - /* AMD 79C973 Ethernet */ - case 11: + /* AMD 79C973 Ethernet */ + case 11: return 1; - /* Crystal 4281 Sound */ - case 12: + /* Crystal 4281 Sound */ + case 12: return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: + /* PCI slot 1 to 4 */ + case 18 ... 21: return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: + /* Unknown device, don't do any translation */ + default: return irq_num; } } @@ -980,8 +987,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) /* XXX: optimize */ pic_irq = piix4_dev->config[0x60 + irq_num]; if (pic_irq < 16) { - /* The pic level is the logical OR of all the PCI irqs mapped - to it */ + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { if (pic_irq == piix4_dev->config[0x60 + i]) From patchwork Mon Jun 24 22:28:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:36 +0200 Message-Id: <20190624222844.26584-3-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 02/10] hw/mips/gt64xxx_pci: Fix 'tabs' coding style issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since we'll move this code around, fix its style first: ERROR: code indent should never use tabs Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 312 +++++++++++++++++++++--------------------- 1 file changed, 156 insertions(+), 156 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c0924646b5..bbd719f091 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -38,192 +38,192 @@ #define DPRINTF(fmt, ...) #endif -#define GT_REGS (0x1000 >> 2) +#define GT_REGS (0x1000 >> 2) /* CPU Configuration */ -#define GT_CPU (0x000 >> 2) -#define GT_MULTI (0x120 >> 2) +#define GT_CPU (0x000 >> 2) +#define GT_MULTI (0x120 >> 2) /* CPU Address Decode */ -#define GT_SCS10LD (0x008 >> 2) -#define GT_SCS10HD (0x010 >> 2) -#define GT_SCS32LD (0x018 >> 2) -#define GT_SCS32HD (0x020 >> 2) -#define GT_CS20LD (0x028 >> 2) -#define GT_CS20HD (0x030 >> 2) -#define GT_CS3BOOTLD (0x038 >> 2) -#define GT_CS3BOOTHD (0x040 >> 2) -#define GT_PCI0IOLD (0x048 >> 2) -#define GT_PCI0IOHD (0x050 >> 2) -#define GT_PCI0M0LD (0x058 >> 2) -#define GT_PCI0M0HD (0x060 >> 2) -#define GT_PCI0M1LD (0x080 >> 2) -#define GT_PCI0M1HD (0x088 >> 2) -#define GT_PCI1IOLD (0x090 >> 2) -#define GT_PCI1IOHD (0x098 >> 2) -#define GT_PCI1M0LD (0x0a0 >> 2) -#define GT_PCI1M0HD (0x0a8 >> 2) -#define GT_PCI1M1LD (0x0b0 >> 2) -#define GT_PCI1M1HD (0x0b8 >> 2) -#define GT_ISD (0x068 >> 2) - -#define GT_SCS10AR (0x0d0 >> 2) -#define GT_SCS32AR (0x0d8 >> 2) -#define GT_CS20R (0x0e0 >> 2) -#define GT_CS3BOOTR (0x0e8 >> 2) - -#define GT_PCI0IOREMAP (0x0f0 >> 2) -#define GT_PCI0M0REMAP (0x0f8 >> 2) -#define GT_PCI0M1REMAP (0x100 >> 2) -#define GT_PCI1IOREMAP (0x108 >> 2) -#define GT_PCI1M0REMAP (0x110 >> 2) -#define GT_PCI1M1REMAP (0x118 >> 2) +#define GT_SCS10LD (0x008 >> 2) +#define GT_SCS10HD (0x010 >> 2) +#define GT_SCS32LD (0x018 >> 2) +#define GT_SCS32HD (0x020 >> 2) +#define GT_CS20LD (0x028 >> 2) +#define GT_CS20HD (0x030 >> 2) +#define GT_CS3BOOTLD (0x038 >> 2) +#define GT_CS3BOOTHD (0x040 >> 2) +#define GT_PCI0IOLD (0x048 >> 2) +#define GT_PCI0IOHD (0x050 >> 2) +#define GT_PCI0M0LD (0x058 >> 2) +#define GT_PCI0M0HD (0x060 >> 2) +#define GT_PCI0M1LD (0x080 >> 2) +#define GT_PCI0M1HD (0x088 >> 2) +#define GT_PCI1IOLD (0x090 >> 2) +#define GT_PCI1IOHD (0x098 >> 2) +#define GT_PCI1M0LD (0x0a0 >> 2) +#define GT_PCI1M0HD (0x0a8 >> 2) +#define GT_PCI1M1LD (0x0b0 >> 2) +#define GT_PCI1M1HD (0x0b8 >> 2) +#define GT_ISD (0x068 >> 2) + +#define GT_SCS10AR (0x0d0 >> 2) +#define GT_SCS32AR (0x0d8 >> 2) +#define GT_CS20R (0x0e0 >> 2) +#define GT_CS3BOOTR (0x0e8 >> 2) + +#define GT_PCI0IOREMAP (0x0f0 >> 2) +#define GT_PCI0M0REMAP (0x0f8 >> 2) +#define GT_PCI0M1REMAP (0x100 >> 2) +#define GT_PCI1IOREMAP (0x108 >> 2) +#define GT_PCI1M0REMAP (0x110 >> 2) +#define GT_PCI1M1REMAP (0x118 >> 2) /* CPU Error Report */ -#define GT_CPUERR_ADDRLO (0x070 >> 2) -#define GT_CPUERR_ADDRHI (0x078 >> 2) -#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ -#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ -#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ +#define GT_CPUERR_ADDRLO (0x070 >> 2) +#define GT_CPUERR_ADDRHI (0x078 >> 2) +#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ +#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ +#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ /* CPU Sync Barrier */ -#define GT_PCI0SYNC (0x0c0 >> 2) -#define GT_PCI1SYNC (0x0c8 >> 2) +#define GT_PCI0SYNC (0x0c0 >> 2) +#define GT_PCI1SYNC (0x0c8 >> 2) /* SDRAM and Device Address Decode */ -#define GT_SCS0LD (0x400 >> 2) -#define GT_SCS0HD (0x404 >> 2) -#define GT_SCS1LD (0x408 >> 2) -#define GT_SCS1HD (0x40c >> 2) -#define GT_SCS2LD (0x410 >> 2) -#define GT_SCS2HD (0x414 >> 2) -#define GT_SCS3LD (0x418 >> 2) -#define GT_SCS3HD (0x41c >> 2) -#define GT_CS0LD (0x420 >> 2) -#define GT_CS0HD (0x424 >> 2) -#define GT_CS1LD (0x428 >> 2) -#define GT_CS1HD (0x42c >> 2) -#define GT_CS2LD (0x430 >> 2) -#define GT_CS2HD (0x434 >> 2) -#define GT_CS3LD (0x438 >> 2) -#define GT_CS3HD (0x43c >> 2) -#define GT_BOOTLD (0x440 >> 2) -#define GT_BOOTHD (0x444 >> 2) -#define GT_ADERR (0x470 >> 2) +#define GT_SCS0LD (0x400 >> 2) +#define GT_SCS0HD (0x404 >> 2) +#define GT_SCS1LD (0x408 >> 2) +#define GT_SCS1HD (0x40c >> 2) +#define GT_SCS2LD (0x410 >> 2) +#define GT_SCS2HD (0x414 >> 2) +#define GT_SCS3LD (0x418 >> 2) +#define GT_SCS3HD (0x41c >> 2) +#define GT_CS0LD (0x420 >> 2) +#define GT_CS0HD (0x424 >> 2) +#define GT_CS1LD (0x428 >> 2) +#define GT_CS1HD (0x42c >> 2) +#define GT_CS2LD (0x430 >> 2) +#define GT_CS2HD (0x434 >> 2) +#define GT_CS3LD (0x438 >> 2) +#define GT_CS3HD (0x43c >> 2) +#define GT_BOOTLD (0x440 >> 2) +#define GT_BOOTHD (0x444 >> 2) +#define GT_ADERR (0x470 >> 2) /* SDRAM Configuration */ -#define GT_SDRAM_CFG (0x448 >> 2) -#define GT_SDRAM_OPMODE (0x474 >> 2) -#define GT_SDRAM_BM (0x478 >> 2) -#define GT_SDRAM_ADDRDECODE (0x47c >> 2) +#define GT_SDRAM_CFG (0x448 >> 2) +#define GT_SDRAM_OPMODE (0x474 >> 2) +#define GT_SDRAM_BM (0x478 >> 2) +#define GT_SDRAM_ADDRDECODE (0x47c >> 2) /* SDRAM Parameters */ -#define GT_SDRAM_B0 (0x44c >> 2) -#define GT_SDRAM_B1 (0x450 >> 2) -#define GT_SDRAM_B2 (0x454 >> 2) -#define GT_SDRAM_B3 (0x458 >> 2) +#define GT_SDRAM_B0 (0x44c >> 2) +#define GT_SDRAM_B1 (0x450 >> 2) +#define GT_SDRAM_B2 (0x454 >> 2) +#define GT_SDRAM_B3 (0x458 >> 2) /* Device Parameters */ -#define GT_DEV_B0 (0x45c >> 2) -#define GT_DEV_B1 (0x460 >> 2) -#define GT_DEV_B2 (0x464 >> 2) -#define GT_DEV_B3 (0x468 >> 2) -#define GT_DEV_BOOT (0x46c >> 2) +#define GT_DEV_B0 (0x45c >> 2) +#define GT_DEV_B1 (0x460 >> 2) +#define GT_DEV_B2 (0x464 >> 2) +#define GT_DEV_B3 (0x468 >> 2) +#define GT_DEV_BOOT (0x46c >> 2) /* ECC */ -#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ -#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ -#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ -#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ -#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ +#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ +#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ +#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ +#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ +#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ /* DMA Record */ -#define GT_DMA0_CNT (0x800 >> 2) -#define GT_DMA1_CNT (0x804 >> 2) -#define GT_DMA2_CNT (0x808 >> 2) -#define GT_DMA3_CNT (0x80c >> 2) -#define GT_DMA0_SA (0x810 >> 2) -#define GT_DMA1_SA (0x814 >> 2) -#define GT_DMA2_SA (0x818 >> 2) -#define GT_DMA3_SA (0x81c >> 2) -#define GT_DMA0_DA (0x820 >> 2) -#define GT_DMA1_DA (0x824 >> 2) -#define GT_DMA2_DA (0x828 >> 2) -#define GT_DMA3_DA (0x82c >> 2) -#define GT_DMA0_NEXT (0x830 >> 2) -#define GT_DMA1_NEXT (0x834 >> 2) -#define GT_DMA2_NEXT (0x838 >> 2) -#define GT_DMA3_NEXT (0x83c >> 2) -#define GT_DMA0_CUR (0x870 >> 2) -#define GT_DMA1_CUR (0x874 >> 2) -#define GT_DMA2_CUR (0x878 >> 2) -#define GT_DMA3_CUR (0x87c >> 2) +#define GT_DMA0_CNT (0x800 >> 2) +#define GT_DMA1_CNT (0x804 >> 2) +#define GT_DMA2_CNT (0x808 >> 2) +#define GT_DMA3_CNT (0x80c >> 2) +#define GT_DMA0_SA (0x810 >> 2) +#define GT_DMA1_SA (0x814 >> 2) +#define GT_DMA2_SA (0x818 >> 2) +#define GT_DMA3_SA (0x81c >> 2) +#define GT_DMA0_DA (0x820 >> 2) +#define GT_DMA1_DA (0x824 >> 2) +#define GT_DMA2_DA (0x828 >> 2) +#define GT_DMA3_DA (0x82c >> 2) +#define GT_DMA0_NEXT (0x830 >> 2) +#define GT_DMA1_NEXT (0x834 >> 2) +#define GT_DMA2_NEXT (0x838 >> 2) +#define GT_DMA3_NEXT (0x83c >> 2) +#define GT_DMA0_CUR (0x870 >> 2) +#define GT_DMA1_CUR (0x874 >> 2) +#define GT_DMA2_CUR (0x878 >> 2) +#define GT_DMA3_CUR (0x87c >> 2) /* DMA Channel Control */ -#define GT_DMA0_CTRL (0x840 >> 2) -#define GT_DMA1_CTRL (0x844 >> 2) -#define GT_DMA2_CTRL (0x848 >> 2) -#define GT_DMA3_CTRL (0x84c >> 2) +#define GT_DMA0_CTRL (0x840 >> 2) +#define GT_DMA1_CTRL (0x844 >> 2) +#define GT_DMA2_CTRL (0x848 >> 2) +#define GT_DMA3_CTRL (0x84c >> 2) /* DMA Arbiter */ -#define GT_DMA_ARB (0x860 >> 2) +#define GT_DMA_ARB (0x860 >> 2) /* Timer/Counter */ -#define GT_TC0 (0x850 >> 2) -#define GT_TC1 (0x854 >> 2) -#define GT_TC2 (0x858 >> 2) -#define GT_TC3 (0x85c >> 2) -#define GT_TC_CONTROL (0x864 >> 2) +#define GT_TC0 (0x850 >> 2) +#define GT_TC1 (0x854 >> 2) +#define GT_TC2 (0x858 >> 2) +#define GT_TC3 (0x85c >> 2) +#define GT_TC_CONTROL (0x864 >> 2) /* PCI Internal */ -#define GT_PCI0_CMD (0xc00 >> 2) -#define GT_PCI0_TOR (0xc04 >> 2) -#define GT_PCI0_BS_SCS10 (0xc08 >> 2) -#define GT_PCI0_BS_SCS32 (0xc0c >> 2) -#define GT_PCI0_BS_CS20 (0xc10 >> 2) -#define GT_PCI0_BS_CS3BT (0xc14 >> 2) -#define GT_PCI1_IACK (0xc30 >> 2) -#define GT_PCI0_IACK (0xc34 >> 2) -#define GT_PCI0_BARE (0xc3c >> 2) -#define GT_PCI0_PREFMBR (0xc40 >> 2) -#define GT_PCI0_SCS10_BAR (0xc48 >> 2) -#define GT_PCI0_SCS32_BAR (0xc4c >> 2) -#define GT_PCI0_CS20_BAR (0xc50 >> 2) -#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) -#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) -#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) -#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) -#define GT_PCI1_CMD (0xc80 >> 2) -#define GT_PCI1_TOR (0xc84 >> 2) -#define GT_PCI1_BS_SCS10 (0xc88 >> 2) -#define GT_PCI1_BS_SCS32 (0xc8c >> 2) -#define GT_PCI1_BS_CS20 (0xc90 >> 2) -#define GT_PCI1_BS_CS3BT (0xc94 >> 2) -#define GT_PCI1_BARE (0xcbc >> 2) -#define GT_PCI1_PREFMBR (0xcc0 >> 2) -#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) -#define GT_PCI1_SCS32_BAR (0xccc >> 2) -#define GT_PCI1_CS20_BAR (0xcd0 >> 2) -#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) -#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) -#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) -#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) -#define GT_PCI1_CFGADDR (0xcf0 >> 2) -#define GT_PCI1_CFGDATA (0xcf4 >> 2) -#define GT_PCI0_CFGADDR (0xcf8 >> 2) -#define GT_PCI0_CFGDATA (0xcfc >> 2) +#define GT_PCI0_CMD (0xc00 >> 2) +#define GT_PCI0_TOR (0xc04 >> 2) +#define GT_PCI0_BS_SCS10 (0xc08 >> 2) +#define GT_PCI0_BS_SCS32 (0xc0c >> 2) +#define GT_PCI0_BS_CS20 (0xc10 >> 2) +#define GT_PCI0_BS_CS3BT (0xc14 >> 2) +#define GT_PCI1_IACK (0xc30 >> 2) +#define GT_PCI0_IACK (0xc34 >> 2) +#define GT_PCI0_BARE (0xc3c >> 2) +#define GT_PCI0_PREFMBR (0xc40 >> 2) +#define GT_PCI0_SCS10_BAR (0xc48 >> 2) +#define GT_PCI0_SCS32_BAR (0xc4c >> 2) +#define GT_PCI0_CS20_BAR (0xc50 >> 2) +#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) +#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) +#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) +#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) +#define GT_PCI1_CMD (0xc80 >> 2) +#define GT_PCI1_TOR (0xc84 >> 2) +#define GT_PCI1_BS_SCS10 (0xc88 >> 2) +#define GT_PCI1_BS_SCS32 (0xc8c >> 2) +#define GT_PCI1_BS_CS20 (0xc90 >> 2) +#define GT_PCI1_BS_CS3BT (0xc94 >> 2) +#define GT_PCI1_BARE (0xcbc >> 2) +#define GT_PCI1_PREFMBR (0xcc0 >> 2) +#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) +#define GT_PCI1_SCS32_BAR (0xccc >> 2) +#define GT_PCI1_CS20_BAR (0xcd0 >> 2) +#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) +#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) +#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) +#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) +#define GT_PCI1_CFGADDR (0xcf0 >> 2) +#define GT_PCI1_CFGDATA (0xcf4 >> 2) +#define GT_PCI0_CFGADDR (0xcf8 >> 2) +#define GT_PCI0_CFGDATA (0xcfc >> 2) /* Interrupts */ -#define GT_INTRCAUSE (0xc18 >> 2) -#define GT_INTRMASK (0xc1c >> 2) -#define GT_PCI0_ICMASK (0xc24 >> 2) -#define GT_PCI0_SERR0MASK (0xc28 >> 2) -#define GT_CPU_INTSEL (0xc70 >> 2) -#define GT_PCI0_INTSEL (0xc74 >> 2) -#define GT_HINTRCAUSE (0xc98 >> 2) -#define GT_HINTRMASK (0xc9c >> 2) -#define GT_PCI0_HICMASK (0xca4 >> 2) -#define GT_PCI1_SERR1MASK (0xca8 >> 2) +#define GT_INTRCAUSE (0xc18 >> 2) +#define GT_INTRMASK (0xc1c >> 2) +#define GT_PCI0_ICMASK (0xc24 >> 2) +#define GT_PCI0_SERR0MASK (0xc28 >> 2) +#define GT_CPU_INTSEL (0xc70 >> 2) +#define GT_PCI0_INTSEL (0xc74 >> 2) +#define GT_HINTRCAUSE (0xc98 >> 2) +#define GT_HINTRMASK (0xc9c >> 2) +#define GT_PCI0_HICMASK (0xca4 >> 2) +#define GT_PCI1_SERR1MASK (0xca8 >> 2) #define PCI_MAPPING_ENTRY(regname) \ hwaddr regname ##_start; \ From patchwork Mon Jun 24 22:28:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:37 +0200 Message-Id: <20190624222844.26584-4-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 03/10] hw/mips/gt64xxx_pci: Fix 'braces' coding style issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since we'll move this code around, fix its style first: ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index bbd719f091..cfd497960c 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -257,19 +257,25 @@ static void check_reserved_space(hwaddr *start, hwaddr *length) hwaddr begin = *start; hwaddr end = *start + *length; - if (end >= 0x1e000000LL && end < 0x1f100000LL) + if (end >= 0x1e000000LL && end < 0x1f100000LL) { end = 0x1e000000LL; - if (begin >= 0x1e000000LL && begin < 0x1f100000LL) + } + if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { begin = 0x1f100000LL; - if (end >= 0x1fc00000LL && end < 0x1fd00000LL) + } + if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { end = 0x1fc00000LL; - if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) + } + if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { begin = 0x1fd00000LL; + } /* XXX: This is broken when a reserved range splits the requested range */ - if (end >= 0x1f100000LL && begin < 0x1e000000LL) + if (end >= 0x1f100000LL && begin < 0x1e000000LL) { end = 0x1e000000LL; - if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) + } + if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { end = 0x1fc00000LL; + } *start = begin; *length = end - begin; @@ -385,8 +391,9 @@ static void gt64120_writel (void *opaque, hwaddr addr, PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t saddr; - if (!(s->regs[GT_CPU] & 0x00001000)) + if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); + } saddr = (addr & 0xfff) >> 2; switch (saddr) { @@ -937,8 +944,9 @@ static uint64_t gt64120_readl (void *opaque, break; } - if (!(s->regs[GT_CPU] & 0x00001000)) + if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); + } return val; } @@ -990,8 +998,9 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[0x60 + i]) + if (pic_irq == piix4_dev->config[0x60 + i]) { pic_level |= pci_irq_levels[i]; + } } qemu_set_irq(pic[pic_irq], pic_level); } From patchwork Mon Jun 24 22:28:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:38 +0200 Message-Id: <20190624222844.26584-5-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 04/10] hw/mips/gt64xxx_pci: Fix 'spaces' coding style issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since we'll move this code around, fix its style first: ERROR: space prohibited between function name and open parenthesis ERROR: line over 90 characters Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index cfd497960c..0b9fb02475 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -384,8 +384,8 @@ static const VMStateDescription vmstate_gt64120 = { } }; -static void gt64120_writel (void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void gt64120_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); @@ -671,8 +671,8 @@ static void gt64120_writel (void *opaque, hwaddr addr, } } -static uint64_t gt64120_readl (void *opaque, - hwaddr addr, unsigned size) +static uint64_t gt64120_readl(void *opaque, + hwaddr addr, unsigned size) { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); @@ -1193,7 +1193,8 @@ PCIBus *gt64120_register(qemu_irq *pic) get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); qdev_init_nofail(dev); - memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000); + memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, + "isd-mem", 0x1000); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); return phb->bus; From patchwork Mon Jun 24 22:28:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:39 +0200 Message-Id: <20190624222844.26584-6-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 05/10] hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 48 +++++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 0b9fb02475..f44326f14f 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -23,6 +23,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/mips/mips.h" #include "hw/pci/pci.h" @@ -466,12 +467,20 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* CPU Sync Barrier */ case GT_PCI0SYNC: case GT_PCI1SYNC: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* SDRAM and Device Address Decode */ @@ -510,7 +519,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_DEV_B3: case GT_DEV_BOOT: /* Not implemented */ - DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented device register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* ECC */ @@ -520,6 +532,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_ECC_CALC: case GT_ECC_ERRADDR: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* DMA Record */ @@ -543,23 +559,20 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_DMA1_CUR: case GT_DMA2_CUR: case GT_DMA3_CUR: - /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); - break; /* DMA Channel Control */ case GT_DMA0_CTRL: case GT_DMA1_CTRL: case GT_DMA2_CTRL: case GT_DMA3_CTRL: - /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); - break; /* DMA Arbiter */ case GT_DMA_ARB: /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented DMA register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* Timer/Counter */ @@ -569,7 +582,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_TC3: case GT_TC_CONTROL: /* Not implemented */ - DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented timer register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* PCI Internal */ @@ -610,6 +626,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI1_CFGADDR: case GT_PCI1_CFGDATA: /* not implemented */ + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented timer register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; case GT_PCI0_CFGADDR: phb->config_reg = val & 0x80fffffc; @@ -666,7 +686,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, break; default: - DPRINTF ("Bad register offset 0x%x\n", (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Illegal register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; } } @@ -940,7 +963,10 @@ static uint64_t gt64120_readl(void *opaque, default: val = s->regs[saddr]; - DPRINTF ("Bad register offset 0x%x\n", (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Illegal register read " + "reg:0x03%x size:%u value:0x%0*x\n", + saddr << 2, size, size << 1, val); break; } From patchwork Mon Jun 24 22:28:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MGuAyROE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45Xkt50kQFz9s5c for ; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 06/10] hw/mips/gt64xxx_pci: Convert debug printf()s to trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- Makefile.objs | 1 + hw/mips/gt64xxx_pci.c | 29 ++++++++++------------------- hw/mips/trace-events | 4 ++++ 3 files changed, 15 insertions(+), 19 deletions(-) create mode 100644 hw/mips/trace-events diff --git a/Makefile.objs b/Makefile.objs index 658cfc9d9f..3b83621f32 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -163,6 +163,7 @@ trace-events-subdirs += hw/input trace-events-subdirs += hw/intc trace-events-subdirs += hw/isa trace-events-subdirs += hw/mem +trace-events-subdirs += hw/mips trace-events-subdirs += hw/misc trace-events-subdirs += hw/misc/macio trace-events-subdirs += hw/net diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index f44326f14f..815ef0711d 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -30,14 +30,7 @@ #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" #include "exec/address-spaces.h" - -//#define DEBUG - -#ifdef DEBUG -#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) -#else -#define DPRINTF(fmt, ...) -#endif +#include "trace.h" #define GT_REGS (0x1000 >> 2) @@ -294,9 +287,7 @@ static void gt64120_isd_mapping(GT64120State *s) check_reserved_space(&start, &length); length = 0x1000; /* Map new address */ - DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx - " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n", - s->ISD_length, s->ISD_start, length, start); + trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start); s->ISD_start = start; s->ISD_length = length; memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); @@ -648,19 +639,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); - DPRINTF("INTRCAUSE %" PRIx64 "\n", val); + trace_gt64120_write("INTRCAUSE", size << 1, val); break; case GT_INTRMASK: s->regs[saddr] = val & 0x3c3ffffe; - DPRINTF("INTRMASK %" PRIx64 "\n", val); + trace_gt64120_write("INTRMASK", size << 1, val); break; case GT_PCI0_ICMASK: s->regs[saddr] = val & 0x03fffffe; - DPRINTF("ICMASK %" PRIx64 "\n", val); + trace_gt64120_write("ICMASK", size << 1, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] = val & 0x0000003f; - DPRINTF("SERR0MASK %" PRIx64 "\n", val); + trace_gt64120_write("SERR0MASK", size << 1, val); break; /* Reserved when only PCI_0 is configured. */ @@ -936,19 +927,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val = s->regs[saddr]; - DPRINTF("INTRCAUSE %x\n", val); + trace_gt64120_read("INTRCAUSE", size << 1, val); break; case GT_INTRMASK: val = s->regs[saddr]; - DPRINTF("INTRMASK %x\n", val); + trace_gt64120_read("INTRMASK", size << 1, val); break; case GT_PCI0_ICMASK: val = s->regs[saddr]; - DPRINTF("ICMASK %x\n", val); + trace_gt64120_read("ICMASK", size << 1, val); break; case GT_PCI0_SERR0MASK: val = s->regs[saddr]; - DPRINTF("SERR0MASK %x\n", val); + trace_gt64120_read("SERR0MASK", size << 1, val); break; /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events new file mode 100644 index 0000000000..75d4c73f2e --- /dev/null +++ b/hw/mips/trace-events @@ -0,0 +1,4 @@ +# gt64xxx.c +gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64 +gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64 +gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 From patchwork Mon Jun 24 22:28:41 2019 Content-Type: text/plain; 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:41 +0200 Message-Id: <20190624222844.26584-8-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 07/10] hw/mips/gt64xxx_pci: Align the pci0-mem size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" One byte is missing, use an aligned size. (qemu) info mtree memory-region: pci0-mem 0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 815ef0711d..2fa313f498 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -23,6 +23,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qemu/log.h" #include "hw/hw.h" #include "hw/mips/mips.h" @@ -1201,7 +1202,7 @@ PCIBus *gt64120_register(qemu_irq *pic) dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); d = GT64120_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); - memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX); + memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); phb->bus = pci_register_root_bus(dev, "pci", gt64120_pci_set_irq, gt64120_pci_map_irq, From patchwork Mon Jun 24 22:28:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CO6zLsdQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45Xkb34bz2z9s8m for ; Tue, 25 Jun 2019 08:33:19 +1000 (AEST) Received: from localhost ([::1]:55098 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfXWX-0007G0-Ma for incoming@patchwork.ozlabs.org; Mon, 24 Jun 2019 18:33:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34179) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfXSP-0004C3-O9 for qemu-devel@nongnu.org; Mon, 24 Jun 2019 18:29:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfXSO-0005P2-6g for qemu-devel@nongnu.org; Mon, 24 Jun 2019 18:29:01 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:35469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hfXSN-0005Le-Tj for qemu-devel@nongnu.org; Mon, 24 Jun 2019 18:29:00 -0400 Received: by mail-wm1-x344.google.com with SMTP id c6so891944wml.0 for ; Mon, 24 Jun 2019 15:28:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rT3WvtpigTN3xO4aUvjlhGu30zqDl1BA3eirdCSenGY=; b=CO6zLsdQmYkw/tpmJ7ZdO1Nni8NIkxXbjZGZYfilr2ULrHk8LveGwlyYo2qx+pz7lq KLPbpO0UudAjz8NuiD+ZKllK0LCHioqqopIavypky0k7UB+tyAwITlhdn+WZjW/r7Jn3 Es7N9S7p+ATy2bR/cbhfREGgai03TY8XkSVEixkAd/4+pJlK78TQCiMeyTJug5BmOkY/ 0duahjtOA/dNOphAyZIra7O9aBPmLwLxuN/j716KzUVIuUGUsE13fmKFyuM+ODvZIdeZ wxGzVokWYHbeRcSvWoGq+7CxW2YVI7+GagjaWsGeKnKo5/8r6PPEkPJue/UDr/WPcH1G mIWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rT3WvtpigTN3xO4aUvjlhGu30zqDl1BA3eirdCSenGY=; b=Y6b4eFtgT5Ibi7JlfvroARR/eYqKKnU/G+EeBAZkJK7rCGlrlRHbcZ1wUn3kP3wiLu XVb+FGjuLT5BS2pJOVZSy6Ii+baJP5YEgKE9Z2gXCmiriToY/2MI5LKpccICIq1UQy37 Ddmaq2+143xn4Z3ShmA5GjMn1KbbWugatdUZ/toRiJjShOqahrqBZuSSNFO9dn+oI6Yd 4Ubb1AE2ca0/L6bao5rLgJG8Fjr6IRtLJDaIeV79ksR0OAgZqEf6v1l+PPdeDMxDM5qq i2a+/83fs8GKn2+C8RsSpakcuJFFbvNSM6aU6hlWP+7NJM3jZ/p8tURxqoV51TQVvcL7 SPHg== X-Gm-Message-State: APjAAAWblHizphsRcbh9NxhT4YvvNkfbNTzla/Kx6jWvPRvBoPVxK0cC WhxbkLrsFcVj1RbNB1sHbQY0OT1G X-Google-Smtp-Source: APXvYqw3EwM8fMiInZQV7ll8rHWM61Hjlqs3BlBBIZ/7Lmsk4FpnR4dMsgb0K46PIERkNBUHv/HX/g== X-Received: by 2002:a1c:c2d5:: with SMTP id s204mr17776629wmf.174.1561415336828; Mon, 24 Jun 2019 15:28:56 -0700 (PDT) Received: from x1.local (183.red-88-21-202.staticip.rima-tde.net. [88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.55 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:42 +0200 Message-Id: <20190624222844.26584-9-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 08/10] hw/mips/gt64xxx_pci: Add a 'cpu_big_endian' qdev property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This device does not have to be TARGET-dependent. Add a 'cpu_big_endian' property which sets the byte-swapping options if required. Signed-off-by: Philippe Mathieu-Daudé --- I might change my mind and name it 'little_endian' to be closer to the datasheet. --- include/hw/mips/mips.h | 2 +- hw/mips/gt64xxx_pci.c | 29 +++++++++++++---------------- hw/mips/mips_malta.c | 2 +- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 2f6774d540..6ec41d33f1 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -9,7 +9,7 @@ #include "hw/irq.h" /* gt64xxx.c */ -PCIBus *gt64120_register(qemu_irq *pic); +PCIBus *gt64120_create(qemu_irq *pic, bool target_is_bigendian); /* bonito.c */ PCIBus *bonito_init(qemu_irq *pic); diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 2fa313f498..5209038ee5 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -240,6 +240,7 @@ typedef struct GT64120State { PCI_MAPPING_ENTRY(ISD); MemoryRegion pci0_mem; AddressSpace pci0_mem_as; + bool cpu_big_endian; } GT64120State; /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -1028,15 +1029,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) static void gt64120_reset(DeviceState *dev) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); + const uint32_t pci_cmd = s->cpu_big_endian ? 0x00000000 : 0x00010001; /* FIXME: Malta specific hw assumptions ahead */ /* CPU Configuration */ -#ifdef TARGET_WORDS_BIGENDIAN - s->regs[GT_CPU] = 0x00000000; -#else - s->regs[GT_CPU] = 0x00001000; -#endif + s->regs[GT_CPU] = !s->cpu_big_endian << 12; s->regs[GT_MULTI] = 0x00000003; /* CPU Address decode */ @@ -1143,11 +1141,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_TC_CONTROL] = 0x00000000; /* PCI Internal */ -#ifdef TARGET_WORDS_BIGENDIAN - s->regs[GT_PCI0_CMD] = 0x00000000; -#else - s->regs[GT_PCI0_CMD] = 0x00010001; -#endif + s->regs[GT_PCI0_CMD] = pci_cmd; s->regs[GT_PCI0_TOR] = 0x0000070f; s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; @@ -1164,11 +1158,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; -#ifdef TARGET_WORDS_BIGENDIAN - s->regs[GT_PCI1_CMD] = 0x00000000; -#else - s->regs[GT_PCI1_CMD] = 0x00010001; -#endif + s->regs[GT_PCI1_CMD] = pci_cmd; s->regs[GT_PCI1_TOR] = 0x0000070f; s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; @@ -1193,13 +1183,14 @@ static void gt64120_reset(DeviceState *dev) gt64120_pci_mapping(s); } -PCIBus *gt64120_register(qemu_irq *pic) +PCIBus *gt64120_create(qemu_irq *pic, bool target_is_bigendian) { GT64120State *d; PCIHostState *phb; DeviceState *dev; dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); + qdev_prop_set_bit(dev, "cpu_big_endian", target_is_bigendian); d = GT64120_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); @@ -1262,6 +1253,11 @@ static const TypeInfo gt64120_pci_info = { }, }; +static Property gt64120_properties[] = { + DEFINE_PROP_BOOL("cpu_big_endian", GT64120State, cpu_big_endian, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void gt64120_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1269,6 +1265,7 @@ static void gt64120_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset = gt64120_reset; dc->vmsd = &vmstate_gt64120; + dc->props = gt64120_properties; } static const TypeInfo gt64120_info = { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 51db5212be..97f8ffbf1b 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1375,7 +1375,7 @@ void mips_malta_init(MachineState *machine) isa_irq = qemu_irq_proxy(&s->i8259, 16); /* Northbridge */ - pci_bus = gt64120_register(isa_irq); + pci_bus = gt64120_create(isa_irq, be); /* Southbridge */ ide_drive_get(hd, ARRAY_SIZE(hd)); From patchwork Mon Jun 24 22:28:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1121567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:43 +0200 Message-Id: <20190624222844.26584-10-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 09/10] hw/mips/gt64xxx_pci: Move it to hw/pci-host/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The GT-64120 is a north-bridge, and it is not MIPS specific. Move it with the other north-bridge devices. We move this device in the common-obj, and compile it once for the 4 different MIPS targets. Signed-off-by: Philippe Mathieu-Daudé --- hw/{mips/gt64xxx_pci.c => pci-host/gt64120.c} | 0 MAINTAINERS | 2 +- hw/mips/Makefile.objs | 2 +- hw/mips/trace-events | 4 ---- hw/pci-host/Makefile.objs | 2 +- hw/pci-host/trace-events | 5 +++++ 6 files changed, 8 insertions(+), 7 deletions(-) rename hw/{mips/gt64xxx_pci.c => pci-host/gt64120.c} (100%) diff --git a/hw/mips/gt64xxx_pci.c b/hw/pci-host/gt64120.c similarity index 100% rename from hw/mips/gt64xxx_pci.c rename to hw/pci-host/gt64120.c diff --git a/MAINTAINERS b/MAINTAINERS index abef4a1cfc..da348e1af1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -928,7 +928,7 @@ M: Aurelien Jarno R: Aleksandar Rikalo S: Maintained F: hw/mips/mips_malta.c -F: hw/mips/gt64xxx_pci.c +F: hw/pci-host/gt64120.c F: tests/acceptance/linux_ssh_mips_malta.py Mipssim diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs index 525809af07..da65e19c20 100644 --- a/hw/mips/Makefile.objs +++ b/hw/mips/Makefile.objs @@ -1,6 +1,6 @@ obj-y += addr.o mips_int.o obj-$(CONFIG_R4K) += mips_r4k.o -obj-$(CONFIG_MALTA) += gt64xxx_pci.o mips_malta.o +obj-$(CONFIG_MALTA) += mips_malta.o obj-$(CONFIG_MIPSSIM) += mips_mipssim.o obj-$(CONFIG_JAZZ) += mips_jazz.o obj-$(CONFIG_FULONG) += mips_fulong2e.o diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 75d4c73f2e..e69de29bb2 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +0,0 @@ -# gt64xxx.c -gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64 -gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64 -gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index a9cd3e022d..3e1657774d 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -17,5 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o - +common-obj-$(CONFIG_MALTA) += gt64120.o common-obj-$(CONFIG_PCI_EXPRESS_DESIGNWARE) += designware.o diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index d19ca9aef6..eecc233670 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -20,3 +20,8 @@ unin_data_write(uint64_t addr, unsigned len, uint64_t val) "write addr 0x%"PRIx6 unin_data_read(uint64_t addr, unsigned len, uint64_t val) "read addr 0x%"PRIx64 " len %d val 0x%"PRIx64 unin_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64 unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64 + +# gt64120.c +gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64 +gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64 +gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 From patchwork Mon Jun 24 22:28:44 2019 Content-Type: text/plain; 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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.58 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:44 +0200 Message-Id: <20190624222844.26584-11-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [RFC PATCH 10/10] hw/pci-host/gt64120: Clean the decoded address space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The SysAd bus is split in various address spaces. Declare the different regions separately, this helps a lot while tracing different access while debugging. We also add the PCI1 ranges. See 'GT-64120A System Controller' datasheet Rev, 1.1, "Table 15: CPU and Device Decoder Default Address Mapping" Signed-off-by: Philippe Mathieu-Daudé --- While this device is modelled toward the Malta board, it is generic. --- hw/mips/mips_malta.c | 6 ------ hw/pci-host/gt64120.c | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 97f8ffbf1b..d6e4a0dad9 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -53,7 +53,6 @@ #include "sysemu/qtest.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/misc/empty_slot.h" #include "sysemu/kvm.h" #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" @@ -1209,11 +1208,6 @@ void mips_malta_init(MachineState *machine) DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); MaltaState *s = MIPS_MALTA(dev); - /* The whole address space decoded by the GT-64120A doesn't generate - exception when accessing invalid memory. Create an empty slot to - emulate this feature. */ - empty_slot_init("gt64120-ad", 0x00000000, 0x20000000); - qdev_init_nofail(dev); /* create CPU */ diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 5209038ee5..6eaa571994 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -31,6 +31,8 @@ #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" #include "exec/address-spaces.h" +#include "hw/misc/empty_slot.h" +#include "hw/misc/unimp.h" #include "trace.h" #define GT_REGS (0x1000 >> 2) @@ -1206,6 +1208,23 @@ PCIBus *gt64120_create(qemu_irq *pic, bool target_is_bigendian) "isd-mem", 0x1000); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); + + create_unimplemented_device("gt64120_i2o", 0x14000000, 256); + + empty_slot_init("SCS0", 0x00000000, 8 * MiB); + empty_slot_init("SCS1", 0x00800000, 8 * MiB); + empty_slot_init("SCS2", 0x01000000, 8 * MiB); + empty_slot_init("SCS3", 0x01800000, 8 * MiB); + empty_slot_init("CS0", 0x1c000000, 8 * MiB); + empty_slot_init("CS1", 0x1c800000, 8 * MiB); + empty_slot_init("CS2", 0x1d000000, 32 * MiB); + empty_slot_init("CS3", 0x1f000000, 12 * MiB); + empty_slot_init("BootCS", 0x1fc00000, 4 * MiB); + + create_unimplemented_device("pci1-io", 0x20000000, 32 * MiB); + empty_slot_init("pci1-mem0", 0x22000000, 32 * MiB); + empty_slot_init("pci1-mem1", 0x24000000, 32 * MiB); + return phb->bus; }