From patchwork Tue Jun 18 19:05:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 1118300 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="LyfwHlcx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SyGR11nHz9sNm for ; Wed, 19 Jun 2019 05:05:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730508AbfFRTFu (ORCPT ); Tue, 18 Jun 2019 15:05:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:40582 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730196AbfFRTFu (ORCPT ); Tue, 18 Jun 2019 15:05:50 -0400 Received: from localhost.localdomain (unknown [194.230.155.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6D84F21530; Tue, 18 Jun 2019 19:05:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560884749; bh=BvA/9DF1WByazKjkGl4tvLr+zpiufLyyUe+O5JplvCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LyfwHlcxCBc3ms/kUd8Tw2+f+1Fe1vVA+hpUQYSD0AUGW94f1PXLud4tgspSo49op dLx48kyh+AjY1of6Sb9Qz196Bhsr9V9W8BqjVph+o/W5MvPpWmaLlYKMRl54OqbTUx +F1eDDmt5xil1fyM1R92vxlvoo2DwhSW7SU6tw0o= From: Krzysztof Kozlowski To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Kukjin Kim , Catalin Marinas , Will Deacon , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Marek Szyprowski , Olof Johansson , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: Joseph Kogut , Arnd Bergmann , Bartlomiej Zolnierkiewicz , Inki Dae , Krzysztof Kozlowski Subject: [RFT 01/10] dt-bindings: gpu: mali: Add Samsung compatibles for Midgard and Utgard Date: Tue, 18 Jun 2019 21:05:25 +0200 Message-Id: <20190618190534.4951-2-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190618190534.4951-1-krzk@kernel.org> References: <20190618190534.4951-1-krzk@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add vendor compatibles for specific implementation of Mali Utgard (Exynos3250, Exynos4-family) and Midgard (Exynos5433, Exynos7). Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 1 + Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index e5ad3b2afe17..9b298edec5b2 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -17,6 +17,7 @@ Required properties: * which must be preceded by one of the following vendor specifics: + "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + + "samsung,exynos5433-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index ae63f09fda7d..519018cb860b 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -17,6 +17,7 @@ Required properties: + amlogic,meson8b-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali + + samsung,exynos3250-mali + rockchip,rk3036-mali + rockchip,rk3066-mali + rockchip,rk3188-mali From patchwork Tue Jun 18 19:05:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 1118302 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="kdKwCHQU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SyGc2qGbz9sNR for ; Wed, 19 Jun 2019 05:06:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730532AbfFRTFz (ORCPT ); Tue, 18 Jun 2019 15:05:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:40758 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730196AbfFRTFz (ORCPT ); Tue, 18 Jun 2019 15:05:55 -0400 Received: from localhost.localdomain (unknown [194.230.155.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 80B6320863; Tue, 18 Jun 2019 19:05:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560884754; bh=jXXvRsijbHdSjSp46+Gnvv9t0hiH6dZfxuMdrgfPP4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kdKwCHQUekeguYgskUHWlqZI387UPs/rDnQ++hEuIb/RZ0SAIcp1KCiVR1w1pA3Df gExJXnw7TirweJC2pIbed4utGYBVQRdlTWk8cNaqnvu7mDOpPqpWaJ7FG8te0lY5Fk oAbz/68kBa/rXtsrkw+qx4RwNxAbnbF8PikOriDc= From: Krzysztof Kozlowski To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Kukjin Kim , Catalin Marinas , Will Deacon , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Marek Szyprowski , Olof Johansson , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: Joseph Kogut , Arnd Bergmann , Bartlomiej Zolnierkiewicz , Inki Dae , Krzysztof Kozlowski Subject: [RFT 02/10] clk: samsung: Add bus clock for GPU/G3D on Exynos4412 Date: Tue, 18 Jun 2019 21:05:26 +0200 Message-Id: <20190618190534.4951-3-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190618190534.4951-1-krzk@kernel.org> References: <20190618190534.4951-1-krzk@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 1 + include/dt-bindings/clock/exynos4.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index d2a68a792a21..ed4af7da9c4f 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -961,6 +961,7 @@ static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { /* list of gate clocks supported in exynos4x12 soc */ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { + GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0), GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index a0439ce8e8d3..88ec3968b90a 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -187,6 +187,7 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 +#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */