From patchwork Tue Jun 18 07:46:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="py24H3zS"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDk29dqz9s4V for ; Tue, 18 Jun 2019 17:48:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727584AbfFRHqk (ORCPT ); Tue, 18 Jun 2019 03:46:40 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14088 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725870AbfFRHqj (ORCPT ); Tue, 18 Jun 2019 03:46:39 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:38 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:38 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:38 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:37 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:37 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during suspend Date: Tue, 18 Jun 2019 00:46:15 -0700 Message-ID: <1560843991-24123-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560843998; bh=tvQslV53EocwPwpfbzGR9nKs+VHwI0rTa6hb/3PMnzs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=py24H3zSsCh8vv5XIuecFN8vBKIfcKLB9Ef4V5fvur/MzQXWl45QCvRxP818KqWxE inVizr59zaN7EAtq0t8/39FeJskarrLcpFdSdIFHFPmdoA2Bf9hfw6unz+MQDYFvwW +WOPoYER0cGVRSL9W81Xd8bgyvk39dlZG/uszlhYKJvMxBDdoTZ+5fvvr3aiHWSdVW Tr3CPVztngIOsXKPv8bkMgmUy8e/5NK0EaDwJKXYB0sSfRc/Utfsyn+M4BCfLb1XIE v02mIC4XkH2pyCNoM5hIC94oH85917Upn0Wrn186s9hIPfG++kEMiOlNLnh0/xSYgr 43UaYgdmjEgnQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry sequence and sc7 entry firmware is run from COP/BPMP-Lite. So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence for Tegra210. This patch has fix for leaving the COP IRQ enabled for Tegra210 during interrupt controller suspend operation. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/irqchip/irq-tegra.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c index e1f771c72fc4..cf0c07052064 100644 --- a/drivers/irqchip/irq-tegra.c +++ b/drivers/irqchip/irq-tegra.c @@ -44,18 +44,22 @@ static unsigned int num_ictlrs; struct tegra_ictlr_soc { unsigned int num_ictlrs; + bool supports_sc7; }; static const struct tegra_ictlr_soc tegra20_ictlr_soc = { .num_ictlrs = 4, + .supports_sc7 = false, }; static const struct tegra_ictlr_soc tegra30_ictlr_soc = { .num_ictlrs = 5, + .supports_sc7 = false, }; static const struct tegra_ictlr_soc tegra210_ictlr_soc = { .num_ictlrs = 6, + .supports_sc7 = true, }; static const struct of_device_id ictlr_matches[] = { @@ -67,6 +71,7 @@ static const struct of_device_id ictlr_matches[] = { struct tegra_ictlr_info { void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; + const struct tegra_ictlr_soc *soc; #ifdef CONFIG_PM_SLEEP u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; @@ -147,8 +152,19 @@ static int tegra_ictlr_suspend(void) lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); - /* Disable COP interrupts */ - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); + /* + * AVP/COP/BPMP-Lite is the Tegra boot processor. + * + * Tegra210 system suspend flow uses sc7entry firmware which + * is executed by COP/BPMP and it includes disabling COP IRQ, + * clamping CPU rail, turning off VDD_CPU, and preparing the + * system to go to SC7/LP0. + * + * COP/BPMP wakes up when COP IRQ is triggered and runs + * sc7entry-firmware. So need to keep COP interrupt enabled. + */ + if (!lic->soc->supports_sc7) + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); /* Disable CPU interrupts */ writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); @@ -339,6 +355,7 @@ static int __init tegra_ictlr_init(struct device_node *node, goto out_unmap; } + lic->soc = soc; tegra_ictlr_syscore_init(); pr_info("%pOF: %d interrupts forwarded to %pOF\n", From patchwork Tue Jun 18 07:46:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117704 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="j6VfsFP+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDW6Z1tz9s9y for ; Tue, 18 Jun 2019 17:48:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728815AbfFRHqq (ORCPT ); Tue, 18 Jun 2019 03:46:46 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9678 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728705AbfFRHqo (ORCPT ); Tue, 18 Jun 2019 03:46:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:41 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:40 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:40 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support Date: Tue, 18 Jun 2019 00:46:16 -0700 Message-ID: <1560843991-24123-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844001; bh=We6H6QZmq3ulWraKmNFRrGEHqkAGeKtjqQtDHViMyOg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=j6VfsFP+B5u1nHhsq13nAS0XmBO+zzY/4I6MCwQSgAYNSnqVuw8vcYKPzhK/NKsYD YLY3UrGD3y7KfRc0eLbFruN3yj9JLY2RJf5184K48DSqy8EuX0QsImFOJe4VBea9mw In3ELIosMCHaI/7BnQadpOl0EZrAE4N7SYFNaFhHFd3ehHhWDPlYzKfMX4YWb7R6lx Lf63DwqavQA9boLuOv0eG1jmlV8XgAOUeK5HL/T8JsDGfqzpkXkNOALneXtPsydIjn 5dtf6n0b8tLt0SSuZS63sMOkzLcjkEDF/rLWtil2tPX2zI1WL5vrwBTlhjqWCdj6TG r9QheNo0H0YyA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds suspend and resume support for Tegra pinctrl driver and registers them to syscore so the pinmux settings are restored before the devices resume. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++ drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 + drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 + drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 + drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++ drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 + 7 files changed, 84 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 34596b246578..ceced30d8bd1 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -20,11 +20,16 @@ #include #include #include +#include #include "../core.h" #include "../pinctrl-utils.h" #include "pinctrl-tegra.h" +#define EMMC2_PAD_CFGPADCTRL_0 0x1c8 +#define EMMC4_PAD_CFGPADCTRL_0 0x1e0 +#define EMMC_DPD_PARKING (0x1fff << 14) + static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) { return readl(pmx->regs[bank] + reg); @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) pmx_writel(pmx, val, g->mux_bank, g->mux_reg); } } + + if (pmx->soc->has_park_padcfg) { + val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0); + val &= ~EMMC_DPD_PARKING; + pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0); + + val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0); + val &= ~EMMC_DPD_PARKING; + pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0); + } +} + +int __maybe_unused tegra_pinctrl_suspend(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + int i, j; + + for (i = 0; i < pmx->nbanks; i++) { + regs = pmx->regs[i]; + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++) + *backup_regs++ = readl(regs++); + } + + return pinctrl_force_sleep(pmx->pctl); +} + +int __maybe_unused tegra_pinctrl_resume(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + int i, j; + + for (i = 0; i < pmx->nbanks; i++) { + regs = pmx->regs[i]; + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++) + writel(*backup_regs++, regs++); + } + + return 0; } static bool gpio_node_has_range(const char *compatible) @@ -645,6 +692,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, int i; const char **group_pins; int fn, gn, gfn; + unsigned long backup_regs_size = 0; pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) @@ -697,6 +745,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, res = platform_get_resource(pdev, IORESOURCE_MEM, i); if (!res) break; + backup_regs_size += resource_size(res); } pmx->nbanks = i; @@ -705,11 +754,24 @@ int tegra_pinctrl_probe(struct platform_device *pdev, if (!pmx->regs) return -ENOMEM; + pmx->reg_bank_size = devm_kcalloc(&pdev->dev, pmx->nbanks, + sizeof(*pmx->reg_bank_size), + GFP_KERNEL); + if (!pmx->reg_bank_size) + return -ENOMEM; + + pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, + GFP_KERNEL); + if (!pmx->backup_regs) + return -ENOMEM; + for (i = 0; i < pmx->nbanks; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pmx->regs[i])) return PTR_ERR(pmx->regs[i]); + + pmx->reg_bank_size[i] = resource_size(res); } pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 287702660783..d63e472ee0e1 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -17,6 +17,8 @@ struct tegra_pmx { int nbanks; void __iomem **regs; + size_t *reg_bank_size; + u32 *backup_regs; }; enum tegra_pinconf_param { @@ -191,8 +193,11 @@ struct tegra_pinctrl_soc_data { bool hsm_in_mux; bool schmitt_in_mux; bool drvtype_in_mux; + bool has_park_padcfg; }; int tegra_pinctrl_probe(struct platform_device *pdev, const struct tegra_pinctrl_soc_data *soc_data); +int __maybe_unused tegra_pinctrl_suspend(struct device *dev); +int __maybe_unused tegra_pinctrl_resume(struct device *dev); #endif diff --git a/drivers/pinctrl/tegra/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c index 762151f17a88..06ea8164df9d 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra114.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c @@ -1841,6 +1841,7 @@ static const struct tegra_pinctrl_soc_data tegra114_pinctrl = { .hsm_in_mux = false, .schmitt_in_mux = false, .drvtype_in_mux = false, + .has_park_padcfg = false, }; static int tegra114_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c index 930c43758c92..abc8fe92d154 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra124.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c @@ -2053,6 +2053,7 @@ static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { .hsm_in_mux = false, .schmitt_in_mux = false, .drvtype_in_mux = false, + .has_park_padcfg = false, }; static int tegra124_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index 4b7837e38fb5..993b82cbfba7 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -2223,6 +2223,7 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { .hsm_in_mux = false, .schmitt_in_mux = false, .drvtype_in_mux = false, + .has_park_padcfg = false, }; static const char *cdev1_parents[] = { diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 0b56ad5c9c1c..10e8a2ec8094 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -1555,6 +1555,7 @@ static const struct tegra_pinctrl_soc_data tegra210_pinctrl = { .hsm_in_mux = true, .schmitt_in_mux = true, .drvtype_in_mux = true, + .has_park_padcfg = true, }; static int tegra210_pinctrl_probe(struct platform_device *pdev) @@ -1562,6 +1563,17 @@ static int tegra210_pinctrl_probe(struct platform_device *pdev) return tegra_pinctrl_probe(pdev, &tegra210_pinctrl); } +#ifdef CONFIG_PM_SLEEP +static const struct dev_pm_ops tegra_pinctrl_pm = { + .suspend = &tegra_pinctrl_suspend, + .resume = &tegra_pinctrl_resume +}; + +#define TEGRA_PINCTRL_PM (&tegra_pinctrl_pm) +#else +#define TEGRA_PINCTRL_PM NULL +#endif + static const struct of_device_id tegra210_pinctrl_of_match[] = { { .compatible = "nvidia,tegra210-pinmux", }, { }, @@ -1571,6 +1583,7 @@ static struct platform_driver tegra210_pinctrl_driver = { .driver = { .name = "tegra210-pinctrl", .of_match_table = tegra210_pinctrl_of_match, + .pm = TEGRA_PINCTRL_PM, }, .probe = tegra210_pinctrl_probe, }; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c index 610124c3d192..779ee40e5f21 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra30.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c @@ -2476,6 +2476,7 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = { .hsm_in_mux = false, .schmitt_in_mux = false, .drvtype_in_mux = false, + .has_park_padcfg = false, }; static int tegra30_pinctrl_probe(struct platform_device *pdev) From patchwork Tue Jun 18 07:46:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="jGud0Hqr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDd4BPTz9s00 for ; Tue, 18 Jun 2019 17:48:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728736AbfFRHsL (ORCPT ); Tue, 18 Jun 2019 03:48:11 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9689 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725870AbfFRHqp (ORCPT ); Tue, 18 Jun 2019 03:46:45 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:43 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:43 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:43 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:43 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 03/17] gpio: tegra: use resume_noirq for tegra gpio resume Date: Tue, 18 Jun 2019 00:46:17 -0700 Message-ID: <1560843991-24123-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844003; bh=Pr7vcEZPGjVmliq8J2fR0U6t7tGM+0Ul14bqoyMQjC8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jGud0Hqrlsdyja3FOUV8qfAb9/4AjvqCEy+IDTOk/kPu0lNqbprnH2jFYsLQ4EC5M U2XSv8t087I75tzlOkfwctsi3NmUotvna3lIkYSONSLYoWWajX7GNafV4+ij8tpezF Mw21p5uJU43qufboDfyCleg0SIxnndHAaIuEfzG3uxMZ4GngvKLsFr1gqyOoL5mfz/ ZIIlbj//xqDWBmrgy0f0kG3dkuJK60yGyVn/1wLQh0evQ4krDB4UBltD2YKosfW8x2 oIH+nwZG7THKehLdRSGrpseyWT9MvJKabRplQJimonT1jpJvL/nmvPIWAd6V0jI6iT tSRzL8xFaF20Q== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org During SC7 resume, PARKED bit clear from the pinmux registers may cause a glitch on the GPIO lines. So, Tegra GPIOs restore should happen prior to restoring Tegra pinmux to keep the GPIO lines in a known good state prior to clearing PARKED bit. This patch has fix for this by moving Tegra GPIO restore to happen during resume_noirq. Signed-off-by: Sowjanya Komatineni --- drivers/gpio/gpio-tegra.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index f57bfc07ae22..f3c58c597ab9 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c @@ -410,7 +410,7 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc) } #ifdef CONFIG_PM_SLEEP -static int tegra_gpio_resume(struct device *dev) +static int tegra_gpio_resume_noirq(struct device *dev) { struct tegra_gpio_info *tgi = dev_get_drvdata(dev); unsigned long flags; @@ -506,6 +506,15 @@ static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) return irq_set_irq_wake(bank->irq, enable); } + +static const struct dev_pm_ops tegra_gpio_pm_ops = { + .suspend = &tegra_gpio_suspend, + .resume_noirq = &tegra_gpio_resume_noirq +}; + +#define TEGRA_GPIO_PM (&tegra_gpio_pm_ops) +#else +#define TEGRA_GPIO_PM NULL #endif #ifdef CONFIG_DEBUG_FS @@ -553,10 +562,6 @@ static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) #endif -static const struct dev_pm_ops tegra_gpio_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) -}; - static int tegra_gpio_probe(struct platform_device *pdev) { struct tegra_gpio_info *tgi; @@ -706,7 +711,7 @@ static const struct of_device_id tegra_gpio_of_match[] = { static struct platform_driver tegra_gpio_driver = { .driver = { .name = "tegra-gpio", - .pm = &tegra_gpio_pm_ops, + .pm = TEGRA_GPIO_PM, .of_match_table = tegra_gpio_of_match, }, .probe = tegra_gpio_probe, From patchwork Tue Jun 18 07:46:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Xi2xihYA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDT0MT6z9s00 for ; Tue, 18 Jun 2019 17:48:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728867AbfFRHqt (ORCPT ); Tue, 18 Jun 2019 03:46:49 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19649 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728840AbfFRHqq (ORCPT ); Tue, 18 Jun 2019 03:46:46 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:47 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:46 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:46 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:45 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:45 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:45 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 04/17] clk: tegra: save and restore divider rate Date: Tue, 18 Jun 2019 00:46:18 -0700 Message-ID: <1560843991-24123-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844007; bh=MzRi4/U6dTntRT5ieX4O/VlRdfg/Fy9oK6/T3fNDiA8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Xi2xihYAeSEksIwpYYcO1Q1B6z6bQGxuRtbkcYpQYfF57WoLfz9Y8F7lJFF6nwK5n P0J0erhNcnS+FOtR8CI6YjtKoQMfIHg3WXoQoYB+l+o3Vidu3B5j4tdBbJITJYN6qW VBrlH+KQ7RhSQG+AUUPMNpEh+el/mtk0OvPWn4ZCKvrYrRKg1pjAjDgcyrLk8hCoUW TFCUZyKYFRTplnQPY+DPSfbhMrvh2Zvah79ehE4DDkiXI7Lyt3p9DgoEHICA5REl4+ aSkchi6R+EMYOIHWAKinlexq1PVbnu3Fg51c4/8qQS8ak7npd6HRPyQbp58TgVOxvD SUKAqEMwMzLJw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements context save and restore for clock divider. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the context of clock divider is saved and on resume context is restored back for normal operation. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk-divider.c | 23 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..ecb7ff9ce97e 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -109,10 +109,33 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_divider_save_context(struct clk_hw *hw) +{ + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + divider->rate = clk_frac_div_recalc_rate(hw, parent_rate); + + return 0; +} + +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + if (clk_frac_div_set_rate(hw, divider->rate, parent_rate) < 0) + WARN_ON(1); +} + const struct clk_ops tegra_clk_frac_div_ops = { .recalc_rate = clk_frac_div_recalc_rate, .set_rate = clk_frac_div_set_rate, .round_rate = clk_frac_div_round_rate, + .save_context = clk_divider_save_context, + .restore_context = clk_divider_restore_context, }; struct clk *tegra_clk_register_divider(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 905bf1096558..83623f5f55f3 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -42,6 +42,7 @@ struct clk *tegra_clk_register_sync_source(const char *name, * @width: width of the divider bit field * @frac_width: width of the fractional bit field * @lock: register lock + * @rate: rate during suspend and resume * * Flags: * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. @@ -62,6 +63,7 @@ struct tegra_clk_frac_div { u8 width; u8 frac_width; spinlock_t *lock; + unsigned long rate; }; #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) From patchwork Tue Jun 18 07:46:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117700 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="nZEdyTYu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDQ2gFmz9s4V for ; Tue, 18 Jun 2019 17:48:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728930AbfFRHqv (ORCPT ); Tue, 18 Jun 2019 03:46:51 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19658 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728877AbfFRHqu (ORCPT ); Tue, 18 Jun 2019 03:46:50 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:50 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:49 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:49 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:48 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:48 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:48 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 05/17] clk: tegra: pllout: save and restore pllout context Date: Tue, 18 Jun 2019 00:46:19 -0700 Message-ID: <1560843991-24123-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844010; bh=Fzu2bnKTENqIS6KXMYVarTHgv0l912Cey6G3jQKOW8c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=nZEdyTYucXwLVnD5zK4QnqT+ncZAbxqTqF5uPDpP5MfIbvasiNFCBWs3k75E1BVdo +34W/kyhru5QrdgiOIbhbKoivkYSQLp5GrXyi8P9Bx2sCqxZzqOG+fRSwNylgNlatX ZFGjLnEqVdOt8RNUa+FSt/iWnjIVkBA1XXflIGVlEwPFWSmRXfEq4M0vlOh6hPIXcg vaZXvnAq3WrUTeg77NmSsJT/HobtP9KROrHpAv+FcFEIPrJ9RI8GsU/QDcxOBDa0cp FNsIXUGPZkc5WoQ0/dBR72a/Zcdc40SrIGrYYMfUyNdgUPiqYObcLfJ9SCEBKcQ2ko 8SHYbnn4m0F6Q== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements save and restore of pllout context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the state of pllout is saved and on resume it is restored back to have pllout in same state as before suspend. pllout rate is saved and restore in clock divider so it will be at same rate as before suspend when pllout state is restored. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk-pll-out.c | 28 ++++++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 31 insertions(+) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 35f2bf00e1e6..52d140379ce3 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -69,10 +69,38 @@ static void clk_pll_out_disable(struct clk_hw *hw) spin_unlock_irqrestore(pll_out->lock, flags); } +static int tegra_clk_pll_out_save_context(struct clk_hw *hw) +{ + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); + + if (!strcmp(__clk_get_name(hw->clk), "pll_re_out1")) + pll_out->pllout_ctx = readl_relaxed(pll_out->reg); + else + pll_out->pllout_ctx = clk_hw_get_rate(hw); + + return 0; +} + +static void tegra_clk_pll_out_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); + + if (!strcmp(__clk_get_name(hw->clk), "pll_re_out1")) { + writel_relaxed(pll_out->pllout_ctx, pll_out->reg); + } else { + if (!__clk_get_enable_count(hw->clk)) + clk_pll_out_disable(hw); + else + clk_pll_out_enable(hw); + } +} + const struct clk_ops tegra_clk_pll_out_ops = { .is_enabled = clk_pll_out_is_enabled, .enable = clk_pll_out_enable, .disable = clk_pll_out_disable, + .save_context = tegra_clk_pll_out_save_context, + .restore_context = tegra_clk_pll_out_restore_context, }; struct clk *tegra_clk_register_pll_out(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 83623f5f55f3..b47f373c35ad 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -439,6 +439,8 @@ struct clk *tegra_clk_register_pllu_tegra210(const char *name, * @rst_bit_idx: bit to reset PLL divider * @lock: register lock * @flags: hardware-specific flags + * @pllout_ctx: pllout context to save and restore during suspend + * and resume */ struct tegra_clk_pll_out { struct clk_hw hw; @@ -447,6 +449,7 @@ struct tegra_clk_pll_out { u8 rst_bit_idx; spinlock_t *lock; u8 flags; + unsigned int pllout_ctx; }; #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) From patchwork Tue Jun 18 07:46:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117699 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="MItmjHHN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDP2Py1z9s9y for ; Tue, 18 Jun 2019 17:48:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728993AbfFRHqz (ORCPT ); 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Tue, 18 Jun 2019 07:46:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:51 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context Date: Tue, 18 Jun 2019 00:46:20 -0700 Message-ID: <1560843991-24123-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844011; bh=rv36G1StpVw38zPplJcIr82dyfD5o7fnQYcI5YUInQk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=MItmjHHNwWANMr7tsbOe/PKtUMY7Mq3EAtnd7lKg+AgoM3SDmtg8NUU32kfo4UICU XBdJnnQICRAIYqFWu1il2PpBjF3wF1inReHmwIJCudPMuKDUO2c/sy63M1y1W2FnEE /npS+gQ+VqTBu1/ooy5UjFQ12ZacXt8o5Q/LJNfm/ThUAFTpKIseWLwmIPN+zUySNH 6mDK55arv7A0XE8tsQuq2hCVDeGVLyuS+0j0KiapAgXjehn6fUBxiZKpvP99nOtd3K 0JFwwTzyqK2xd9aH4sdi7tUBNEemH0+UBgqGMnDRV8qb8E+fI2MSOxPybBntmQv2e0 eQ1ZW4/RRc0yw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements save and restore of pll context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry pll rate is stored and on resume it is restored back along with its state. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk-pll.c | 115 ++++++++++++++++++++++++++++++++------------ drivers/clk/tegra/clk.h | 6 ++- 2 files changed, 88 insertions(+), 33 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 1583f5fc992f..4b0ed8fc6268 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1008,6 +1008,54 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, return rate; } +void tegra_clk_sync_state_pll(struct clk_hw *hw) +{ + if (!__clk_get_enable_count(hw->clk)) + clk_pll_disable(hw); + else + clk_pll_enable(hw); +} + +static int tegra_clk_pll_save_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + + pll->rate = clk_hw_get_rate(hw); + + if (!strcmp(__clk_get_name(hw->clk), "pll_mb")) + pll->pllbase_ctx = pll_readl_base(pll); + else if (!strcmp(__clk_get_name(hw->clk), "pll_re_vco")) + pll->pllbase_ctx = pll_readl_base(pll) & (0xf << 16); + + return 0; +} + +static void tegra_clk_pll_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + u32 val; + + if (clk_pll_is_enabled(hw)) + return; + + if (!strcmp(__clk_get_name(hw->clk), "pll_mb")) { + pll_writel_base(pll->pllbase_ctx, pll); + } else if (!strcmp(__clk_get_name(hw->clk), "pll_re_vco")) { + val = pll_readl_base(pll); + val &= ~(0xf << 16); + pll_writel_base(pll->pllbase_ctx | val, pll); + } + + if (pll->params->set_defaults) + pll->params->set_defaults(pll); + + clk_set_rate(hw->clk, pll->rate); + + /* do not sync pllx state here. pllx is sync'd after dfll resume */ + if (strcmp(__clk_get_name(hw->clk), "pll_x")) + tegra_clk_sync_state_pll(hw); +} + const struct clk_ops tegra_clk_pll_ops = { .is_enabled = clk_pll_is_enabled, .enable = clk_pll_enable, @@ -1015,6 +1063,8 @@ const struct clk_ops tegra_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_round_rate, .set_rate = clk_pll_set_rate, + .save_context = tegra_clk_pll_save_context, + .restore_context = tegra_clk_pll_restore_context, }; const struct clk_ops tegra_clk_plle_ops = { @@ -1802,6 +1852,27 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) return ret; } + +static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll) +{ + u32 val, val_aux; + + /* ensure parent is set to pll_ref */ + val = pll_readl_base(pll); + val_aux = pll_readl(pll->params->aux_reg, pll); + + if (val & PLL_BASE_ENABLE) { + if ((val_aux & PLLE_AUX_PLLRE_SEL) || + (val_aux & PLLE_AUX_PLLP_SEL)) + WARN(1, "pll_e enabled with unsupported parent %s\n", + (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : + "pll_re_vco"); + } else { + val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); + pll_writel(val_aux, pll->params->aux_reg, pll); + fence_udelay(1, pll->clk_base); + } +} #endif static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, @@ -2214,27 +2285,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, { struct tegra_clk_pll *pll; struct clk *clk; - u32 val, val_aux; pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); - /* ensure parent is set to pll_re_vco */ - - val = pll_readl_base(pll); - val_aux = pll_readl(pll_params->aux_reg, pll); - - if (val & PLL_BASE_ENABLE) { - if ((val_aux & PLLE_AUX_PLLRE_SEL) || - (val_aux & PLLE_AUX_PLLP_SEL)) - WARN(1, "pll_e enabled with unsupported parent %s\n", - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : - "pll_re_vco"); - } else { - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); - pll_writel(val_aux, pll_params->aux_reg, pll); - } + _clk_plle_tegra_init_parent(pll); clk = _tegra_clk_register_pll(pll, name, parent_name, flags, &tegra_clk_plle_tegra114_ops); @@ -2276,6 +2332,8 @@ static const struct clk_ops tegra_clk_pllss_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllxc_set_rate, + .save_context = tegra_clk_pll_save_context, + .restore_context = tegra_clk_pll_restore_context, }; struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, @@ -2520,11 +2578,19 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw) spin_unlock_irqrestore(pll->lock, flags); } +static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + + _clk_plle_tegra_init_parent(pll); +} + static const struct clk_ops tegra_clk_plle_tegra210_ops = { .is_enabled = clk_plle_tegra210_is_enabled, .enable = clk_plle_tegra210_enable, .disable = clk_plle_tegra210_disable, .recalc_rate = clk_pll_recalc_rate, + .restore_context = tegra_clk_plle_t210_restore_context, }; struct clk *tegra_clk_register_plle_tegra210(const char *name, @@ -2535,27 +2601,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name, { struct tegra_clk_pll *pll; struct clk *clk; - u32 val, val_aux; pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); - /* ensure parent is set to pll_re_vco */ - - val = pll_readl_base(pll); - val_aux = pll_readl(pll_params->aux_reg, pll); - - if (val & PLLE_BASE_ENABLE) { - if ((val_aux & PLLE_AUX_PLLRE_SEL) || - (val_aux & PLLE_AUX_PLLP_SEL)) - WARN(1, "pll_e enabled with unsupported parent %s\n", - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : - "pll_re_vco"); - } else { - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); - pll_writel(val_aux, pll_params->aux_reg, pll); - } + _clk_plle_tegra_init_parent(pll); clk = _tegra_clk_register_pll(pll, name, parent_name, flags, &tegra_clk_plle_tegra210_ops); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index b47f373c35ad..581deb4f3ac0 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -310,6 +310,8 @@ struct tegra_clk_pll_params { * @pmc: address of PMC, required to read override bits * @lock: register lock * @params: PLL parameters + * @rate: rate during system suspend and resume + * @pllbase_ctx: pll base register value during suspend and resume */ struct tegra_clk_pll { struct clk_hw hw; @@ -317,6 +319,8 @@ struct tegra_clk_pll { void __iomem *pmc; spinlock_t *lock; struct tegra_clk_pll_params *params; + unsigned long rate; + unsigned int pllbase_ctx; }; #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) @@ -834,7 +838,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); - +void tegra_clk_sync_state_pll(struct clk_hw *hw); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Tue Jun 18 07:46:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="hmtsUmsB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDL6qgLz9s4V for ; Tue, 18 Jun 2019 17:48:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729050AbfFRHrA (ORCPT ); Tue, 18 Jun 2019 03:47:00 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9715 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726047AbfFRHq4 (ORCPT ); Tue, 18 Jun 2019 03:46:56 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:54 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:54 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:54 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:53 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:53 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:53 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 07/17] clk: tegra: save and restore CPU and System clocks context Date: Tue, 18 Jun 2019 00:46:21 -0700 Message-ID: <1560843991-24123-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844014; bh=rX5C6TLRq6S7JDWcvC7pebJyWsbcNEJPnKOIpc/oRDQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=hmtsUmsBcnfkalFaVr5lFf0cnBssKBVcJ8SMd+T64qsDe+rXwauY26LHtvRXFYBU1 ID5Y1Acjw8v2KEdAk31OzrvHcOpymFQVGcTyj7nOJZLvko4BTh7f+KYioyCQndZLRt /+iKvcSGCnYl93hv2IX3v0Q2pj9XRpsgwlkKzx862Bxih2h3+CHvzmvUaqmAoQLD3r aUMPAPB8WI7qQOTl2WXSDY+0wWDnI1itTuSD650GQJ32Ms0gr/ESgVhEuLd+cwZNyq TjACd0JGQ9iaSIZg2CZhMjuH/Q2/KCXDEmZ3kkVKKjJp4MK5y5f0f9hRIosuQSlXCO +DuFqEMaPI+7Q== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org During system suspend state, core power goes off and looses all the CAR controller register settings. This patch creates APIs for saving and restoring the context of Tegra CPUG, CPULP and SCLK. CPU and System clock context includes - CPUG, CPULP, and SCLK burst policy settings for clock sourcea of all their normal states. - SCLK divisor and System clock rate for restoring SCLK, AHB and APB rates on resume. - OSC_DIV settings which are used as reference clock input to some PLLs. - SPARE_REG and CLK_MASK settings. These APIs are used in Tegra210 clock driver during suspend and resume operation. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk-tegra-super-gen4.c | 4 -- drivers/clk/tegra/clk.c | 80 ++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 14 ++++++ 3 files changed, 94 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index cdfe7c9697e1..ed69ec4d883e 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -19,10 +19,6 @@ #define PLLX_MISC2 0x514 #define PLLX_MISC3 0x518 -#define CCLKG_BURST_POLICY 0x368 -#define CCLKLP_BURST_POLICY 0x370 -#define SCLK_BURST_POLICY 0x028 -#define SYSTEM_CLK_RATE 0x030 #define SCLK_DIVIDER 0x2c static DEFINE_SPINLOCK(sysrate_lock); diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 573e3c967ae1..26690663157a 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -70,6 +70,12 @@ static struct clk **clks; static int clk_num; static struct clk_onecell_data clk_data; +static u32 cclkg_burst_policy_ctx[2]; +static u32 cclklp_burst_policy_ctx[2]; +static u32 sclk_burst_policy_ctx[2]; +static u32 sys_clk_divisor_ctx, system_rate_ctx; +static u32 spare_ctx, misc_clk_enb_ctx, clk_arm_ctx; + /* Handlers for SoC-specific reset lines */ static int (*special_reset_assert)(unsigned long); static int (*special_reset_deassert)(unsigned long); @@ -199,6 +205,80 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } +void tegra_cclkg_burst_policy_save_context(void) +{ + int i; + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) + cclkg_burst_policy_ctx[i] = readl_relaxed(clk_base + + CCLKG_BURST_POLICY + + (i * 4)); +} + +void tegra_cclkg_burst_policy_restore_context(void) +{ + int i; + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) + writel_relaxed(cclkg_burst_policy_ctx[i], + clk_base + CCLKG_BURST_POLICY + (i * 4)); + + fence_udelay(2, clk_base); +} + +void tegra_sclk_cclklp_burst_policy_save_context(void) +{ + int i; + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) { + cclklp_burst_policy_ctx[i] = readl_relaxed(clk_base + + CCLKLP_BURST_POLICY + + (i * 4)); + + sclk_burst_policy_ctx[i] = readl_relaxed(clk_base + + SCLK_BURST_POLICY + + (i * 4)); + } + + sys_clk_divisor_ctx = readl_relaxed(clk_base + SYS_CLK_DIV); + system_rate_ctx = readl_relaxed(clk_base + SYSTEM_CLK_RATE); + spare_ctx = readl_relaxed(clk_base + SPARE_REG0); + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB); + clk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM); +} + +void tegra_sclk_cpulp_burst_policy_restore_context(void) +{ + int i; + u32 val; + + /* + * resume SCLK and CPULP clocks + * for SCLk, set safe dividers values first and then restore source + * and dividers + */ + + writel_relaxed(0x1, clk_base + SYSTEM_CLK_RATE); + val = readl_relaxed(clk_base + SYS_CLK_DIV); + if (val < sys_clk_divisor_ctx) + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV); + + fence_udelay(2, clk_base); + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) { + writel_relaxed(cclklp_burst_policy_ctx[i], + clk_base + CCLKLP_BURST_POLICY + (i * 4)); + writel_relaxed(sclk_burst_policy_ctx[i], + clk_base + SCLK_BURST_POLICY + (i * 4)); + } + + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV); + writel_relaxed(system_rate_ctx, clk_base + SYSTEM_CLK_RATE); + writel_relaxed(spare_ctx, clk_base + SPARE_REG0); + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB); + writel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM); +} + struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 581deb4f3ac0..c8f8a23096e2 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -10,6 +10,16 @@ #include #include +#define SCLK_BURST_POLICY 0x28 +#define SYSTEM_CLK_RATE 0x30 +#define CLK_MASK_ARM 0x44 +#define MISC_CLK_ENB 0x48 +#define CCLKG_BURST_POLICY 0x368 +#define CCLKLP_BURST_POLICY 0x370 +#define SYS_CLK_DIV 0x400 +#define SPARE_REG0 0x55c +#define BURST_POLICY_REG_SIZE 2 + /** * struct tegra_clk_sync_source - external clock source from codec * @@ -839,6 +849,10 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); void tegra_clk_sync_state_pll(struct clk_hw *hw); +void tegra_cclkg_burst_policy_save_context(void); +void tegra_cclkg_burst_policy_restore_context(void); +void tegra_sclk_cclklp_burst_policy_save_context(void); +void tegra_sclk_cpulp_burst_policy_restore_context(void); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Tue Jun 18 07:46:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117676 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="G/Ns6yra"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgC86xYhz9s5c for ; Tue, 18 Jun 2019 17:47:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729037AbfFRHq7 (ORCPT ); Tue, 18 Jun 2019 03:46:59 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19673 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728840AbfFRHq6 (ORCPT ); Tue, 18 Jun 2019 03:46:58 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:56 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:56 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:56 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:56 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 08/17] clk: tegra: add support for peripheral clock suspend and resume Date: Tue, 18 Jun 2019 00:46:22 -0700 Message-ID: <1560843991-24123-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844017; bh=XxXnlq+TujPWngS562UXjtW8HdavZKOUpZld3hJwekQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=G/Ns6yraA5bwBGu3XnArGzWXpybmCZGgv068rhuLenhsEg1bjiqV65EtkBqA2W3qq axgjbAM7GxSzFulkX++U9u5Q7O3l25GRvuvYwnZ/J2sjndSDogh88w/twGTjUgt8aU T7H+HI0yyD1hiQVGh17DM7QXcEuWGgFUr9MoAwtO3cj7vYvFfeqNnqT/47+9CaxnAm OCKxoWlhpQ0XnSSMDZSIzLNz9NYP2Ol+YZSeEsc6XbPXGJLhc1NZywH/TqysO1h8D6 xuNY9mHttpr31Y+EDONXyVMflVThS8/Ugw737KqXfnICHrfg++/EVE4SJx4u8BmAo8 j5ci3QiqVVkTg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch creates APIs to save and restore the state of all peripheral clocks reset and enables. These APIs are invoked by Tegra210 clock driver during suspend and resume to save the peripheral clocks state before suspend and to restore them on resume. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++- drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 26690663157a..bd3b46c5f941 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -70,6 +70,7 @@ static struct clk **clks; static int clk_num; static struct clk_onecell_data clk_data; +static u32 *periph_ctx; static u32 cclkg_burst_policy_ctx[2]; static u32 cclklp_burst_policy_ctx[2]; static u32 sclk_burst_policy_ctx[2]; @@ -279,6 +280,63 @@ void tegra_sclk_cpulp_burst_policy_restore_context(void) writel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM); } +void tegra_clk_periph_suspend(void __iomem *clk_base) +{ + int i, idx; + + idx = 0; + for (i = 0; i < periph_banks; i++, idx++) + periph_ctx[idx] = + readl_relaxed(clk_base + periph_regs[i].rst_reg); + + for (i = 0; i < periph_banks; i++, idx++) + periph_ctx[idx] = + readl_relaxed(clk_base + periph_regs[i].enb_reg); +} + +void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base) +{ + int i; + + WARN_ON(count != periph_banks); + + for (i = 0; i < count; i++) + writel_relaxed(clks_on[i], clk_base + periph_regs[i].enb_reg); +} + +void tegra_clk_periph_resume(void __iomem *clk_base) +{ + int i, idx; + + idx = 0; + for (i = 0; i < periph_banks; i++, idx++) + writel_relaxed(periph_ctx[idx], + clk_base + periph_regs[i].rst_reg); + + /* ensure all resets have propagated */ + fence_udelay(2, clk_base); + tegra_read_chipid(); + + for (i = 0; i < periph_banks; i++, idx++) + writel_relaxed(periph_ctx[idx], + clk_base + periph_regs[i].enb_reg); + + /* ensure all enables have propagated */ + fence_udelay(2, clk_base); + tegra_read_chipid(); +} + +static int tegra_clk_suspend_ctx_init(int banks) +{ + int err = 0; + + periph_ctx = kcalloc(2 * banks, sizeof(*periph_ctx), GFP_KERNEL); + if (!periph_ctx) + err = -ENOMEM; + + return err; +} + struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; @@ -295,11 +353,21 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) periph_banks = banks; clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL); - if (!clks) + if (!clks) { kfree(periph_clk_enb_refcnt); + return NULL; + } clk_num = num; + if (IS_ENABLED(CONFIG_PM_SLEEP)) { + if (tegra_clk_suspend_ctx_init(banks)) { + kfree(periph_clk_enb_refcnt); + kfree(clks); + return NULL; + } + } + return clks; } diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c8f8a23096e2..a354cacae5a6 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -853,6 +853,9 @@ void tegra_cclkg_burst_policy_save_context(void); void tegra_cclkg_burst_policy_restore_context(void); void tegra_sclk_cclklp_burst_policy_save_context(void); void tegra_sclk_cpulp_burst_policy_restore_context(void); +void tegra_clk_periph_suspend(void __iomem *clk_base); +void tegra_clk_periph_resume(void __iomem *clk_base); +void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Tue Jun 18 07:46:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="bbiwUL/p"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgDH40PNz9s4V for ; Tue, 18 Jun 2019 17:47:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729319AbfFRHry (ORCPT ); Tue, 18 Jun 2019 03:47:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14127 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729042AbfFRHrA (ORCPT ); Tue, 18 Jun 2019 03:47:00 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:46:59 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:46:59 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:59 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:59 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:46:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:46:59 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:46:58 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 09/17] clk: tegra: support for saving and restoring OSC clock context Date: Tue, 18 Jun 2019 00:46:23 -0700 Message-ID: <1560843991-24123-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844019; bh=LIyfL7frpgJGlYXzyqay8F1a5dljw6dG3mcUcqh5Ovo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=bbiwUL/pLBrXnaYtjuKw11ptbgg6r6S8BMjNb5ojl5E4hLJA7zy95NqQ1N9xYhsTZ v07nxMPAUHiCBf9lZgNWiP3i08+w1Teh97MN70tEmmsfdpJ1S37ZD3JBzXM0vx/uHD YvsjgVNWls2igACcipyiPRIxMqUcw014rcwLQ8MOvpiyRAaxwhuULHrApSndPEFXIa SxmHlpwTnLy+B/Lqwar1arYm5iGZDuS+YtqX6IZYs906m0f26kDZT2WOYYxHF8Apq5 1x1R4irTJ54KjCmea1CkRR9xnrxKxz22e578wk7f8kGcwH3b/2vjFz3BYtN5b2/KHR QG7pQ5QXa46Yg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds support for storing OSC clock frequency and the drive-strength during OSC clock init and creates an API to restore OSC control register value from the saved context. This API is invoked by Tegra210 clock driver during system resume to restore the OSC clock settings. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk-tegra-fixed.c | 14 ++++++++++++++ drivers/clk/tegra/clk.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index 8d91b2b191cf..e8df0ccbffd0 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -17,7 +17,10 @@ #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_SHIFT 28 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 +#define OSC_CTRL_MASK (0x3f2 | \ + (0xf << OSC_CTRL_OSC_FREQ_SHIFT)) +static u32 osc_ctrl_ctx; int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned long *input_freqs, unsigned int num, unsigned int clk_m_div, unsigned long *osc_freq, @@ -29,6 +32,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned osc_idx; val = readl_relaxed(clk_base + OSC_CTRL); + osc_ctrl_ctx = val & OSC_CTRL_MASK; osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; if (osc_idx < num) @@ -96,3 +100,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) *dt_clk = clk; } } + +void tegra_clk_osc_resume(void __iomem *clk_base) +{ + u32 val; + + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK; + val |= osc_ctrl_ctx; + writel_relaxed(val, clk_base + OSC_CTRL); + fence_udelay(2, clk_base); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index a354cacae5a6..bb34a19aaf26 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -856,6 +856,7 @@ void tegra_sclk_cpulp_burst_policy_restore_context(void); void tegra_clk_periph_suspend(void __iomem *clk_base); void tegra_clk_periph_resume(void __iomem *clk_base); void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base); +void tegra_clk_osc_resume(void __iomem *clk_base); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Tue Jun 18 07:46:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="IR6FHF69"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgD93Vchz9s4V for ; Tue, 18 Jun 2019 17:47:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729124AbfFRHrE (ORCPT ); Tue, 18 Jun 2019 03:47:04 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14145 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729110AbfFRHrD (ORCPT ); Tue, 18 Jun 2019 03:47:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:02 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:02 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:02 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:01 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 10/17] clk: tegra: add suspend resume support for DFLL Date: Tue, 18 Jun 2019 00:46:24 -0700 Message-ID: <1560843991-24123-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844022; bh=qGPf8GeJzYp5l1LLIt//TFC/PvM/mcxGGf78pbIwi5s=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=IR6FHF692X/4x2AJEoqn/f6pleTP9fwnEp5824cbV7rxFrPGCg6y0CyMKp+MmV8Fr WVp5wM99/LvkHNw6cdo1+DpGiTR2lLhTBzMZ5+BF6DCToXAz1ot4cIUSW8mKTqZSCv Q8pR4oZHDaD1sKN9X9DG7aT+IRZJQ8RMR0+4o6PDSgCwnH9m2a3Wgn6Tyr9V4nojdm GzsZQGW62CxGYzAIz0FJVTwl01DgHpfpydPtkdVbimcbVdcZBcQQikKVtDetx1Ffl6 MZ30jgx67vqwxZYPlVAD/7lCGpYb2H4EBsdMpB8XDjprBHFMjRfJ0Prca9kSjcD/Gl Usj0xr0jKTNSQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch creates APIs for supporting Tegra210 clock driver to perform DFLL suspend and resume operation. During suspend, DFLL mode is saved and on resume Tegra210 clock driver invokes DFLL resume API to re-initialize DFLL to enable target device clock in open loop mode or closed loop mode. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- drivers/clk/tegra/clk-dfll.c | 78 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-dfll.h | 2 ++ 2 files changed, 80 insertions(+) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index f8688c2ddf1a..a1f37cf99b00 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -277,6 +277,7 @@ struct tegra_dfll { unsigned long dvco_rate_min; enum dfll_ctrl_mode mode; + enum dfll_ctrl_mode resume_mode; enum dfll_tune_range tune_range; struct dentry *debugfs_dir; struct clk_hw dfll_clk_hw; @@ -1864,6 +1865,83 @@ static int dfll_fetch_common_params(struct tegra_dfll *td) } /* + * tegra_dfll_suspend + * @pdev: DFLL instance + * + * dfll controls clock/voltage to other devices, including CPU. Therefore, + * dfll driver pm suspend callback does not stop cl-dvfs operations. + */ +void tegra_dfll_suspend(struct platform_device *pdev) +{ + struct tegra_dfll *td = dev_get_drvdata(&pdev->dev); + + if (!td) + return; + + if (td->mode <= DFLL_DISABLED) + return; + + td->resume_mode = td->mode; + switch (td->mode) { + case DFLL_CLOSED_LOOP: + dfll_set_mode(td, DFLL_CLOSED_LOOP); + dfll_set_frequency_request(td, &td->last_req); + + dfll_unlock(td); + break; + default: + break; + } +} + +/** + * tegra_dfll_resume - reprogram the DFLL after context-loss + * @pdev: DFLL instance + * + * Re-initialize and enable target device clock in open loop mode. Called + * directly from SoC clock resume syscore operation. Closed loop will be + * re-entered in platform syscore ops as well after CPU clock source is + * switched to DFLL in open loop. + */ +void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll) +{ + struct tegra_dfll *td = dev_get_drvdata(&pdev->dev); + + if (!td) + return; + + if (on_dfll) { + if (td->resume_mode == DFLL_CLOSED_LOOP) + dfll_lock(td); + td->resume_mode = DFLL_DISABLED; + return; + } + + reset_control_deassert(td->dvco_rst); + + pm_runtime_get(td->dev); + + /* Re-init DFLL */ + dfll_init_out_if(td); + dfll_set_default_params(td); + dfll_set_open_loop_config(td); + + pm_runtime_put(td->dev); + + /* Restore last request and mode up to open loop */ + switch (td->resume_mode) { + case DFLL_CLOSED_LOOP: + case DFLL_OPEN_LOOP: + dfll_set_mode(td, DFLL_OPEN_LOOP); + if (td->pmu_if == TEGRA_DFLL_PMU_I2C) + dfll_i2c_set_output_enabled(td, false); + break; + default: + break; + } +} + +/* * API exported to per-SoC platform drivers */ diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 1b14ebe7268b..c21fc2061a20 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -40,6 +40,8 @@ struct tegra_dfll_soc_data { int tegra_dfll_register(struct platform_device *pdev, struct tegra_dfll_soc_data *soc); struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev); +void tegra_dfll_suspend(struct platform_device *pdev); +void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll); int tegra_dfll_runtime_suspend(struct device *dev); int tegra_dfll_runtime_resume(struct device *dev); From patchwork Tue Jun 18 07:46:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117688 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="DWI6L8Ui"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgCy3Dylz9s00 for ; Tue, 18 Jun 2019 17:47:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729159AbfFRHrI (ORCPT ); Tue, 18 Jun 2019 03:47:08 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14155 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729140AbfFRHrH (ORCPT ); Tue, 18 Jun 2019 03:47:07 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:04 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:47:05 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:04 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:04 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:03 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:04 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 11/17] clk: tegra210: support for Tegra210 clocks suspend and resume Date: Tue, 18 Jun 2019 00:46:25 -0700 Message-ID: <1560843991-24123-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844024; bh=SGcqTwvLQqwf1tE0nNYcxmB0duJ1Yuf1/djbG6n28AE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DWI6L8UiRvOIoa3VkwUYVGNn1EyJJhVBini8WE2AIFGM9hdSlJHvD9XLa/nVnTwAK 4p4jmrN/fnoM1exu97UXMoYrmsazlXEod4ifZOs/LAywWxqX+TSt4+k5+o/+mTsu8r MsI8C1Jhips8SFjJAzWS5Kw1RbGqHxr6ffCS3TS9gm9tYDnLu/XmtYzYhwZtK4mdzR O20G6sKIpoAmkmlfOKnfee+EtP++tJ95GJ51TizktV0qlQFlhBoyAbr/jtUyfsgA4U iVzMx4AtnsdFgR3Nct8rVxDvq+v/L89spqvxEPyFtvDq829dggwWtESUJLKdF4WHEN uxvf6PbgOedhw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds system suspend and resume support for Tegra210 clocks. All the CAR controller settings are lost on suspend when core power goes off. This patch has implementation for saving and restoring all the PLLs and clocks context during system suspend and resume to have the system back to operating state. Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 218 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 211 insertions(+), 7 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index e1ba62d2b1a0..c34d92e871f4 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -9,10 +9,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -20,6 +22,7 @@ #include #include "clk.h" +#include "clk-dfll.h" #include "clk-id.h" /* @@ -36,6 +39,8 @@ #define CLK_SOURCE_LA 0x1f8 #define CLK_SOURCE_SDMMC2 0x154 #define CLK_SOURCE_SDMMC4 0x164 +#define CLK_OUT_ENB_Y 0x298 +#define CLK_ENB_PLLP_OUT_CPU BIT(31) #define PLLC_BASE 0x80 #define PLLC_OUT 0x84 @@ -225,6 +230,7 @@ #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac +#define CPU_SOFTRST_CTRL 0x380 #define LVL2_CLK_GATE_OVRA 0xf8 #define LVL2_CLK_GATE_OVRC 0x3a0 @@ -2820,6 +2826,7 @@ static int tegra210_enable_pllu(void) struct tegra_clk_pll_freq_table *fentry; struct tegra_clk_pll pllu; u32 reg; + int ret; for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { if (fentry->input_rate == pll_ref_freq) @@ -2836,7 +2843,7 @@ static int tegra210_enable_pllu(void) reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); reg &= ~BIT(pllu.params->iddq_bit_idx); writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); - udelay(5); + fence_udelay(5, clk_base); reg = readl_relaxed(clk_base + PLLU_BASE); reg &= ~GENMASK(20, 0); @@ -2844,13 +2851,13 @@ static int tegra210_enable_pllu(void) reg |= fentry->n << 8; reg |= fentry->p << 16; writel(reg, clk_base + PLLU_BASE); - udelay(1); + fence_udelay(1, clk_base); reg |= PLL_ENABLE; writel(reg, clk_base + PLLU_BASE); + fence_udelay(1, clk_base); - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, - reg & PLL_BASE_LOCK, 2, 1000); - if (!(reg & PLL_BASE_LOCK)) { + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); + if (ret) { pr_err("Timed out waiting for PLL_U to lock\n"); return -ETIMEDOUT; } @@ -2890,12 +2897,12 @@ static int tegra210_init_pllu(void) reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); - udelay(1); + fence_udelay(1, clk_base); reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); - udelay(1); + fence_udelay(1, clk_base); reg = readl_relaxed(clk_base + PLLU_BASE); reg &= ~PLLU_BASE_CLKENABLE_USB; @@ -3282,6 +3289,188 @@ static void tegra210_disable_cpu_clock(u32 cpu) } #ifdef CONFIG_PM_SLEEP +static u32 cpu_softrst_ctx[3]; +static struct platform_device *dfll_pdev; +static u32 *periph_clk_src_ctx; +struct periph_source_bank { + u32 start; + u32 end; +}; + +static struct periph_source_bank periph_srcs[] = { + [0] = { + .start = 0x100, + .end = 0x198, + }, + [1] = { + .start = 0x1a0, + .end = 0x1f8, + }, + [2] = { + .start = 0x3b4, + .end = 0x42c, + }, + [3] = { + .start = 0x49c, + .end = 0x4b4, + }, + [4] = { + .start = 0x560, + .end = 0x564, + }, + [5] = { + .start = 0x600, + .end = 0x678, + }, + [6] = { + .start = 0x694, + .end = 0x6a0, + }, + [7] = { + .start = 0x6b8, + .end = 0x718, + }, +}; + +/* This array lists the valid clocks for each periph clk bank */ +static u32 periph_clks_on[] = { + 0xdcd7dff9, + 0x87d1f3e7, + 0xf3fed3fa, + 0xffc18cfb, + 0x793fb7ff, + 0x3fe66fff, + 0xfc1fc7ff, +}; + +static struct platform_device *dfll_pdev; +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4)) +#define car_writel(_val, _base, _off) \ + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4)) + +static u32 * __init tegra210_init_suspend_ctx(void) +{ + int i, size = 0; + + for (i = 0; i < ARRAY_SIZE(periph_srcs); i++) + size += periph_srcs[i].end - periph_srcs[i].start + 4; + + periph_clk_src_ctx = kmalloc(size, GFP_KERNEL); + + return periph_clk_src_ctx; +} + +static int tegra210_clk_suspend(void) +{ + int i; + unsigned long off; + struct device_node *node; + u32 *clk_rst_ctx = periph_clk_src_ctx; + u32 val; + + tegra_cclkg_burst_policy_save_context(); + + if (!dfll_pdev) { + node = of_find_compatible_node(NULL, NULL, + "nvidia,tegra210-dfll"); + if (node) + dfll_pdev = of_find_device_by_node(node); + of_node_put(node); + if (!dfll_pdev) + pr_err("dfll node not found. no suspend for dfll\n"); + } + + if (dfll_pdev) + tegra_dfll_suspend(dfll_pdev); + + /* Enable PLLP_OUT_CPU after dfll suspend */ + val = car_readl(CLK_OUT_ENB_Y, 0); + val |= CLK_ENB_PLLP_OUT_CPU; + car_writel(val, CLK_OUT_ENB_Y, 0); + + tegra_clk_periph_suspend(clk_base); + + for (i = 0; i < ARRAY_SIZE(periph_srcs); i++) + for (off = periph_srcs[i].start; off <= periph_srcs[i].end; + off += 4) + *clk_rst_ctx++ = car_readl(off, 0); + + tegra_sclk_cclklp_burst_policy_save_context(); + + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i); + + clk_save_context(); + + return 0; +} + +static void tegra210_clk_resume(void) +{ + int i; + unsigned long off; + u32 val; + u32 *clk_rst_ctx = periph_clk_src_ctx; + struct clk_hw *parent; + struct clk *clk; + + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i); + + tegra_clk_osc_resume(clk_base); + + /* + * restore all the plls before configuring clocks and resetting + * the devices. + */ + tegra210_init_pllu(); + tegra_sclk_cpulp_burst_policy_restore_context(); + clk_restore_context(); + + /* enable all clocks before configuring clock sources */ + tegra_clk_periph_force_on(periph_clks_on, ARRAY_SIZE(periph_clks_on), + clk_base); + /* wait for all writes to happen to have all the clocks enabled */ + wmb(); + fence_udelay(2, clk_base); + + /* restore all the devices clock sources */ + for (i = 0; i < ARRAY_SIZE(periph_srcs); i++) + for (off = periph_srcs[i].start; off <= periph_srcs[i].end; + off += 4) + car_writel(*clk_rst_ctx++, off, 0); + + /* propagate and restore resets, restore clock state */ + fence_udelay(5, clk_base); + tegra_clk_periph_resume(clk_base); + + /* + * restore CPUG clocks: + * - enable DFLL in open loop mode + * - switch CPUG to DFLL clock source + * - close DFLL loop + * - sync PLLX state + */ + if (dfll_pdev) + tegra_dfll_resume(dfll_pdev, false); + + tegra_cclkg_burst_policy_restore_context(); + fence_udelay(2, clk_base); + + if (dfll_pdev) + tegra_dfll_resume(dfll_pdev, true); + + parent = clk_hw_get_parent(__clk_get_hw(clks[TEGRA210_CLK_CCLK_G])); + clk = clks[TEGRA210_CLK_PLL_X]; + if (parent != __clk_get_hw(clk)) + tegra_clk_sync_state_pll(__clk_get_hw(clk)); + + /* Disable PLL_OUT_CPU after DFLL resume */ + val = car_readl(CLK_OUT_ENB_Y, 0); + val &= ~CLK_ENB_PLLP_OUT_CPU; + car_writel(val, CLK_OUT_ENB_Y, 0); +} + static void tegra210_cpu_clock_suspend(void) { /* switch coresite to clk_m, save off original source */ @@ -3295,8 +3484,20 @@ static void tegra210_cpu_clock_resume(void) writel(tegra210_cpu_clk_sctx.clk_csite_src, clk_base + CLK_SOURCE_CSITE); } +#else +#define tegra210_clk_suspend NULL +#define tegra210_clk_resume NULL +static inline u32 *tegra210_init_suspend_ctx(void) +{ + return NULL; +} #endif +static struct syscore_ops tegra_clk_syscore_ops = { + .suspend = tegra210_clk_suspend, + .resume = tegra210_clk_resume, +}; + static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { .wait_for_reset = tegra210_wait_cpu_in_reset, .disable_clock = tegra210_disable_cpu_clock, @@ -3580,5 +3781,8 @@ static void __init tegra210_clock_init(struct device_node *np) tegra210_mbist_clk_init(); tegra_cpu_car_ops = &tegra210_cpu_car_ops; + + if (tegra210_init_suspend_ctx()) + register_syscore_ops(&tegra_clk_syscore_ops); } CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); From patchwork Tue Jun 18 07:46:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ZgEA02B3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgD43rf2z9s4V for ; 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Tue, 18 Jun 2019 07:47:06 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:06 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 12/17] soc/tegra: pmc: allow support for more tegra wake Date: Tue, 18 Jun 2019 00:46:26 -0700 Message-ID: <1560843991-24123-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844027; bh=4EGQI++zj4lUDjQs0M1vegh7zzNvu5bAdmZ5kricB/0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZgEA02B306QGuVA6EM5wD1pKUQMNg5hcs5pnmYOGM8L2pnTzCaunYb15iOriCsRuo 28sxZirK2rUfhr9AWRyttvVKg0k6/rhl5wtR/WonT80yHeYDikeIx4PeemZEfrUT4M GjiwJHkLJ5PBnzn4zOcDmNFi1iRpLKfClU68SedyH7d3OTiQuKjqZ9uByQYhlJ1SqZ +neCV99leG2sHOSQkzNkdk2CRUYJrn+uMQ6+7K9UjBxyZ7cpuW1z7bOPzCo8rZG9sk 010Hj3R3r6h8sRYyNHeiX5xamg037SKpEg6O28zJ0e3LmNY9RV9MLoiLODug7jzLm7 QDwR/CeQicFjw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch allows to create separate irq_set_wake and irq_set_type implementations for different tegra designs PMC that has different wake models which require difference wake registers and different programming sequence. AOWAKE model support is available for Tegra186 and Tegra194 only and it resides within PMC and supports tiered wake architecture. Tegra210 and prior tegra designs uses PMC directly to receive wake events and coordinate the wake sequence. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index edd4fe06810f..e87f29a35fcf 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -226,6 +226,8 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + int (*irq_set_wake)(struct irq_data *data, unsigned int on); + int (*irq_set_type)(struct irq_data *data, unsigned int type); const char * const *reset_sources; unsigned int num_reset_sources; @@ -1919,7 +1921,7 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; -static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); unsigned int offset, bit; @@ -1951,7 +1953,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } -static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) +static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); u32 value; @@ -2005,8 +2007,10 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) pmc->irq.irq_unmask = irq_chip_unmask_parent; pmc->irq.irq_eoi = irq_chip_eoi_parent; pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; - pmc->irq.irq_set_type = tegra_pmc_irq_set_type; - pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; + if (pmc->soc->irq_set_type) + pmc->irq.irq_set_type = pmc->soc->irq_set_type; + if (pmc->soc->irq_set_wake) + pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, &tegra_pmc_irq_domain_ops, pmc); @@ -2679,6 +2683,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .regs = &tegra186_pmc_regs, .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .irq_set_wake = tegra186_pmc_irq_set_wake, + .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra186_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), .reset_levels = tegra186_reset_levels, From patchwork Tue Jun 18 07:46:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="mr95d6Nt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgCv59Gqz9s9y for ; Tue, 18 Jun 2019 17:47:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729177AbfFRHrL (ORCPT ); Tue, 18 Jun 2019 03:47:11 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14174 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726238AbfFRHrL (ORCPT ); Tue, 18 Jun 2019 03:47:11 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:09 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:09 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:09 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:09 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210 Date: Tue, 18 Jun 2019 00:46:27 -0700 Message-ID: <1560843991-24123-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844029; bh=Eft9jVTETH16qx1GufxFmbqLBke4vXfKbSmLNuCeeYA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=mr95d6NtTmSciq2E3sFgyuSs+AhtQluFR6xuZePLQKADK7dnFg7ubCDF+Z2ECmrDj tiqISvbLEDLwsENrnRN6bHwv6R0mmB+5gkrDEKGfBjxrVA5xlvb2VvluZF4oZbFme6 u8Mhyqfi9WkwGim+JaMdUHoualURPduJdvpevE4GdDUlj8V74Aa9M16tLg1q2+Vo4r C88q5Rrv6HvtnYRbS/w9nJY76eKcH/Uk8NN1bVnRezarg45uLwSoG4PJ4k9HyEKO6m zLb362kFexWJ270V/DFFj5YuFRA1qU8GUKDFHS/mNeqx0ZVnwet54Q0OVO1djAT2M3 wwJcPfytCj46A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index e87f29a35fcf..603fc3bd73f5 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -57,6 +57,12 @@ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5) + +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) @@ -87,6 +93,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1921,6 +1932,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* + * latch wakeups to SW_WAKE_STATUS register to capture events + * that would not make it into wakeup event register during LP0 exit. + */ + value = tegra_pmc_readl(pmc, PMC_CNTRL); + value |= PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + value &= ~PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= 1 << bit; + else + value &= ~(1 << bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1953,6 +2013,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= 1 << bit; + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~(1 << bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= 1 << bit; + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2541,6 +2644,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2558,10 +2665,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ From patchwork Tue Jun 18 07:46:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117683 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="DiM1ZPkH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgCm5WYlz9s00 for ; Tue, 18 Jun 2019 17:47:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729194AbfFRHrO (ORCPT ); Tue, 18 Jun 2019 03:47:14 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14184 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726238AbfFRHrN (ORCPT ); Tue, 18 Jun 2019 03:47:13 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:12 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:47:12 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:12 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:12 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:12 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 14/17] arm64: tegra: enable wake from deep sleep on RTC alarm. Date: Tue, 18 Jun 2019 00:46:28 -0700 Message-ID: <1560843991-24123-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844032; bh=yDxMxfPTCgsxiYAL44L3iSaV2tcgK1454UaiFZ8F9DY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DiM1ZPkHoJ3e4hCEshegM+ypO5Nk6Dg+7HkEwkEqAHgpFP9jPBYMzMQOilOP/K1ov X8UlnOJeWLoDr4sriHXCFNdJn/1pyP7ALUK9+qbklirmCiwgGBahjstHa4okk65dC3 rKc+yWPHnwTD3m01H9CjFenyQpl3MdiLt9Y823YvQqknkZRU5Nt3KE48DfwdsEQiJT EkPeBXAFzI4iX1g1t+3rUl6CkuNR5HAscbtr/B6Sbtkq8/y104qW3J942jCow7NtUb fpv1M7y0+pTo+SfudFOwS3/ixI3XZYEtUHjkuAMBgpmysMzqS+koukOFctJoaQjy+8 uUpWa0yKwlNsw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index edf27fe2f10e..d284bd6088af 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -763,7 +763,8 @@ rtc@7000e000 { compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; @@ -773,6 +774,8 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #interrupt-cells = <2>; + interrupt-controller; powergates { pd_audio: aud { From patchwork Tue Jun 18 07:46:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Wkp4Qxu1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgCm11QHz9s9y for ; Tue, 18 Jun 2019 17:47:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729214AbfFRHrR (ORCPT ); Tue, 18 Jun 2019 03:47:17 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14193 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726238AbfFRHrQ (ORCPT ); Tue, 18 Jun 2019 03:47:16 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:15 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:15 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:15 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:15 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:15 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:15 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 15/17] soc/tegra: pmc: configure core power request polarity Date: Tue, 18 Jun 2019 00:46:29 -0700 Message-ID: <1560843991-24123-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844035; bh=ZIM1lgKmGOLI8vjBUZA7Djdy5mObSNe1HI0kza+VS88=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Wkp4Qxu1JqsaH8jdLmvAIkoRC95+Ax2jKrePMPbf+rOcKLuTcrM9b9uJQyWNi8E7V BCX2c8EhvV06SxEXy4k98Gw3gWjzK3zFXdarlfVBEANy8yIyR45GV5a8HF47Bpx7TQ F8szrzHmPD0mZYmcCVm7FLCq6dYFaDjOH728DNWqXu5YfsKRcVDMGFBVkzmnHBHMqC gkfbXglYAP1LDpOd6SOBkIET/b+YmHq2poXiI1k9Y9yJZOQ1JWaoBo+SIDL/Iiinlv N0TmSvRWUM1pr44OxVOLhFnqUVBPXmjatk/w1TEmfPrHDylCV9kS7KlbgsGZdvxAzQ hnxLNiPFjE7KA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 603fc3bd73f5..c9eea5ef008a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -56,6 +56,7 @@ #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) #define PMC_CNTRL_MAIN_RST BIT(4) #define PMC_CNTRL_LATCH_WAKEUPS BIT(5) @@ -2304,6 +2305,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) else value |= PMC_CNTRL_SYSCLK_POLARITY; + if (pmc->corereq_high) + value &= ~PMC_CNTRL_PWRREQ_POLARITY; + else + value |= PMC_CNTRL_PWRREQ_POLARITY; + /* configure the output polarity while the request is tristated */ tegra_pmc_writel(pmc, value, PMC_CNTRL); From patchwork Tue Jun 18 07:46:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="OB9/UxJy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgCj41jHz9s5c for ; Tue, 18 Jun 2019 17:47:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729235AbfFRHrT (ORCPT ); Tue, 18 Jun 2019 03:47:19 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19691 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729226AbfFRHrT (ORCPT ); Tue, 18 Jun 2019 03:47:19 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:18 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:18 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:18 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:17 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:17 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 16/17] soc/tegra: pmc: configure deep sleep control settings Date: Tue, 18 Jun 2019 00:46:30 -0700 Message-ID: <1560843991-24123-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844039; bh=nQJmjDHX/yyz71fC5Ramf2lDdXrwkLYirADexX5oFCU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=OB9/UxJyZ+AG0aOpRR1NfNDxjMOzFg6yaSD0RkvrR/nkxWcSxlrQIhNyp08qu4bqF mc3bSzjBRkcKi+/QmOsuqURXHxkL5HmEbwP9fUtQElV7IP6ue/UFHbYWH4reGbeNFH GQHEVzXK4shiMQgFqBKYGmQryX9RpdPUvodtlBBPXWdfFoGxGETUiTNFR7wQhaRFos YBpmbb/V79N7A9CI+Y3uoyvQ+Jwl9zpovqBiRVY9p4NknXrVPq+l5SNIfEdTCdxATc zEhDU8C59HI3GImfFXPi2s8JK6PiVFxau46UrEbM3dhoBFsaH1zsJfbYDaX/3Okxn7 /XfU5qxT3W6dQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 and prior Tegra chips have deep sleep entry and wakeup related timings which are platform specific that should be configured before entering into deep sleep. Below are the timing specific configurations for deep sleep entry and wakeup. - Core rail power-on stabilization timer - OSC clock stabilization timer after SOC rail power is stabilized. - Core power off time is the minimum wake delay to keep the system in deep sleep state irrespective of any quick wake event. These values depends on the discharge time of regulators and turn OFF time of the PMIC to allow the complete system to finish entering into deep sleep state. These values vary based on the platform design and are specified through the device tree. This patch has implementation to configure these timings which are must to have for proper deep sleep and wakeup operations. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index c9eea5ef008a..1b2ecda88a26 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -89,6 +89,8 @@ #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc +#define PMC_COREPWRGOOD_TIMER 0x3c +#define PMC_COREPWROFF_TIMER 0xe0 #define PMC_PWR_DET_VALUE 0xe4 @@ -2292,6 +2294,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = { static void tegra20_pmc_init(struct tegra_pmc *pmc) { u32 value; + unsigned long osc, pmu, off; /* Always enable CPU power request */ value = tegra_pmc_readl(pmc, PMC_CNTRL); @@ -2317,6 +2320,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) value = tegra_pmc_readl(pmc, PMC_CNTRL); value |= PMC_CNTRL_SYSCLK_OE; tegra_pmc_writel(pmc, value, PMC_CNTRL); + + osc = DIV_ROUND_UP_ULL(pmc->core_osc_time * 8192, 1000000); + pmu = DIV_ROUND_UP_ULL(pmc->core_pmu_time * 32768, 1000000); + off = DIV_ROUND_UP_ULL(pmc->core_off_time * 32768, 1000000); + if (osc && pmu) + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), + PMC_COREPWRGOOD_TIMER); + if (off) + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); } static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, From patchwork Tue Jun 18 07:46:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1117679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="rKHUB+Hq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgCh4NyBz9s4V for ; Tue, 18 Jun 2019 17:47:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729254AbfFRHrW (ORCPT ); Tue, 18 Jun 2019 03:47:22 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9740 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729251AbfFRHrW (ORCPT ); Tue, 18 Jun 2019 03:47:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 00:47:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 00:47:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:21 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 18 Jun 2019 07:47:20 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 18 Jun 2019 07:47:20 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Jun 2019 00:47:20 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V3 17/17] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Date: Tue, 18 Jun 2019 00:46:31 -0700 Message-ID: <1560843991-24123-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> References: <1560843991-24123-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560844041; bh=Vsp36/vqBLGzaHV4U5nFiJBH5J5qqVmQ31C7uPAHcPk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rKHUB+HqOYKLOeLs3gxU+2VJICl873Ak0DxOzwmFxJZtt4Rp0tDiqJwLoQAf2qHEe bFfkRful2dQCxQoJuqpkTKOVj4/yD2dC6WT7xi8zRhobYnUS4uKcOa+Yzn3ey5QgUc iSSNhOqqtjMwLwlrTl3kgmE/K7AW0VcJil7Z6O5Rspqz0LKi9ChNJwkIvBaYQMxG8F +/yJ75T4Rigjpd8SWCxauF8IkDj+H9CfO3QTSOjKyE1FXg0TBAwt3gCM/rxMHKBkGq kl71f1CHD6tzP7ABi5ojSXQHJQ1cZBpvdEve42/MNE67nkDNUDldpsob1DTwJxfo4X Z88pVPot5Alnw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch has Jetson TX1 platform specific SC7 timing configuration in device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index e8654061ce03..f7c9332085f8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -279,6 +279,13 @@ pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; /* eMMC */