From patchwork Wed Jun 5 14:39:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Edelsohn X-Patchwork-Id: 1110514 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502397-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=temperror (0-bit key) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="GqL8mPHD"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="i/TmHZ8+"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45Jrz61QTBz9s3l for ; Thu, 6 Jun 2019 00:39:28 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=oihoFCqsOdkHm22Ssw58tSp9LH8p42pVVn1I2Dr7Nn3w/D SJuB+w8wE1d1cOdOR59gINj3pWn+omzUIE2Thm2AGdkEitn4eyCCXfkXYtWsyRwL pJVg/AkWZ+VznGy8HKmmqgMfisqTo7wiGreU4Wwwe84tzZzlDdhmzntJ/vv5I= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=gDB/mnGBGaf6X1x5wDqbrv28Ylg=; b=GqL8mPHD6EO/tusxtPzH kc37GIltxIvLzqW/OePGVLCS01evvlD/rBO1J7Kr/v72YXiCjdBNmGCQGd8g2FZJ XnBkJ9MWnK+eNC9+7A9AY3fBfJfWRgst3Ety+m0vJhMDwHqpU+RKezjWKq7dXL29 THD87MBGnoTnTha2mlfA6Vs= Received: (qmail 28246 invoked by alias); 5 Jun 2019 14:39:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28237 invoked by uid 89); 5 Jun 2019 14:39:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Gm-Message-State:APjAAAX X-HELO: mail-wr1-f51.google.com Received: from mail-wr1-f51.google.com (HELO mail-wr1-f51.google.com) (209.85.221.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Jun 2019 14:39:19 +0000 Received: by mail-wr1-f51.google.com with SMTP id f9so5010760wre.12 for ; Wed, 05 Jun 2019 07:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=TLKmk9l2OK75nOq710qz5enH5/41mdPxOkAPoDmlKAo=; b=i/TmHZ8+o8R30yPbva0l0vhkU6ofgM6mgYE2POwB+hyIdThLYbAWsfQHfsFVi1vHzp v5s/mVOKSo7gsnDZ1fN+vtzqtx6WXdEp8GOJThzxPxPkC9/sWilL6VHIiN5oOSYH7Xri vk85k3qbwImquTlzrRgLVWwzakO7dbiG3I0x87SI6RxQSojMlp8IycMG/ow6idxrCU12 umnOiEKCar71tSesQOk5DktW2ZT5euDcQbrVKmI5A4XNXKwDp/GCexoEO7Ob5GdWB7DQ jLV9c3x4PJpg+mUpe5J8CP/TIa+psiYHbAz9COjUw+3NR2/ymElHZR2UFYtv8tkaDUv0 KAmQ== MIME-Version: 1.0 From: David Edelsohn Date: Wed, 5 Jun 2019 10:39:00 -0400 Message-ID: Subject: [PATCH] AIX unwind register number fixes To: GCC Patches The recent changes to rs6000 "debug" register numbers created a conflict in libgcc aix unwind support. aix-unwind.h provided definitions of the DWARF register numbers for its own reference. After the internal register number changes and the definition of those register names in rs6000.md, the register names appear in insn-constants.h, which is included by libgcc. The macro definitions in aix-unwind.h now conflict with the versions derived from rs6000.md. This patch changes the aix-unwind.h macro names from XX_REGNO to R_XX, following the convention of the other unwind files in libgcc to avoid conflict. Bootstrapped on powerpc-ibm-aix7.2.0.0. Thanks, David * config/rs6000/aix-unwind.h (LR_REGNO): Rename to R_LR. (CR2_REGNO): Rename to R_CR2. (XER_REGNO): Rename to R_XER. (FIRST_ALTIVEC_REGNO): Rename to R_FIRST_ALTIVEC. (VRSAVE_REGNO): Rename to R_VRSAVE. (VSCR_REGNO): R_VSCR. } \ @@ -56,7 +56,7 @@ { \ unsigned int *insn \ = (unsigned int *) \ - _Unwind_GetGR ((CTX), LR_REGNO); \ + _Unwind_GetGR ((CTX), R_LR); \ if (*insn == 0x80410014) \ _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 20); \ } \ @@ -241,9 +241,9 @@ ppc_aix_fallback_frame_state (struct _Unwind_Conte if (i != __LIBGCC_STACK_POINTER_REGNUM__) REGISTER_CFA_OFFSET_FOR (fs, i, &mctx->gpr[i], new_cfa); - REGISTER_CFA_OFFSET_FOR (fs, CR2_REGNO, &mctx->cr, new_cfa); - REGISTER_CFA_OFFSET_FOR (fs, XER_REGNO, &mctx->xer, new_cfa); - REGISTER_CFA_OFFSET_FOR (fs, LR_REGNO, &mctx->lr, new_cfa); + REGISTER_CFA_OFFSET_FOR (fs, R_CR2, &mctx->cr, new_cfa); + REGISTER_CFA_OFFSET_FOR (fs, R_XER, &mctx->xer, new_cfa); + REGISTER_CFA_OFFSET_FOR (fs, R_LR, &mctx->lr, new_cfa); fs->retaddr_column = RETURN_COLUMN; REGISTER_CFA_OFFSET_FOR (fs, RETURN_COLUMN, &mctx->iar, new_cfa); @@ -268,10 +268,10 @@ ppc_aix_fallback_frame_state (struct _Unwind_Conte for (i = 0; i < 32; i++) REGISTER_CFA_OFFSET_FOR - (fs, i+FIRST_ALTIVEC_REGNO, &vstate->regs[i], new_cfa); + (fs, i+R_FIRST_ALTIVEC, &vstate->regs[i], new_cfa); - REGISTER_CFA_OFFSET_FOR (fs, VSCR_REGNO, &vstate->vscr, new_cfa); - REGISTER_CFA_OFFSET_FOR (fs, VRSAVE_REGNO, &vstate->vrsave, new_cfa); + REGISTER_CFA_OFFSET_FOR (fs, R_VSCR, &vstate->vscr, new_cfa); + REGISTER_CFA_OFFSET_FOR (fs, R_VRSAVE, &vstate->vrsave, new_cfa); } } Index: aix-unwind.h =================================================================== --- aix-unwind.h (revision 271883) +++ aix-unwind.h (working copy) @@ -24,12 +24,12 @@ /* Useful register numbers. */ -#define LR_REGNO 65 -#define CR2_REGNO 70 -#define XER_REGNO 76 -#define FIRST_ALTIVEC_REGNO 77 -#define VRSAVE_REGNO 109 -#define VSCR_REGNO 110 +#define R_LR 65 +#define R_CR2 70 +#define R_XER 76 +#define R_FIRST_ALTIVEC 77 +#define R_VRSAVE 109 +#define R_VSCR 110 /* If the current unwind info (FS) does not contain explicit info saving R2, then we have to do a minor amount of code reading to @@ -44,7 +44,7 @@ { \ unsigned int *insn \ = (unsigned int *) \ - _Unwind_GetGR ((CTX), LR_REGNO); \ + _Unwind_GetGR ((CTX), R_LR); \ if (*insn == 0xE8410028) \ _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 40); \