From patchwork Fri May 31 16:00:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108424 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq1D6vPgz9s3l for ; Sat, 1 Jun 2019 02:00:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A1AB6C21DD4; Fri, 31 May 2019 16:00:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4523C21C51; Fri, 31 May 2019 16:00:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B080C21C51; Fri, 31 May 2019 16:00:43 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id A161CC21BE5 for ; Fri, 31 May 2019 16:00:42 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MHnyM-1hLEhD1fhm-00ExyN; Fri, 31 May 2019 18:00:34 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:15 +0300 Message-Id: <20190531160020.9755-2-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:PWk8bfsDPh+dcKb835UjyGlt5WAuBS9kOKbdbc0svHE79F/2gDe Wvk0ajPeE+Cm54R22T4W0VmwaJ8GPs0sA4UfTIEbgcxx1BHMm4iTy57FDbuvWpcbUmWnTl/ Wvkj18xsKr6LI1qewVTD1z5SryWUxYnZsN5vbtxtJSGiwAbkZzvxC11absA78gZQgqCxN2t TrzBTqoDCdhlPNnnR6PuQ== X-UI-Out-Filterresults: notjunk:1; V03:K0:WM4B/DEmZWA=:gv/kLcY4BVLctrBvFV3W5E Arw4Tb/O+AlHWwKMOcCqPe/SI4WQy2ayceTG0ykuEtdPYiqtACR2s8JlKoes1EJ8kcLuudYME 3JxDolH84q0lLIFurAc2p2Z1yuMqBTmEsk85jGfovj74qJNK8LaAnQ85MNDxYFMnQFnAhvQpm 1lci/037ee9Qg8iqHEPUYEU3BuRtAboCcnASHNJKi0PLAkSxpfOG12HSgd1I+It2bB1a4Dx6B e6n3i63dAwcIkGubhzYOszPxOiVRSye75tTZ/Oui6C6ShOSAjp0Sks9AnGQsLa3R624MqO41G 4AaQffmkWgzOpo5p9HtigZQmH51Y8+tcO1hfKqMju9wubeYWHlMCWSnUKYEAi64Icx3Fj2xG9 S9aAiP3tVjONOShPiyLhiK9+0OkoEceumBgvVhpobS+PIpQ4ShcPamU+k5ioiyevsVUS4Fa6D jEVR6BuksMuNsXMsJEyDLD5gCeH+4sW3IAz/oreMOLuQ+JheAAL3Xy+XN2LYyxf4wHvvU81wa oJcIfl7y/xofwWQXOuBGuO3ZVCnCDb3ZYcQ3meoKXswlvRR23uWwgw3qednZm9TG/WXwwWfQ4 zRSHut7jiZqiN5OMIvXQKUJKYt220HnkEbhoYoNHBttozJW+egCOHv8rbVMxATBcpuFFCBI8g 1vaxFUFzz8HbP1mOXBm+mm4sK+15ViP5O7tvuhZ7Vh9tqKWlvoG7KcI6jlZwqFljlCqq6WmDh enei1YbDqwDrQjQ5xdTIn5denl+sQQXVxB13kA== Cc: Tom Rini , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 1/6] arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, lpuart4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler Add support for lpuart1, lpuart2, lpuart3 and lpuart4. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None arch/arm/dts/fsl-imx8qm.dtsi | 80 ++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index b39c40bd98..db01959990 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -22,6 +22,10 @@ ethernet0 = &fec1; ethernet1 = &fec2; serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -193,6 +197,30 @@ power-domains = <&pd_dma>; wakeup-irq = <345>; }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <346>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <347>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <348>; + }; + pd_dma_lpuart4: PD_DMA_UART4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <349>; + }; }; }; @@ -297,6 +325,58 @@ status = "disabled"; }; + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART1_CLK>, + <&clk IMX8QM_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART3_CLK>, + <&clk IMX8QM_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + status = "disabled"; + }; + + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a0a0000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART4_CLK>, + <&clk IMX8QM_UART4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART4_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart4>; + status = "disabled"; + }; + usdhc1: usdhc@5b010000 { compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; interrupt-parent = <&gic>; From patchwork Fri May 31 16:00:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108426 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq3P0MDNz9s3l for ; Sat, 1 Jun 2019 02:02:41 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C0D2BC21D74; Fri, 31 May 2019 16:01:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BDC1CC21DF8; Fri, 31 May 2019 16:00:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A4066C21DD3; Fri, 31 May 2019 16:00:49 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by lists.denx.de (Postfix) with ESMTPS id AA9B1C21D8A for ; Fri, 31 May 2019 16:00:45 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MUXAC-1h6J8e0slc-00QSRZ; Fri, 31 May 2019 18:00:36 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:16 +0300 Message-Id: <20190531160020.9755-3-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:IehW6/qb7pkSw7yQW9usdDt+je+dtfpZn9BbcLS8EYe283fHoWX /euPcD2rOYO2Ta1pMkAxzN2I+7mxDsARIrVO4yXfklvGi1YDY4sGSW5mQqWWK40Z2vo7V6R S82UHlcFkgWktedULhHpe7aUCI3wmVNka1YAXSCiSKOLdwb0ZCWE7OhZgQ0nhKQRksp7ZwL 9VhjMyQTMPmv2Zn6sUvUA== X-UI-Out-Filterresults: notjunk:1; V03:K0:hgYLkOd8h4w=:iDOZrsBAx0xfSHGw97fFTy G0TEtotoKryiVw25ATOYOe8lgEkix8mwPwx2McW9AELFJhkaD6zMB7Z8boDz4Z5AB5/SXTiqW Pdzt4VUXlYzdFV8NCvBr6y09UgNauNYELS0308IWcQS6NiMBIIole93YcXPGBToSnDYxXeMqV T/oJAk5fw7GAR1voaqdM4WMlPdOrnPT3KNaFe2miKZm8hLxCBMSKg/P+8rV6cI7nd49lSCXoD SgQvJSSBb8leOKNkyq186blip0U+f3WfdmpWjt1twoKXdub5GcxIPMkgIz8ChAhaQfx8flo+v 2Ov17fjei0n2rV5usqD8kisIHLMucf8/lcscikNtNJXELiFdcg6YIGDqdxtGMLnNq70iu+CVJ KjrpJMonXTeyTyWWG2oLQOzigk1+6DcMl8ijJ/G6AdZSrIb43a2qQtnmftF0L/Ul5A6yELyh0 hvaqIKhsvzT5yg+HPUaJ74Dx4FWmLWZNQEJVhGoDcrcFXgkGPVqOulrvdgBigSf2ZRvLcf13K bn+qhVt6r/N+E9+d35Cux6UdOsaG5vk/r5/5pSy+0gh23pn079A20IW0g1W6VLnoR2p7rG+42 D9VkYlgY5VP5ltYSv8xOVnOl3Dyaq1R55836o8YH28qrUtZ3sWhMF4Vo7ye9Y05762/jjin9f w51GRq4+hPwXGUTWFWOipW+sP0XhXOemW9tGv1Puh4wEtHLTwaMRtDjFGq9x6ywj7mJ75onGV JeMPVepInx6nINPzXxZWIdTAxYlqkeSDQCJJcw== Cc: Tom Rini , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 2/6] arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, i2c3 and i2c4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler Add support for i2c0, i2c1, i2c2, i2c3 and i2c4. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None arch/arm/dts/fsl-imx8qm.dtsi | 75 ++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index db01959990..af060db3a1 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -29,6 +29,11 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; }; memory@80000000 { @@ -224,6 +229,76 @@ }; }; + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C0_CLK>, + <&clk IMX8QM_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C1_CLK>, + <&clk IMX8QM_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C2_CLK>, + <&clk IMX8QM_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C3_CLK>, + <&clk IMX8QM_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a840000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C4_CLK>, + <&clk IMX8QM_I2C4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C4_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c4>; + status = "disabled"; + }; + gpio0: gpio@5d080000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x0 0x5d080000 0x0 0x10000>; From patchwork Fri May 31 16:00:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108425 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq2P60vFz9s3l for ; Sat, 1 Jun 2019 02:01:49 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 69661C21D8A; Fri, 31 May 2019 16:00:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4D55CC21CB1; Fri, 31 May 2019 16:00:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A8A4EC21D8E; Fri, 31 May 2019 16:00:49 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id ABB6BC21D8E for ; Fri, 31 May 2019 16:00:45 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1N8Won-1gSaXf3eQT-014S68; Fri, 31 May 2019 18:00:39 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:17 +0300 Message-Id: <20190531160020.9755-4-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:eYFK6HOc0ZCENAI30i2tZbqt5At7Hm8eCxOUnpWfawxKTw5ES2K WiEx3V1hxAot/G8WT8neJ95xtbzY+5gCUQomfcn4oRLjpelpjKVknXa4EXmDgoyA6YF2leb zc3AXS0wRpYLpzKcSdaXHDdfrDMmlJP/9RP9lKedPKUjIkXqAmGN4H7PrUr+ajOObjB6tHj hH3epiSie7Z30oyj1PYgg== X-UI-Out-Filterresults: notjunk:1; V03:K0:2pcmDqVtZ0g=:RYxV+PeQLdi54CA6gs+Co9 MWU0Bx+FPK/zIyuBDKWqM8vm+ZF4Zwb9m0AkLN8N03Rl0PTqfN3AIQ0gSGXr6zerGh51qAJzx LccLeY+EkHpCSumRlfyoWbwc39oeZrg4zbDWYvjtBr9hphQbZcflXyMNT+RyXJluVMXL89bzy 23NE0aEB4SBA8t5nS1t8hGqAXtIgF1oV2thU6TLFe4keN3imu29AmD1oG6Kf4qaNY1foVmwNW U2/KOMGgn1uafYpdxnF/kfTCgJb6XgdKaC7VppwzfWuzgtHtAJoEmJKbALLwFMgBANl0j7lIb onyNgudEWuRi5/GX5OJ5rgm7W1qUi9IurobuoRLybjqMBOCEmSPhk1/cu3Nqw3Eg8g+QzhQi8 X8mHkMwSEopJ2gp+XwtvJFp1GgbZ9Cb72lBw9KjCC4hs4Zc4Dcsz8YG0gjnNBHWqyowCeFEW5 d9sCOyeLjjqzOJBwVO0ihaBBrPANWzB8sxF0+pIMyC7sIZZ7x49NKqlwy0VM417e/dl94Ill4 pis3PcYDquE8/rSWrqMl+k0GghChlkHcjOtXJv868s2i2SyPE5atFOr+DApDtBHUJ0QjTT1U+ GaUkzxH2+Egbd/TiBYk94nVkcX/9FnYDJZ3hAMO/528uMwnuRPXHcmPPIqdQ1UEAXoJ26lWVu Y3cPOwZZ0RBrEQKnHGUQDkHz2h6yVKhgtc7a/4eq9aPe6fVwfbQ6XUBTSpBjkDXKd41+siEjd HpTADUI3rbveLoX0OHo5NuMrMWyTdUe2teRdSg== Cc: Tom Rini , Marcel Ziswiler , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 3/6] clk: imx8qm: fix usdhc2 clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 6b5561e178..a6b09d2109 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_UART0_IPG_CLK: case IMX8QM_UART0_CLK: resource = SC_R_UART_0; @@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: @@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: From patchwork Fri May 31 16:00:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108428 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq3k3j2Kz9s3l for ; Sat, 1 Jun 2019 02:02:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D225AC21DD7; Fri, 31 May 2019 16:01:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 45BD8C21E0F; Fri, 31 May 2019 16:01:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5B31FC21DED; Fri, 31 May 2019 16:00:55 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id 8A1CAC21D8A for ; Fri, 31 May 2019 16:00:51 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1Mr8n4-1gmAvf4Ady-00oIn5; Fri, 31 May 2019 18:00:42 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:18 +0300 Message-Id: <20190531160020.9755-5-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:x0hVm7QimzUX8LG47+lpLFvDNUBTV104ormnbHcR6NaUQ3TCL4Z /KsHyCd+X39iV1nmscgf1FQChCWlmls2HFHP+HjjKXvz41eg4+JHlN0Cw+7TBGWqB9XzASy A5fnjlz17swZV746x6OOYAWecVCXWQg71wDmV3rzd7pEI/afnAaVSnk6Kk/ENcYEYM4lDC6 L3GOPBouVWpyxZhxQjneA== X-UI-Out-Filterresults: notjunk:1; V03:K0:l57rZaECsxI=:zxYq2Yvd00QxtL0QbRsSP/ uj7rJtfP8/fmOtF4wRIHx9UMoA1qlGg5WliKthycQ+aONOXmYclWFwT8g6EVr0M1GsfZQLvk1 aynMGA7dwZNEWjMSo4wQX3KK8Filo0u6rsswx7JGiU8iysECPZxrqlVp7Sk2eJFHImBxa1cYR 8DivVQLWlSucMDjtG8NfC4T/yL94f/B1DHgweKOALeLn1/wF8tGL7b8FIwPk8Lv4+E15Zuowb 2ahfnjBAhn11lKfUxmbsSDulnPlkyy2RRuAo2Hr42vPpQIZNNaDRWuyGdv5p4aNS/ai2PJ5r8 eTNp8wrmItO5DWVOoMwMYirLtIBUPRqipTX2+/eX6Lt6dZp8S6Bd4KXS1M2jhIkymMV5h9wp6 6boOhf6kEhcb398ys2uKknIGOXVK/k95hPlcqbZEbHFiIl2FHZcIc8ME53o2TB0cgB8Y0ka33 qItH+rmxlTsvX2jESAkkSnDwgP+Ibt7Wk2I6i53dMapZuoAhk2MXvEJUkIJYmKerI7y6otxBr nP1QFcqXV5YGiJ7VAC2a60m9jPBwHUeIQhkL/9VxFEDKOK7E7w6RxkJBM/fOUjZqBcMtNHvFN kOO28oFOK+d4Oyrf3g0JLtxS99jJgIxaw6xHZTyKTG5CtshPP21NE3IJc9c51Z+gxtVMn+vLY NNvb5TSLaXE6pAn8Ej8TlghY0bdOuT0RGh5TqhxSq6JuHQ32yyAl9/QOQ3VYfw0NAReG/EcLR U06IDRmKi1vwyk+6neIuH+PmThkSp83X4i7BeQ== Cc: "NXP i.MX U-Boot Team" , Marcel Ziswiler , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 4/6] imx8qm: fix cpu frequency reporting X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" CPU frequency reporting failed with the following error message being printed: sc_pm_get_clock_rate: resource:507 clk:2: res:3 Could not read CPU frequency: -22 CPU: NXP i.MX8QM RevB A53 at 0 MHz Fix this by differentiating between the A35 as found on the i.MX 8QXP and the A53 as found on the i.MX 8QM SoCs. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None arch/arm/mach-imx/imx8/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 53f9a8735a..aa78444d8f 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -623,8 +623,10 @@ static ulong imx8_get_cpu_rate(void) { ulong rate; int ret; + int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ? + SC_R_A53 : SC_R_A72; - ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU, + ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU, (sc_pm_clock_rate_t *)&rate); if (ret) { printf("Could not read CPU frequency: %d\n", ret); From patchwork Fri May 31 16:00:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108427 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq3c2r5Gz9s3l for ; Sat, 1 Jun 2019 02:02:52 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id EF545C21DFA; Fri, 31 May 2019 16:01:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 75E36C21BE5; Fri, 31 May 2019 16:01:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 979FDC21D83; Fri, 31 May 2019 16:00:54 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by lists.denx.de (Postfix) with ESMTPS id E98BFC21DA2 for ; Fri, 31 May 2019 16:00:50 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MXYdX-1h5U3v1tZn-00YxpS; Fri, 31 May 2019 18:00:44 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:19 +0300 Message-Id: <20190531160020.9755-6-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:YUrGG2tb0MmaEQHCuAcx92w8oUmokAIiVgqvpuPRtQ/wXvIRni1 GttGjoYms9KIbZsh8r882OgS2gknHEWTMaPO5uXjp0+rb2UY1maBXIrE/PhILzfCqUKgw8+ r+7C5J8CFQmbcfwn3AnP29XCCVzUZ+IBU1ftSFS4pScdXnSR0myfSjhX5SkToJ8osXPN6y5 KP8if8eQk41zszCTWxkig== X-UI-Out-Filterresults: notjunk:1; V03:K0:1n+Cb3vCL1s=:iDqPuZBRRhs2jyFdwa06Nw ZP+w7o2yi2ZtP1aw8YOMIo3M796U9JCfF10Ntccm1A8C5BIs6QS97JhtcN7sZ9mxqOd48svox zAsM/6jooLjFpIXefZ2HeMOnWTcJrTahNE3VuPsw7qyTt3AhAQyB1UYj3P04groCxnAAlInM4 hskYk0VWw84Rn5ucYOnmg8MBRt0nVCo56Veznf5BxNWELZJiiQHrgJ9Mn0iLzT0VU18S4jPu6 p8RaABD8n8QkKh/7KOo2Pibctn6heiv1P0otre65Ic4dXEz5qLCDIp9bvnUt5BezygdqtXXDC v+I25zVjTFLDViLJ6/Ew7I+iLxiscudLNR1RFO8pxYyNHle567TmIHF1SnkEPlCDqKXrJmGB+ OljjEdqAd2bIC1BGZLRFKbAMBNxIFmks/UNvvmG/lAE4+NpBjT4tQTjcxj4eF2VFvFgqWdrSy JxIMj+8bGMQfxv3t09x52zao5lr/ScfYgs7SJfqtwwdTBGmApZzFJ3oBSvn7l7HpYN46CXHi6 /TnLGIpA+g9HH7axtTOFUGiOxMX3D7Hos8aXYc89vVRRByKBxfN2xA9TRdJylQlIiDGNoOppL lehckv29mvWM6oLJdGyxraw4Z0X9+8zCOGb4S9srofLEPcY9FOtkX6+OWsDkzwPTtmLHOlSBd 4jXpHyB4kFjYJDzvj+7gumoSIiFcl5ztjWYuqCnxMyqXDzBZ7kk43+U5PSkss/G1HdD7OeIU0 ynW0Uv1fpk/rD+QzJY+90CTyTwjXPuwlDfQiQg== Cc: Tom Rini , Marcel Ziswiler , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 5/6] imx8: fuse: fix fuse driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This fixes the i.MX 8 fuse driver to actually build for i.MX 8QM as well. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None drivers/misc/imx8/fuse.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 29d2256a22..2f2fad2c17 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -15,13 +15,11 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_ECC_WORD_START_1 0x10 #define FSL_ECC_WORD_END_1 0x10F -#ifdef CONFIG_IMX8QXP #define FSL_ECC_WORD_START_2 0x220 #define FSL_ECC_WORD_END_2 0x31F #define FSL_QXP_FUSE_GAP_START 0x110 #define FSL_QXP_FUSE_GAP_END 0x21F -#endif #define FSL_SIP_OTP_READ 0xc200000A #define FSL_SIP_OTP_WRITE 0xc200000B From patchwork Fri May 31 16:00:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108430 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq4d4Kvxz9s3l for ; Sat, 1 Jun 2019 02:03:45 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0BBDEC21C8B; Fri, 31 May 2019 16:03:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 68E29C21DF8; Fri, 31 May 2019 16:03:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2517CC21D72; Fri, 31 May 2019 16:01:13 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id 3270FC21DFD for ; Fri, 31 May 2019 16:01:09 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MofY5-1gmRlx417Z-00p74O; Fri, 31 May 2019 18:00:50 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:20 +0300 Message-Id: <20190531160020.9755-7-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:07VXQoMKQbxvaXilDyfse8C3jc0Kir4+QX1FYocQbPfKAD4PSlt TBgO+XAAAGVagy0qFIM+alhPigimy0g8POBCB4q3xM84kPZgBWdvHYXTRxDh0SSrQXBazXn BFoesixLT1UkvtNX6zvhY7FSM+RzMG2phAIsVFCoIXtdoEfqXJa+vWNGNHWgEMwzDBSG5va oNCUQEzce9H60YhJPN0SA== X-UI-Out-Filterresults: notjunk:1; V03:K0:ZkuNQByhDcU=:8aE4LmBtfl+At+MQ+L1uL7 pC+F5i1JHNxkWQyEPuSJJB7UxV0a0p1QBi69m9T1jvdWwjxk9FxW5eD3xka7f2BQ5eei92MG4 lrgLMnMWruVhl38Qz9TA69qe/74iDraacxKrmB1TEVnZbdICMM7hlCZ7UCbctcrvyTViZZYBY EYgWvJWdtt/b0Ap2LWiIGM059t0GCutXi/M1lt5vhiuvRmUbxyK/1W78n3mzPl4wzu2ika9At ZllaA9tifQSMjAiJ6G5ceiWKqNX8Q+mYH+oGfMzYYZ5uypUKevzH/bTXUZTRirHWioH6IfUpn GZt5TxWruR2KNh0xNpFPEUpqVOaWJNhO1HQtd+dE8m+rVN2FeRLCivtOttfwVKCtERoxZkJ53 Mz0hMK72rADqYNDq3gB4fTtcg/wAB1tutRtbzjJvsoObQsichn9HUAnmqtsdSmC2SrqO/nDEW jUWEW6zyQ/HhBAKQ2UwITdu4+fiWgwBtlbQmAC+N1ppO8/5PEdqJiI/z3j/JOThEiJEZaLKuK P+VYBO2I5767ac7iZvLq1458H6B0+mtfw+yUD5NCLDwLPTnSg5XrYGhiJ36nsl1m3I1WV+/jL Mgl+b4BKL2rlOVl6+UOjxdhZgImD6IMWkOyovnZa+mzEm0ANJ0vxPWhUX6I/DkZgobAt63oxH cui7igjQC88QneNTWFE7z66t+Oj5jNUdLaLITuRSXWdDCL0XaVGSK0MpV9HtCIwi3gJUZbqCL I9b/d0pQkNF03ISs4yTA8Xk2JvuMVfjDMkmXPg== Cc: Igor Opaniuk , "NXP i.MX U-Boot Team" , Marcel Ziswiler , Michal Simek , Max Krummenacher , Stefan Roese , Maxime Ripard , Marek Vasut Subject: [U-Boot] [PATCH v3 6/6] board: toradex: add apalis imx8qm 4gb wb it v1.0b module support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler This commit adds initial support for the Toradex Apalis iMX8QM 4GB WB IT V1.0B module. Unlike the V1.0A early access samples exclusively booting from SD card, they are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports either booting from the on-module eMMC or may be used for recovery purpose using the universal update utility (uuu) aka mfgtools 3.0. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Gigabit Ethernet - GPIOs - I2C Unfortunately, there is no USB functionality for the i.MX 8QM as of yet. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: - no longer explicitly disable CONFIG_CMD_CRC32, CONFIG_CMD_EXPORTENV, CONFIG_CMD_IMLS and CONFIG_CMD_IMPORTENV - increase max gunzip size (CONFIG_SYS_BOOTM_LEN) to 64 MB - rename board file and folder to more generic apalis-imx8 to be used for all SKUs - just exclusively use distro_bootcmd trying SD cards before eMMC - enable FDT relocation - added update_uboot helper wrapper as internally suggested by Igor Changes in v2: - Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as suggested by Max. - Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config() stuff not applicable to the Micrel PHY we are using as suggested by Max. - Drop CONFIG_FEC_XCV_TYPE in favour of device tree configuration therof as suggested by Max. arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 128 ++++ arch/arm/dts/fsl-imx8qm-apalis.dts | 615 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/apalis-imx8/Kconfig | 30 + board/toradex/apalis-imx8/MAINTAINERS | 9 + board/toradex/apalis-imx8/Makefile | 6 + board/toradex/apalis-imx8/README | 66 ++ board/toradex/apalis-imx8/apalis-imx8.c | 149 +++++ .../apalis-imx8/apalis-imx8qm-imximage.cfg | 24 + configs/apalis-imx8qm_defconfig | 56 ++ include/configs/apalis-imx8.h | 131 ++++ 12 files changed, 1221 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qm-apalis.dts create mode 100644 board/toradex/apalis-imx8/Kconfig create mode 100644 board/toradex/apalis-imx8/MAINTAINERS create mode 100644 board/toradex/apalis-imx8/Makefile create mode 100644 board/toradex/apalis-imx8/README create mode 100644 board/toradex/apalis-imx8/apalis-imx8.c create mode 100644 board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg create mode 100644 configs/apalis-imx8qm_defconfig create mode 100644 include/configs/apalis-imx8.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ae62fbcbc2..4418dd30ca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -603,6 +603,7 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += \ + fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi new file mode 100644 index 0000000000..7b1a9550e4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&lpuart2 { + u-boot,dm-spl; +}; + +&lpuart3 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts new file mode 100644 index 0000000000..9b1f8aa32d --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2019 Toradex + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" +#include "fsl-imx8qm-apalis-u-boot.dtsi" + +/ { + model = "Toradex Apalis iMX8QM"; + compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; + stdout-path = &lpuart1; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>, + <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>, + <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>, + <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>, + <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>; + + apalis-imx8qm { + pinctrl_gpio12: gpio12grp { + fsl,pins = < + /* Apalis GPIO1 */ + SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021 + /* Apalis GPIO2 */ + SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021 + >; + }; + + pinctrl_gpio34: gpio34grp { + fsl,pins = < + /* Apalis GPIO3 */ + SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021 + /* Apalis GPIO4 */ + SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021 + >; + }; + + pinctrl_gpio56: gpio56grp { + fsl,pins = < + /* Apalis GPIO5 */ + SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021 + /* Apalis GPIO6 */ + SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021 + >; + }; + + pinctrl_gpio7: gpio7 { + fsl,pins = < + /* Apalis GPIO7 */ + SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 + >; + }; + + pinctrl_gpio8: gpio8 { + fsl,pins = < + /* Apalis GPIO8 */ + SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021 + >; + }; + + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + /* Apalis WAKE1_MICO */ + SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* ETH_RESET# */ + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 + >; + }; + + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + /* Apalis BKL_ON */ + SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021 + >; + }; + + /* Apalis I2C2 (DDC) */ + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022 + >; + }; + + pinctrl_cam1_gpios: cam1gpiosgrp { + fsl,pins = < + /* Apalis CAM1_D7 */ + SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021 + /* Apalis CAM1_D6 */ + SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021 + /* Apalis CAM1_D5 */ + SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021 + /* Apalis CAM1_D4 */ + SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021 + /* Apalis CAM1_D3 */ + SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021 + /* Apalis CAM1_D2 */ + SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021 + /* Apalis CAM1_D1 */ + SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021 + /* Apalis CAM1_D0 */ + SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021 + /* Apalis CAM1_PCLK */ + SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021 + /* Apalis CAM1_MCLK */ + SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021 + /* Apalis CAM1_VSYNC */ + SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021 + /* Apalis CAM1_HSYNC */ + SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021 + >; + }; + + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_MCLK */ + SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021 + /* Apalis DAP1_D_OUT */ + SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021 + /* Apalis DAP1_RESET */ + SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + /* Apalis DAP1_BIT_CLK */ + SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021 + /* Apalis DAP1_D_IN */ + SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021 + /* Apalis DAP1_SYNC */ + SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + /* Wi-Fi_I2S_EN# */ + SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021 + >; + }; + + pinctrl_esai0_gpios: esai0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G1 */ + SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021 + /* Apalis LCD1_G2 */ + SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021 + >; + }; + + pinctrl_fec2_gpios: fec2gpiosgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + /* Apalis LCD1_R1 */ + SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021 + /* Apalis LCD1_R0 */ + SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021 + /* Apalis LCD1_G0 */ + SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021 + /* Apalis LCD1_R7 */ + SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021 + /* Apalis LCD1_DE */ + SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021 + /* Apalis LCD1_HSYNC */ + SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021 + /* Apalis LCD1_VSYNC */ + SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021 + /* Apalis LCD1_PCLK */ + SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021 + /* Apalis LCD1_R6 */ + SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021 + /* Apalis LCD1_R5 */ + SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021 + /* Apalis LCD1_R4 */ + SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021 + /* Apalis LCD1_R3 */ + SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021 + /* Apalis LCD1_R2 */ + SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021 + >; + }; + + pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio { + fsl,pins = < + /* Apalis TS_2 */ + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021 + >; + }; + + pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G6 */ + SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021 + /* Apalis LCD1_G7 */ + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021 + >; + }; + + pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { + fsl,pins = < + /* Apalis TS_4 */ + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021 + >; + }; + + pinctrl_mlb_gpios: mlbgpiosgrp { + fsl,pins = < + /* Apalis TS_1 */ + SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021 + >; + }; + + pinctrl_qspi1a_gpios: qspi1agpiosgrp { + fsl,pins = < + /* Apalis LCD1_B0 */ + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + /* Apalis LCD1_B1 */ + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021 + /* Apalis LCD1_B2 */ + SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021 + /* Apalis LCD1_B3 */ + SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021 + /* Apalis LCD1_B5 */ + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + /* Apalis LCD1_B7 */ + SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021 + /* Apalis LCD1_B4 */ + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021 + /* Apalis LCD1_B6 */ + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021 + >; + }; + + pinctrl_sim0_gpios: sim0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G5 */ + SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 + /* Apalis LCD1_G3 */ + SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021 + /* Apalis TS_5 */ + SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021 + /* Apalis LCD1_G4 */ + SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_usdhc1_gpios: usdhc1gpiosgrp { + fsl,pins = < + /* Apalis TS_6 */ + SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021 + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + /* Apalis TS_3 */ + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020 + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020 + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020 + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020 + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020 + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart1ctrl: lpuart1ctrlgrp { + fsl,pins = < + /* Apalis UART1_DTR */ + SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021 + /* Apalis UART1_DSR */ + SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021 + /* Apalis UART1_DCD */ + SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021 + /* Apalis UART1_RI */ + SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021 + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020 + SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020 + SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020 + SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020 + >; + }; + + /* Apalis PWM3 */ + pinctrl_gpio_pwm0: gpiopwm0grp { + fsl,pins = < + SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 0x00000021 + >; + }; + + /* Apalis PWM4 */ + pinctrl_gpio_pwm1: gpiopwm1grp { + fsl,pins = < + SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 0x00000021 + >; + }; + + /* Apalis PWM1 */ + pinctrl_gpio_pwm2: gpiopwm2grp { + fsl,pins = < + SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 0x00000021 + >; + }; + + /* Apalis PWM2 */ + pinctrl_gpio_pwm3: gpiopwm3grp { + fsl,pins = < + SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 0x00000021 + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_gpio_pwm_bkl: gpiopwmbklgrp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 0x00000021 + >; + }; + + /* Apalis USBH_EN */ + pinctrl_gpio_usbh_en: gpiousbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000060 + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000060 + >; + }; + + /* Apalis USBO1_EN */ + pinctrl_gpio_usbo1_en: gpiousbo1en { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000060 + >; + }; + + /* Apalis USBO1_OC# */ + pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn { + fsl,pins = < + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x06000060 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + /* Apalis SATA1_ACT# */ + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + >; + }; + + pinctrl_mmc1_cd: mmc1cdgrp { + fsl,pins = < + /* Apalis MMC1_CD# */ + SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_sd1_cd: sd1cdgrp { + fsl,pins = < + /* Apalis SD1_CD# */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 11 1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; + }; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* On-module I2C */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + bus-width = <8>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 385000775c..bbe323d5ca 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -27,6 +27,11 @@ choice prompt "i.MX8 board select" optional +config TARGET_APALIS_IMX8 + bool "Support Apalis iMX8 module" + select BOARD_LATE_INIT + select IMX8QM + config TARGET_COLIBRI_IMX8X bool "Support Colibri iMX8X module" select BOARD_LATE_INIT @@ -46,6 +51,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" +source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" endif diff --git a/board/toradex/apalis-imx8/Kconfig b/board/toradex/apalis-imx8/Kconfig new file mode 100644 index 0000000000..c680d63fa1 --- /dev/null +++ b/board/toradex/apalis-imx8/Kconfig @@ -0,0 +1,30 @@ +if TARGET_APALIS_IMX8 + +config SYS_BOARD + default "apalis-imx8" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis-imx8" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS new file mode 100644 index 0000000000..c9ac58b47b --- /dev/null +++ b/board/toradex/apalis-imx8/MAINTAINERS @@ -0,0 +1,9 @@ +Apalis iMX8 +M: Marcel Ziswiler +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8-apalis.dts +F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi +F: board/toradex/apalis-imx8/ +F: configs/apalis-imx8qm_defconfig +F: include/configs/apalis-imx8.h diff --git a/board/toradex/apalis-imx8/Makefile b/board/toradex/apalis-imx8/Makefile new file mode 100644 index 0000000000..a8c3eb7240 --- /dev/null +++ b/board/toradex/apalis-imx8/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Toradex +# + +obj-y += apalis-imx8.o diff --git a/board/toradex/apalis-imx8/README b/board/toradex/apalis-imx8/README new file mode 100644 index 0000000000..e6e3dcb367 --- /dev/null +++ b/board/toradex/apalis-imx8/README @@ -0,0 +1,66 @@ +U-Boot for the Toradex Apalis iMX8QM V1.0B Module + +Quick Start +=========== + +- Build the ARM trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Load U-Boot binary using uuu +- Flash U-Boot binary into the eMMC +- Boot + +Get and Build the ARM Trusted Firmware +====================================== + +$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +======================================= + +$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true +$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Copy the following binaries to the U-Boot folder: + +$ cp imx-atf/build/imx8qm/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmware to the U-Boot folder: + +$ cp firmware-imx-8.0/firmware/seco/ahab-container.img . + +Build U-Boot +============ + +$ make apalis-imx8qm_defconfig +$ make u-boot-dtb.imx + +Load the U-Boot Binary Using UUU +================================ + +Get the latest version of the universal update utility (uuu) aka mfgtools 3.0: + +https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases + +Put the module into USB recovery aka serial downloader mode, connect USB device +to your host and execute uuu: + +sudo ./uuu u-boot/u-boot-dtb.imx + +Flash the U-Boot Binary into the eMMC +===================================== + +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition: + +load mmc 1:1 $loadaddr u-boot-dtb.imx +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 +mmc dev 0 1 +mmc write ${loadaddr} 0x0 ${blkcnt} + +Boot diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c new file mode 100644 index 0000000000..f516e546a8 --- /dev/null +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Toradex + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart1_pads[] = { + SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate; + sc_err_t err = 0; + + /* Power up UART1 */ + err = sc_pm_set_resource_power_mode(-1, SC_R_UART_1, SC_PM_PW_MODE_ON); + if (err != SC_ERR_NONE) + return 0; + + /* Set UART3 clock root to 80 MHz */ + rate = 80000000; + err = sc_pm_set_clock_rate(-1, SC_R_UART_1, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + return 0; + + /* Enable UART1 clock root */ + err = sc_pm_clock_enable(-1, SC_R_UART_1, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 if build info not supported */ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Model: Toradex Apalis iMX8\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */ + env_set("board_name", "Apalis iMX8QM"); + env_set("board_rev", "v1.0"); +#endif + + return 0; +} diff --git a/board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg b/board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg new file mode 100644 index 0000000000..71981f8c55 --- /dev/null +++ b/board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-apalis-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig new file mode 100644 index 0000000000..f3dbaf0101 --- /dev/null +++ b/configs/apalis-imx8qm_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_APALIS_IMX8=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg" +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_CPU=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h new file mode 100644 index 0000000000..be2c5a2293 --- /dev/null +++ b/include/configs/apalis-imx8.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + */ + +#ifndef __APALIS_IMX8_H +#define __APALIS_IMX8_H + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Networking */ +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE SZ_4K +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x84000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x94400000\0" \ + "scriptaddr=0x87000000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "console=ttyLP1 earlycon\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ + "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x89000000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ +#define CONFIG_SYS_MMC_ENV_PART 1 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#endif /* __APALIS_IMX8_H */