From patchwork Fri May 31 05:01:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 1108036 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="IIUV+IDv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45FXMn3GHTz9sDX for ; Fri, 31 May 2019 15:00:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726403AbfEaFAw (ORCPT ); Fri, 31 May 2019 01:00:52 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16233 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbfEaFAv (ORCPT ); Fri, 31 May 2019 01:00:51 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 30 May 2019 22:00:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 30 May 2019 22:00:50 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 30 May 2019 22:00:50 -0700 Received: from localhost.nvidia.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 31 May 2019 05:00:48 +0000 From: Abhishek Sahu To: Bjorn Helgaas CC: , , Abhishek Sahu Subject: [PATCH 1/2] PCI: Code reorganization for VGA device link Date: Fri, 31 May 2019 10:31:08 +0530 Message-ID: <20190531050109.16211-2-abhsahu@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190531050109.16211-1-abhsahu@nvidia.com> References: <20190531050109.16211-1-abhsahu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL106.nvidia.com (172.18.146.12) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559278840; bh=KOYlF9zE1nAd15bslH2RS9I7HwZ+Rr/vibg1nSmt3Rs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: X-Originating-IP:X-ClientProxiedBy:Content-Type; b=IIUV+IDvaITEXNAfgo8DOsmQ3d2Z5WMqm7I7RUMtjjsqw6pFAqQLhivqTh+2NUbar r+QOHqefH8zss2sqJC96L/mzFiXI2tGcacwufDxyYv/wEGQDTPHsgfyPUdr92wmDa0 OHIdfuX1dTM4UupHyIWaSIC0Q824vlcVU2SVbdnRoRI0QTy/3wXctiJS2FJ0D/DE9M rsz3RomLQVIxs2UY75fluC7r9svazexhh3USPq+0gtaPVQa4mr1p0+O8M94qDyNiDl 77aZgTwtgMmLSHZ+Boh9zuy093Te6QXx8cdOupH3omDWVCdjMgMhF7RD1bIxuKh6rw jTnlVAnFlOw7g== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch does minor code reorganization. It introduces a helper function which creates device link from the non-VGA controller (consumer) to the VGA (supplier) and uses this helper function for creating device link from integrated HDA controller to VGA. It will help in subsequent patches which require a similar kind of device link from USB/Type-C USCI controller to VGA. Signed-off-by: Abhishek Sahu --- drivers/pci/quirks.c | 44 +++++++++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a077f67fe1da..a20f7771a323 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4916,36 +4916,50 @@ static void quirk_fsl_no_msi(struct pci_dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); /* - * GPUs with integrated HDA controller for streaming audio to attached displays - * need a device link from the HDA controller (consumer) to the GPU (supplier) - * so that the GPU is powered up whenever the HDA controller is accessed. - * The GPU and HDA controller are functions 0 and 1 of the same PCI device. - * The device link stays in place until shutdown (or removal of the PCI device - * if it's hotplugged). Runtime PM is allowed by default on the HDA controller - * to prevent it from permanently keeping the GPU awake. + * GPUs can be multi-function PCI device which can contain controllers other + * than VGA (like Audio, USB, etc.). Internally in the hardware, these non-VGA + * controllers are tightly coupled with VGA controller. Whenever these + * controllers are runtime active, the VGA controller should also be in active + * state. Normally, in these GPUs, the VGA controller is present at function 0. + * + * This is a helper function which creates device link from the non-VGA + * controller (consumer) to the VGA (supplier). The device link stays in place + * until shutdown (or removal of the PCI device if it's hotplugged). + * Runtime PM is allowed by default on these non-VGA controllers to prevent + * it from permanently keeping the GPU awake. */ -static void quirk_gpu_hda(struct pci_dev *hda) +static void +pci_create_device_link_with_vga(struct pci_dev *pdev, unsigned int devfn) { struct pci_dev *gpu; - if (PCI_FUNC(hda->devfn) != 1) + if (PCI_FUNC(pdev->devfn) != devfn) return; - gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), - hda->bus->number, - PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); + gpu = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), + pdev->bus->number, + PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { pci_dev_put(gpu); return; } - if (!device_link_add(&hda->dev, &gpu->dev, + if (!device_link_add(&pdev->dev, &gpu->dev, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) - pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); + pci_err(pdev, "cannot link with VGA %s\n", pci_name(gpu)); - pm_runtime_allow(&hda->dev); + pm_runtime_allow(&pdev->dev); pci_dev_put(gpu); } + +/* + * Create device link for GPUs with integrated HDA controller for streaming + * audio to attached displays. + */ +static void quirk_gpu_hda(struct pci_dev *hda) +{ + pci_create_device_link_with_vga(hda, 1); +} DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, From patchwork Fri May 31 05:01:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 1108037 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="IJ77GkHS"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45FXMw5W8dz9sN6 for ; Fri, 31 May 2019 15:01:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725955AbfEaFAz (ORCPT ); Fri, 31 May 2019 01:00:55 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8866 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726617AbfEaFAx (ORCPT ); Fri, 31 May 2019 01:00:53 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 30 May 2019 22:00:51 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 30 May 2019 22:00:52 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 30 May 2019 22:00:52 -0700 Received: from localhost.nvidia.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 31 May 2019 05:00:50 +0000 From: Abhishek Sahu To: Bjorn Helgaas CC: , , Abhishek Sahu Subject: [PATCH 2/2] PCI: Create device link for NVIDIA GPU Date: Fri, 31 May 2019 10:31:09 +0530 Message-ID: <20190531050109.16211-3-abhsahu@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190531050109.16211-1-abhsahu@nvidia.com> References: <20190531050109.16211-1-abhsahu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL106.nvidia.com (172.18.146.12) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559278852; bh=X9Kjg+2IaxMtapTnBZhXu4pRG7RuEQMor0d4RRehUic=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: X-Originating-IP:X-ClientProxiedBy:Content-Type; b=IJ77GkHSy4VdQXAZeFLwUarWDrzuu1tdnTUw/Ji9VMVhm8qclmOjJUjZmi9H50s8K HbGanXpJdCP/33gIfJvNmBMgBFlBkpJgMStV1TdVzZrtePScJfeYTOg45BzaBZPjk9 eRLCpfVtfgDH3xBD6D1TXVcoo4xRWDmmtdDjd6+fy8Dk7NwfcuOPgShOKh1SxLwAi+ 1GrG9MHmngXdqnfmYA/FxLmK2WjLKHVa7hLrY4dHZQOFZiIpBegA+mZ/PcgipB7GZz CzlG5mcwFuNWFDwhmS6YBzaJRbdjcrrrpKKmrL89e9Wsy8UbaZSYCurFYPjun6cwAe 5hBiYoVeKGYHg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org NVIDIA Turing GPUs include hardware support for USB Type-C and VirtualLink. It helps in delivering the power, display, and data required to power VR headsets through a single USB Type-C connector. The Turing GPU is a multi-function PCI device has the following four functions: - VGA display controller (Function 0) - Audio controller (Function 1) - USB xHCI Host controller (Function 2) - USB Type-C USCI controller (Function 3) The function 0 is tightly coupled with other functions in the hardware. When function 0 goes in runtime suspended state, then it will do power gating for most of the hardware blocks. Some of these hardware blocks are used by other functions which leads to functional failure. So if any of these functions (1/2/3) are active, then function 0 should also be in active state. 'commit 07f4f97d7b4b ("vga_switcheroo: Use device link for HDA controller")' creates the device link from function 1 to function 0. A similar kind of device link needs to be created between function 0 and functions 2 and 3 for NVIDIA Turing GPU. This patch does the same and create the required device links. It will make function 0 to be runtime PM active if other functions are still active. Signed-off-by: Abhishek Sahu --- drivers/pci/quirks.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a20f7771a323..afdbc199efc5 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4967,6 +4967,29 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); +/* Create device link for NVIDIA GPU with integrated USB controller to VGA. */ +static void quirk_gpu_usb(struct pci_dev *usb) +{ + pci_create_device_link_with_vga(usb, 2); +} +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); + +/* + * Create device link for NVIDIA GPU with integrated Type-C UCSI controller + * to VGA. Currently there is no class code defined for UCSI device over PCI + * so using UNKNOWN class for now and it will be updated when UCSI + * over PCI gets a class code. + */ +#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 +static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) +{ + pci_create_device_link_with_vga(ucsi, 3); +} +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + PCI_CLASS_SERIAL_UNKNOWN, 8, + quirk_gpu_usb_typec_ucsi); + /* * Some IDT switches incorrectly flag an ACS Source Validation error on * completions for config read requests even though PCIe r4.0, sec