From patchwork Fri May 24 02:29:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1104577 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4599Mx0dBfz9s1c for ; Fri, 24 May 2019 12:30:52 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 81055C21E88; Fri, 24 May 2019 02:30:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 16030C21E70; Fri, 24 May 2019 02:30:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B962FC21EC8; Fri, 24 May 2019 02:30:15 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lists.denx.de (Postfix) with ESMTPS id 25359C21C93 for ; Fri, 24 May 2019 02:30:10 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2019 19:30:09 -0700 X-ExtLoop1: 1 Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.59]) by orsmga002.jf.intel.com with SMTP; 23 May 2019 19:30:06 -0700 Received: by ubuntu (sSMTP sendmail emulation); Fri, 24 May 2019 10:30:05 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Date: Fri, 24 May 2019 10:29:58 +0800 Message-Id: <1558665000-3037-2-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558665000-3037-1-git-send-email-ley.foon.tan@intel.com> References: <1558665000-3037-1-git-send-email-ley.foon.tan@intel.com> Cc: Tom Rini , Chin Liang See Subject: [U-Boot] [PATCH 1/3] pci: intel: Increase TLP polling counter X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some PCIe devices require longer time to response. Increase polling counter to 20000 (~100ms). Signed-off-by: Ley Foon Tan --- drivers/pci/pcie_intel_fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 3cdf05b314..e74b35ac16 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -56,7 +56,7 @@ #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) #define TLP_HDR_SIZE 3 -#define TLP_LOOP 500 +#define TLP_LOOP 20000 #define DWORD_MASK 3 #define IS_ROOT_PORT(pcie, bdf) \ From patchwork Fri May 24 02:29:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1104579 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4599Nf5cX5z9s1c for ; Fri, 24 May 2019 12:31:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6D7B6C21EA6; Fri, 24 May 2019 02:30:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8342CC21EEF; Fri, 24 May 2019 02:30:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3D9F8C21EEF; Fri, 24 May 2019 02:30:18 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lists.denx.de (Postfix) with ESMTPS id C1A61C21E88 for ; Fri, 24 May 2019 02:30:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2019 19:30:13 -0700 X-ExtLoop1: 1 Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.59]) by orsmga006.jf.intel.com with SMTP; 23 May 2019 19:30:09 -0700 Received: by ubuntu (sSMTP sendmail emulation); Fri, 24 May 2019 10:30:08 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Date: Fri, 24 May 2019 10:29:59 +0800 Message-Id: <1558665000-3037-3-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558665000-3037-1-git-send-email-ley.foon.tan@intel.com> References: <1558665000-3037-1-git-send-email-ley.foon.tan@intel.com> Cc: Tom Rini , Chin Liang See Subject: [U-Boot] [PATCH 2/3] pci: intel: Fix error when enumerating multi-function PCIe device X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hardware return completion status non-zero when read from non exist function in multi-function PCIe device. Return error will cause PCIe enumeration fail. Change it to return 0 and return value 0xffffffff when error. Signed-off-by: Ley Foon Tan --- drivers/pci/pcie_intel_fpga.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index e74b35ac16..a096d1c697 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -161,8 +161,10 @@ static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value) dw[count++] = cra_readl(pcie, RP_RXCPL_REG); if (ctrl & RP_RXCPL_EOP) { comp_status = TLP_COMP_STATUS(dw[1]); - if (comp_status) - return -EFAULT; + if (comp_status) { + *value = pci_get_ff(PCI_SIZE_32); + return 0; + } if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) && From patchwork Fri May 24 02:30:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1104578 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4599NX44Vvz9s1c for ; Fri, 24 May 2019 12:31:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 43A62C21EB4; Fri, 24 May 2019 02:30:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 18E6FC21ECA; Fri, 24 May 2019 02:30:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B31C7C21DAF; Fri, 24 May 2019 02:30:22 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lists.denx.de (Postfix) with ESMTPS id 91CA5C21EC8 for ; Fri, 24 May 2019 02:30:18 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2019 19:30:16 -0700 X-ExtLoop1: 1 Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.59]) by orsmga008.jf.intel.com with SMTP; 23 May 2019 19:30:14 -0700 Received: by ubuntu (sSMTP sendmail emulation); Fri, 24 May 2019 10:30:12 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Date: Fri, 24 May 2019 10:30:00 +0800 Message-Id: <1558665000-3037-4-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558665000-3037-1-git-send-email-ley.foon.tan@intel.com> References: <1558665000-3037-1-git-send-email-ley.foon.tan@intel.com> Cc: Tom Rini , Chin Liang See Subject: [U-Boot] [PATCH 3/3] pci: intel: Fix configuration type based on secondary number X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This fix issue when access config from PCIe switch. The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link. The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link. Signed-off-by: Ley Foon Tan --- drivers/pci/pcie_intel_fpga.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index a096d1c697..a5ea4888f3 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -36,16 +36,18 @@ #define RP_CFG_ADDR(pcie, reg) \ ((pcie->hip_base) + (reg) + (1 << 20)) +#define RP_SECONDARY(pcie) \ + readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) #define TLP_CFGRD_DW0(pcie, bus) \ - ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \ - : TLP_FMTTYPE_CFGRD1) << 24) | \ + ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \ + : TLP_FMTTYPE_CFGRD0) << 24) | \ TLP_PAYLOAD_SIZE) #define TLP_CFGWR_DW0(pcie, bus) \ - ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \ - : TLP_FMTTYPE_CFGWR1) << 24) | \ + ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \ + : TLP_FMTTYPE_CFGWR0) << 24) | \ TLP_PAYLOAD_SIZE) #define TLP_CFG_DW1(pcie, tag, be) \