From patchwork Tue May 21 16:26:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102921 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501367-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="FQhnL76c"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h4X0Dr8z9s55 for ; Wed, 22 May 2019 02:27:23 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=Yam/7tXgwdPgZEXRngJ QnDWwmlpVE4E0BfwvB6Xie+IMb3xLnIX18+mdV7OyTXmHzZ7F6xpmb4D0tHulDwP 5KnYwscg5yoMqnbq5ZnudJLLo6/wDTfBrhH+j6oFc6oF0i2i48MmzTC8npnJZyDe c58IPotVTYlO97a1mhVwu9DA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=88t2PW35OEsaSAjxOpaLagCSu nc=; b=FQhnL76cnq7EIvUcNmFXO+9ACH6rbiTrvkWpqNLPWs9hjobwHncaV0XV2 oNxGt9dhBuZuIqeicspxEn1VVazvcIL+1TyDLRpTB6Y/E1BldvUwIS8K69QtnzHw vvAfvVmKEt2mtSVXJCxEHW/l6mGdgwfsAzi5XQKaHxSkMgLH9M= Received: (qmail 79979 invoked by alias); 21 May 2019 16:27:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 79932 invoked by uid 89); 21 May 2019 16:27:11 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=doubles, 77408 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:09 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 9A3DD1240630; Tue, 21 May 2019 16:27:06 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 1/6] rs6000: wh -> d+p8v Date: Tue, 21 May 2019 16:26:55 +0000 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes This replaces the "wh" constraint by "d", with isa "p8v". 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wh"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wh. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wh" constraint by "wa" with "p8v". * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 4 ---- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 20 ++++++++++++-------- gcc/doc/md.texi | 5 +---- 5 files changed, 13 insertions(+), 20 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index dbcf08c..c9f168f 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -71,9 +71,6 @@ (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" "If -mmfpgpr was used, a floating point register or NO_REGS.") -(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" - "Floating point register if direct moves are available, or NO_REGS.") - (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b5dc5f3..a95848a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2512,7 +2512,6 @@ rs6000_debug_reg_global (void) "we reg_class = %s\n" "wf reg_class = %s\n" "wg reg_class = %s\n" - "wh reg_class = %s\n" "wi reg_class = %s\n" "wj reg_class = %s\n" "wk reg_class = %s\n" @@ -2537,7 +2536,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], @@ -3163,7 +3161,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wd - Preferred register class for V2DFmode. wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. - wh - FP register for direct move instructions. wi - FP or VSX register to hold 64-bit integers for VSX insns. wj - FP or VSX register to hold 64-bit integers for direct moves. wk - FP or VSX register to hold 64-bit doubles for direct moves. @@ -3208,7 +3205,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_DIRECT_MOVE) { - rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS; rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */ = rs6000_constraints[RS6000_CONSTRAINT_wi]; rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index eaf309b..ca30639 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1253,7 +1253,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ - RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b2bba5d..398398c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -471,7 +471,7 @@ (define_mode_attr zero_fp [(SF "j") (define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) ; Definitions for 64-bit direct move -(define_mode_attr f64_dm [(DF "wk") (DD "wh")]) +(define_mode_attr f64_dm [(DF "wk") (DD "d")]) ; Definitions for 64-bit use of altivec registers (define_mode_attr f64_av [(DF "wv") (DD "wn")]) @@ -7349,10 +7349,10 @@ (define_insn "movsf_hardfloat" ;; FMR MR MT%0 MF%1 NOP (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" - "=!r, wz, m, Z, ?wh, ?r, + "=!r, wz, m, Z, ?d, ?r, f, !r, *c*l, !r, *h") (match_operand:SD 1 "input_operand" - "m, Z, r, wx, r, wh, + "m, Z, r, wx, r, d, f, r, r, *h, 0"))] "(register_operand (operands[0], SDmode) || register_operand (operands[1], SDmode)) @@ -7371,7 +7371,10 @@ (define_insn "movsd_hardfloat" nop" [(set_attr "type" "load, fpload, store, fpstore, mffgpr, mftgpr, - fpsimple, *, mtjmpr, mfjmpr, *")]) + fpsimple, *, mtjmpr, mfjmpr, *") + (set_attr "isa" + "*, *, *, *, p8v, p8v, + *, *, *, *, *")]) ;; MR MT%0 MF%0 LWZ STW LI ;; LIS G-const. F/n-const NOP @@ -7684,7 +7687,7 @@ (define_insn "*mov_hardfloat64" "*, *, *, p9v, p9v, *, *, *, *, *, *, *, *, *, *, - *, *, *, *, *")]) + *, *, *, p8v, p8v")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -7737,8 +7740,8 @@ (define_expand "mov" ;; problematical. Don't allow direct move for this case. (define_insn_and_split "*mov_64bit_dm" - [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh") - (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,,r,Y,r,wh,r"))] + [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,d") + (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,,r,Y,r,d,r"))] "TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (mode) && (mode != TDmode || WORDS_BIG_ENDIAN) && (gpc_reg_operand (operands[0], mode) @@ -7747,7 +7750,8 @@ (define_insn_and_split "*mov_64bit_dm" "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,8,12,12,8,8,8")]) + [(set_attr "length" "8,8,8,8,12,12,8,8,8") + (set_attr "isa" "*,*,*,*,*,*,*,p8v,p8v")]) (define_insn_and_split "*movtd_64bit_nodm" [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 6c7d121..daf0195 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3197,7 +3197,7 @@ Altivec vector register Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, -@code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk}, +@code{wf}, @code{wg}, @code{wi}, @code{wj}, @code{wk}, @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so @@ -3259,9 +3259,6 @@ VSX vector register to hold vector float data or NO_REGS. @item wg If @option{-mmfpgpr} was used, a floating point register or NO_REGS. -@item wh -Floating point register if direct moves are available, or NO_REGS. - @item wi FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. From patchwork Tue May 21 16:26:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501368-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="S4enL3Pf"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h4m2cKyz9s7h for ; Wed, 22 May 2019 02:27:36 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=XwzPYG5rr8pQJ3hPP/F 7IGd25+7FGHwIK+DJAavJq6sGQCTLYejAsE6sbGbskl9fhLryKgUHDgjuXjH0yad xVsNBcez6t2pqsnG8aXeGYeGbxf3UPhHebAeRHCqthQ68CHveWQe/FvWOvq18bfB LYoJte0Li0ndTb8u7+aFVQ1k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=dbQ2uUFUKiGFq1maZnFiEaILL WA=; b=S4enL3PfJVwv250W75QIBfCVzRKXO7ZZQs99atdu4hCvGez0TiOPmUUrG Mu1vM+S4KJb3TShjWUH1K5uKQycFO0Zu0cURnXwrt1hF+BtE3SXNacrTfen8lXNZ gZz6C0W1BwlxhYqiI3xo4VOXZeKGZ8FBLeXFJ+eGQZmphkK0nY= Received: (qmail 80630 invoked by alias); 21 May 2019 16:27:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 80591 invoked by uid 89); 21 May 2019 16:27:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=wir, wv X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:13 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 445451240630; Tue, 21 May 2019 16:27:12 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 2/6] rs6000: wj -> wi+p8v Date: Tue, 21 May 2019 16:26:56 +0000 Message-Id: <048e68a481b4ec13d9f74a7a4d67988637e75aa8.1558453009.git.segher@kernel.crashing.org> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes Also deletes VS_64dm, it's unused. 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wj"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wj. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wj" constraint by "wi" with "p8v". (VS_64dm): Delete. * config/rs6000/vsx.md: Ditto. * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 5 ----- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 22 +++++++++++----------- gcc/config/rs6000/vsx.md | 10 +++------- gcc/doc/md.texi | 5 +---- 6 files changed, 15 insertions(+), 31 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c9f168f..9f315e4 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -74,9 +74,6 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") -(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" - "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") - (define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a95848a..76c80a4 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void) "wf reg_class = %s\n" "wg reg_class = %s\n" "wi reg_class = %s\n" - "wj reg_class = %s\n" "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" @@ -2537,7 +2536,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], @@ -3162,7 +3160,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. wi - FP or VSX register to hold 64-bit integers for VSX insns. - wj - FP or VSX register to hold 64-bit integers for direct moves. wk - FP or VSX register to hold 64-bit doubles for direct moves. wl - Float register if we can do 32-bit signed int loads. wm - VSX register for ISA 2.07 direct move operations. @@ -3205,8 +3202,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_DIRECT_MOVE) { - rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */ - = rs6000_constraints[RS6000_CONSTRAINT_wi]; rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ = rs6000_constraints[RS6000_CONSTRAINT_ws]; rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index ca30639..218ed10 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ - RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 398398c..9a986a1 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -834,7 +834,7 @@ (define_insn_and_split "*zero_extendhi2_dot2" (define_insn "zero_extendsi2" - [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wj,r,wa") + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wi,r,wa") (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))] "" "@ @@ -846,7 +846,7 @@ (define_insn "zero_extendsi2" mfvsrwz %0,%x1 xxextractuw %x0,%x1,4" [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts") - (set_attr "isa" "*,*,*,p8v,*,p8v,p9v")]) + (set_attr "isa" "*,*,*,p8v,p8v,p8v,p9v")]) (define_insn_and_split "*zero_extendsi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -1019,7 +1019,7 @@ (define_insn_and_split "*extendhi2_dot2" (define_insn "extendsi2" [(set (match_operand:EXTSI 0 "gpc_reg_operand" - "=r, r, wl, wa, wj, v, v, wr") + "=r, r, wl, wa, wi, v, v, wr") (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "YZ, r, Z, Z, r, v, v, ?wa")))] "" @@ -1035,7 +1035,7 @@ (define_insn "extendsi2" [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr") (set_attr "sign_extend" "yes") (set_attr "length" "4,4,4,4,4,4,8,8") - (set_attr "isa" "*,*,*,p8v,*,p9v,p8v,p8v")]) + (set_attr "isa" "*,*,*,p8v,p8v,p9v,p8v,p8v")]) (define_split [(set (match_operand:EXTSI 0 "int_reg_operand") @@ -5233,7 +5233,7 @@ (define_insn "*xxsel" ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,v") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,v") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,v")] UNSPEC_LFIWAX))] "TARGET_HARD_FLOAT && TARGET_LFIWAX" @@ -5243,7 +5243,7 @@ (define_insn "lfiwax" mtvsrwa %x0,%1 vextsw2d %0,%1" [(set_attr "type" "fpload,fpload,mffgpr,vecexts") - (set_attr "isa" "*,*,*,p9v")]) + (set_attr "isa" "*,p8v,p8v,p9v")]) ; This split must be run before register allocation because it allocates the ; memory slot that is needed to move values to/from the FPR. We don't allocate @@ -5315,7 +5315,7 @@ (define_insn_and_split "floatsi2_lfiwax_mem" (set_attr "type" "fpload")]) (define_insn "lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wa") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,wa") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")] UNSPEC_LFIWZX))] "TARGET_HARD_FLOAT && TARGET_LFIWZX" @@ -5325,7 +5325,7 @@ (define_insn "lfiwzx" mtvsrwz %x0,%1 xxextractuw %x0,%x1,4" [(set_attr "type" "fpload,fpload,mftgpr,vecexts") - (set_attr "isa" "*,*,*,p9v")]) + (set_attr "isa" "*,p8v,p8v,p9v")]) (define_insn_and_split "floatunssi2_lfiwzx" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") @@ -8831,13 +8831,13 @@ (define_insn "*movdi_internal64" m, ^d, ^d, wY, Z, $v, $wv, ^wi, wa, wa, wv, wi, wi, wv, wv, r, *h, *h, - ?r, ?wg, ?r, ?wj") + ?r, ?wg, ?r, ?wi") (match_operand:DI 1 "input_operand" "r, YZ, r, I, L, nF, ^d, m, ^d, ^v, $wv, wY, Z, ^wi, Oj, wM, OjwM, Oj, wM, wS, wB, *h, r, 0, - wg, r, wj, r"))] + wg, r, wi, r"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -8888,7 +8888,7 @@ (define_insn "*movdi_internal64" *, *, *, p9v, *, p9v, *, *, p9v, p9v, *, *, *, *, *, *, *, *, - *, *, *, *")]) + *, *, p8v, p8v")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ae757f1..ff4ceb6 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -275,11 +275,6 @@ (define_mode_attr VS_double [(V4SI "V8SI") (V2DF "V4DF") (V1TI "V2TI")]) -;; Map register class for 64-bit element in 128-bit vector for direct moves -;; to/from gprs -(define_mode_attr VS_64dm [(V2DF "wk") - (V2DI "wj")]) - ;; Map register class for 64-bit element in 128-bit vector for normal register ;; to register moves (define_mode_attr VS_64reg [(V2DF "ws") @@ -4158,12 +4153,13 @@ (define_insn "vsx_splat_v4si_di" [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we") (vec_duplicate:V4SI (truncate:SI - (match_operand:DI 1 "gpc_reg_operand" "wj,r"))))] + (match_operand:DI 1 "gpc_reg_operand" "wi,r"))))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" "@ xxspltw %x0,%x1,1 mtvsrws %x0,%1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "p8v,*")]) ;; V4SF splat (ISA 3.0) (define_insn_and_split "vsx_splat_v4sf" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index daf0195..55de2f1 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3197,7 +3197,7 @@ Altivec vector register Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, -@code{wf}, @code{wg}, @code{wi}, @code{wj}, @code{wk}, +@code{wf}, @code{wg}, @code{wi}, @code{wk}, @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so @@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS. @item wi FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. -@item wj -FP or VSX register to hold 64-bit integers for direct moves or NO_REGS. - @item wk FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS. From patchwork Tue May 21 16:26:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102923 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501369-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="TBkTDPOu"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h4z6q7Tz9s7h for ; Wed, 22 May 2019 02:27:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=vvooNGQkcc0XgNqtCYZ PML1cVk6JoXzGEmJ19yMyI5KLZyry5P0BjNfJBeZZuh55LcsgzbaSqEsqK7xeMLm XnB70FiEqqMACDGG06/cJDRfM4pH2OhpqCGKafwUYzPvpdQFEcqBwbl52VMH3kT/ eFwf8qd0+yS8JxIEUUx8lgzo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=Nj6d+3m9lDiHTT1fl1zkLNQnQ S4=; b=TBkTDPOu0ySqJwk2x5/AzFo/n7/Dxo2xEM6bLNvyzTzlAF7ewq4Cb59VR /aKLB4qOt+Dfkyi2NR0aroqOVmYbcSXnYcaxxdhf9OpHpIY44e3IZcIYJzDfFcLw r0Gq7Yy5dzCs1g15P9m22vvbBSh3c8LscWw/pIjIpxEHlFKadc= Received: (qmail 81127 invoked by alias); 21 May 2019 16:27:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81076 invoked by uid 89); 21 May 2019 16:27:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:18 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 033DE1240630; Tue, 21 May 2019 16:27:16 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 3/6] rs6000: wk -> ws+p8v Date: Tue, 21 May 2019 16:26:57 +0000 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wk"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wk. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wk" constraint by "ws" with "p8v". * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 9 +-------- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 2 +- gcc/doc/md.texi | 5 +---- 5 files changed, 3 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 9f315e4..6f60627 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -74,9 +74,6 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") -(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" - "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") - (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 76c80a4..718535f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void) "wf reg_class = %s\n" "wg reg_class = %s\n" "wi reg_class = %s\n" - "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" "wp reg_class = %s\n" @@ -2536,7 +2535,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], @@ -3160,7 +3158,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. wi - FP or VSX register to hold 64-bit integers for VSX insns. - wk - FP or VSX register to hold 64-bit doubles for direct moves. wl - Float register if we can do 32-bit signed int loads. wm - VSX register for ISA 2.07 direct move operations. wn - always NO_REGS. @@ -3201,11 +3198,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ if (TARGET_DIRECT_MOVE) - { - rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ - = rs6000_constraints[RS6000_CONSTRAINT_ws]; - rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; - } + rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; if (TARGET_POWERPC64) { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 218ed10..cc60559 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ - RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9a986a1..33a6de7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -471,7 +471,7 @@ (define_mode_attr zero_fp [(SF "j") (define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) ; Definitions for 64-bit direct move -(define_mode_attr f64_dm [(DF "wk") (DD "d")]) +(define_mode_attr f64_dm [(DF "ws") (DD "d")]) ; Definitions for 64-bit use of altivec registers (define_mode_attr f64_av [(DF "wv") (DD "wn")]) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 55de2f1..13a621d 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3197,7 +3197,7 @@ Altivec vector register Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, -@code{wf}, @code{wg}, @code{wi}, @code{wk}, +@code{wf}, @code{wg}, @code{wi}, @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so @@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS. @item wi FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. -@item wk -FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS. - @item wl Floating point register if the LFIWAX instruction is enabled or NO_REGS. From patchwork Tue May 21 16:26:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501370-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Eyng2+YF"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h5C163Nz9s55 for ; Wed, 22 May 2019 02:27:58 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=F+0CAW/IywRcbCekMe1 TmcP77wW3G7lKNsQ05XGSVyTqUIReFUXtgFEiGXnBtewTuEhPfKxwvRPtjVTYVDr saOlWJa+KuNf3vOpR3+gNkO8edQ78tvxS/3ZJj2BdR/ArolDwaID0lc2kG5gh428 Er6QiE+t3Fl4QkKQN1yju7Yo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=SmTf6jhnUP0054cyD5TMBu/DZ m8=; b=Eyng2+YFJ7JN5sN9ZYn7Q4OjbfYpSuOe3LcUuKSZO4Zcyu6ewa5ZVwpjG BXi2EqItXinUqd2bjE/wAIlkkhJHzFI6fh6ef6tdXi1+iDrWWGKcwjVymnjxfxm2 S0InnkVGMUHlvb03UJi55IG6wjqiB2u9rliPr1QsHNyV2S7RM8= Received: (qmail 81749 invoked by alias); 21 May 2019 16:27:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81667 invoked by uid 89); 21 May 2019 16:27:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=extracting X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:22 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 96A891240630; Tue, 21 May 2019 16:27:21 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 4/6] rs6000: wm -> wa+p8v Date: Tue, 21 May 2019 16:26:58 +0000 Message-Id: <9adc94b9961a063c1820ca493cd96be5d666848c.1558453009.git.segher@kernel.crashing.org> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wm"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wm. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/vsx.md: Replace "wm" constraint by "wa" with "p8v". * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 5 +---- gcc/config/rs6000/rs6000.c | 6 ------ gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/vsx.md | 6 ++---- gcc/doc/md.texi | 5 +---- 5 files changed, 4 insertions(+), 19 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 6f60627..90a94c1 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -77,12 +77,9 @@ (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") -(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" - "VSX register if direct move instructions are enabled, or NO_REGS.") - ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use ;; direct move directly, and movsf can't to move between the register sets. -;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode +;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") (define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]" diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 718535f..d6ffc36 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2514,7 +2514,6 @@ rs6000_debug_reg_global (void) "wg reg_class = %s\n" "wi reg_class = %s\n" "wl reg_class = %s\n" - "wm reg_class = %s\n" "wp reg_class = %s\n" "wq reg_class = %s\n" "wr reg_class = %s\n" @@ -2536,7 +2535,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], @@ -3159,7 +3157,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wg - Float register for power6x move insns. wi - FP or VSX register to hold 64-bit integers for VSX insns. wl - Float register if we can do 32-bit signed int loads. - wm - VSX register for ISA 2.07 direct move operations. wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. ws - Register class to do ISA 2.06 DF operations. @@ -3197,9 +3194,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_LFIWAX) rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ - if (TARGET_DIRECT_MOVE) - rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; - if (TARGET_POWERPC64) { rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index cc60559..27055a6 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1255,7 +1255,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ - RS6000_CONSTRAINT_wm, /* VSX register for direct move */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ff4ceb6..6108451 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3198,10 +3198,8 @@ (define_expand "vsx_set_" (define_insn "vsx_extract_" [(set (match_operand: 0 "gpc_reg_operand" "=d, d, wr, wr") - (vec_select: - (match_operand:VSX_D 1 "gpc_reg_operand" ", , wm, wa") - + (match_operand:VSX_D 1 "gpc_reg_operand" ", , wa, wa") (parallel [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] "VECTOR_MEM_VSX_P (mode)" @@ -3250,7 +3248,7 @@ (define_insn "vsx_extract_" gcc_unreachable (); } [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm") - (set_attr "isa" "*,*,*,p9v")]) + (set_attr "isa" "*,*,p8v,p9v")]) ;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract___load" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 13a621d..7ec1740 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3198,7 +3198,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, @code{wf}, @code{wg}, @code{wi}, -@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, +@code{wl}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so that the correct register is used. Otherwise the register number @@ -3265,9 +3265,6 @@ FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. @item wl Floating point register if the LFIWAX instruction is enabled or NO_REGS. -@item wm -VSX register if direct move instructions are enabled, or NO_REGS. - @item wn No register (NO_REGS). From patchwork Tue May 21 16:26:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102925 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501371-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="bZzcmKvw"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h5Q4Lccz9s7h for ; Wed, 22 May 2019 02:28:10 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=SqpU+oP6TJSeHmkQBr1 DzkFEFd+bEuFFoBmHTdg+O6HpOnij7C/BXcQnCA70CNPRhg0MaU1dc9TDa8WhJ0P TTXLN9z6phF3R9f3hXnvjM6/2ULG4MiAJqJohE5ZMZy+UZZy47Gq9KHa6aPLItnA 2TySJx5BbuQrwjrwKunhUfGc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=u0P0ugmGMkF/xxVl57187JPgn js=; b=bZzcmKvw00WFf3NjCnO8IQpdxZ5fYVkanyWJPpCyaMUtco4ETRYR7J8Ru Cu0Ik88j2WQlbu9B/RExxW1FxdtDtR/vfVy8NVfgeAhPtU1YREvxp3sk3cTYQ1Y7 X05ba8noZ+MtSjb7r4OCKtvyYNsqorIVuHqDrRVq/+V3oLTa3g= Received: (qmail 82192 invoked by alias); 21 May 2019 16:27:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 82131 invoked by uid 89); 21 May 2019 16:27:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT autolearn=ham version=3.3.1 spammy=HX-Languages-Length:5389 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:26 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 246481240630; Tue, 21 May 2019 16:27:25 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 5/6] rs6000: wl -> d+p6 Date: Tue, 21 May 2019 16:26:59 +0000 Message-Id: <5b36315d596a0d0e77c6b904a7ade4125fc92695.1558453009.git.segher@kernel.crashing.org> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wl"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wl. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wl" constraint by "d" with "p6". * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 6 ------ gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 4 ++-- gcc/doc/md.texi | 5 +---- 5 files changed, 3 insertions(+), 16 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 90a94c1..802ce44 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -74,9 +74,6 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") -(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" - "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") - ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use ;; direct move directly, and movsf can't to move between the register sets. ;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d6ffc36..6124bce 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void) "wf reg_class = %s\n" "wg reg_class = %s\n" "wi reg_class = %s\n" - "wl reg_class = %s\n" "wp reg_class = %s\n" "wq reg_class = %s\n" "wr reg_class = %s\n" @@ -2534,7 +2533,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], @@ -3156,7 +3154,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. wi - FP or VSX register to hold 64-bit integers for VSX insns. - wl - Float register if we can do 32-bit signed int loads. wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. ws - Register class to do ISA 2.06 DF operations. @@ -3191,9 +3188,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_MFPGPR) /* DFmode */ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; - if (TARGET_LFIWAX) - rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ - if (TARGET_POWERPC64) { rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 27055a6..176f34d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ - RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 33a6de7..454518e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1019,7 +1019,7 @@ (define_insn_and_split "*extendhi2_dot2" (define_insn "extendsi2" [(set (match_operand:EXTSI 0 "gpc_reg_operand" - "=r, r, wl, wa, wi, v, v, wr") + "=r, r, d, wa, wi, v, v, wr") (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "YZ, r, Z, Z, r, v, v, ?wa")))] "" @@ -1035,7 +1035,7 @@ (define_insn "extendsi2" [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr") (set_attr "sign_extend" "yes") (set_attr "length" "4,4,4,4,4,4,8,8") - (set_attr "isa" "*,*,*,p8v,p8v,p9v,p8v,p8v")]) + (set_attr "isa" "*,*,p6,p8v,p8v,p9v,p8v,p8v")]) (define_split [(set (match_operand:EXTSI 0 "int_reg_operand") diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7ec1740..2d531cc 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3198,7 +3198,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, @code{wf}, @code{wg}, @code{wi}, -@code{wl}, @code{wp}, @code{wq}, @code{ws}, +@code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so that the correct register is used. Otherwise the register number @@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS. @item wi FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. -@item wl -Floating point register if the LFIWAX instruction is enabled or NO_REGS. - @item wn No register (NO_REGS). From patchwork Tue May 21 16:27:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102926 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501372-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="o2AvZXtL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h5f0v93z9s7h for ; Wed, 22 May 2019 02:28:21 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=SITz5u8mRWTifaFV7xP Md/DH5YmpCi8/Jv264XqmcuGQijhLWxwUHhrrxCUkIbA/UGO6huhJn9WN0XZlRJr uY2pL+UVj7xGvbrRTwlRc+oLZYCDAwMgK9j3Xpa0nGF5NJe4EleQ/UIC9lRAY5ra DD/6FvAr5LbMU7IB21RGhem4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=/neMvxadVL+qWh0N1Xicsnk3L vg=; b=o2AvZXtLk72hiS5e9fl6l8bpD4SAHdKGY4727SCTCqbmRl6Dpg4XR1Ixs eDnQUo/TfiobU1wyno9iGmKp1z5MHqaJgtejBl13QGRuohqc01j4BEq7IOSzPdqw O3bJlTRNpUWeMtac6lT+LAtxHWGWtRdoozECuQtuFg+lj6CkW8= Received: (qmail 82700 invoked by alias); 21 May 2019 16:27:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 82650 invoked by uid 89); 21 May 2019 16:27:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT autolearn=ham version=3.3.1 spammy= X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:30 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 3CFC91240630; Tue, 21 May 2019 16:27:29 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 6/6] rs6000: wz -> d+p7 Date: Tue, 21 May 2019 16:27:00 +0000 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wz"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wz. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wz" constraint by "d" with "p7". * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 8 +------- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 8 ++++---- gcc/doc/md.texi | 3 --- 5 files changed, 5 insertions(+), 18 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 802ce44..fd8be34 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -103,9 +103,6 @@ (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" "Floating point register if the STFIWX instruction is enabled or NO_REGS.") -(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" - "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") - (define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" "BASE_REGS if 64-bit instructions are enabled or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6124bce..54a3261 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2521,7 +2521,6 @@ rs6000_debug_reg_global (void) "wv reg_class = %s\n" "ww reg_class = %s\n" "wx reg_class = %s\n" - "wz reg_class = %s\n" "wA reg_class = %s\n" "\n", reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], @@ -2541,7 +2540,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]); nl = "\n"; @@ -3160,8 +3158,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wt - VSX register for TImode in VSX registers. wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. ww - Register class to do SF conversions in with VSX operations. - wx - Float register if we can do 32-bit int stores. - wz - Float register if we can do 32-bit unsigned int loads. */ + wx - Float register if we can do 32-bit int stores. */ if (TARGET_HARD_FLOAT) { @@ -3202,9 +3199,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_STFIWX) rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */ - if (TARGET_LFIWZX) - rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */ - if (TARGET_FLOAT128_TYPE) { rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 176f34d..fb94901 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1262,7 +1262,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ - RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ RS6000_CONSTRAINT_MAX }; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 454518e..32c41f3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -834,7 +834,7 @@ (define_insn_and_split "*zero_extendhi2_dot2" (define_insn "zero_extendsi2" - [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wi,r,wa") + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wi,r,wa") (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))] "" "@ @@ -846,7 +846,7 @@ (define_insn "zero_extendsi2" mfvsrwz %0,%x1 xxextractuw %x0,%x1,4" [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts") - (set_attr "isa" "*,*,*,p8v,p8v,p8v,p9v")]) + (set_attr "isa" "*,*,p7,p8v,p8v,p8v,p9v")]) (define_insn_and_split "*zero_extendsi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -7349,7 +7349,7 @@ (define_insn "movsf_hardfloat" ;; FMR MR MT%0 MF%1 NOP (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" - "=!r, wz, m, Z, ?d, ?r, + "=!r, d, m, Z, ?d, ?r, f, !r, *c*l, !r, *h") (match_operand:SD 1 "input_operand" "m, Z, r, wx, r, d, @@ -7373,7 +7373,7 @@ (define_insn "movsd_hardfloat" "load, fpload, store, fpstore, mffgpr, mftgpr, fpsimple, *, mtjmpr, mfjmpr, *") (set_attr "isa" - "*, *, *, *, p8v, p8v, + "*, p7, *, *, p8v, p8v, *, *, *, *, *")]) ;; MR MT%0 MF%0 LWZ STW LI diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 2d531cc..db9c210 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3289,9 +3289,6 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS. @item wx Floating point register if the STFIWX instruction is enabled or NO_REGS. -@item wz -Floating point register if the LFIWZX instruction is enabled or NO_REGS. - @item wA Address base register if 64-bit instructions are enabled or NO_REGS.