From patchwork Mon May 20 08:30:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 1101883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="eh592mys"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 456sYm33w6z9s9N for ; Mon, 20 May 2019 18:31:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731149AbfETIbW (ORCPT ); Mon, 20 May 2019 04:31:22 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:44115 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729675AbfETIbW (ORCPT ); Mon, 20 May 2019 04:31:22 -0400 Received: by mail-pg1-f195.google.com with SMTP id z16so6424997pgv.11 for ; Mon, 20 May 2019 01:31:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YDxVfW0Drk7B/WkdvCIQOYRuq9nRhmzNbEq0alSDlGc=; b=eh592mysWWaYmUlTdrJu5JmfPhAPRF044bjHqVn0RRF+Cc2Qvpf8BdsBT/qFoMgXr2 5WYW6pVaaaLsonApbGcCNPZ64vDP375PnN9spMsi/O/4+77Pa5K5j+U0G1JW8Hdlyk26 ZaQGBEK8AmtDo3XTJyJ/tr1m7f1jRs8XBBzfie8q34ToPxL2G5ZgqZta6ZbrlNa0QKBP 9+5BtOhM+2XG1ULJyQ48cve2UX73EL2Pf0oCJiVjDqWl2NMnFFNFgylX31O0ATpjy7It F0a3ZSGbmOfL7Ps8dHG3idQuEu8vAl7OWF/agtQUTaHdNgLG8oZuNVZB47QJDzevNA+4 Zztw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YDxVfW0Drk7B/WkdvCIQOYRuq9nRhmzNbEq0alSDlGc=; b=SYwiYVS1GWB/rnWBIxoOs7VJSlAT4hqJqG9eGikZzI/S5qOn1a15Tnlee+20BqZDN9 QfMdKzYY6zlxbjdBIa0JlyGtk6jr0GL+WzuJJ4zVLoO7KQ+mh8fK0kfHv/RzAnFMywJZ ZzY9Ttk20oDFL9DUizSO5rtdIijWK8Gq0IKmIpOaS/aWnsCWXDdzKFSMxM34w74IyL45 szSAc/ISbuQiG0hWYcYWgaFh+xI4cpRRT5vaQ8PXVuaqarVE0WDNUjgnBFj3YOHb3Hx0 aYAcSqkbg4ge4LUWdP4oZ+sl8bs5T0RgHn2cTmz9SsWRkg1/IEUTWjn2pXj7/j4cMefM NNzg== X-Gm-Message-State: APjAAAVC+FcmwVnQYe/lO6A7S72SThsrjgzmDmcUJK80n8P8oaVtWK2a AOjzXMK6WSj87mHFjxjJbm4v X-Google-Smtp-Source: APXvYqwIB4PznKqCQ1cB5xDX9ohSxJ3Q8ajVmP/fHvwxtLD7sXxbiRog+BtNITGhoESjpgVTOlJXAA== X-Received: by 2002:a63:7909:: with SMTP id u9mr67807558pgc.223.1558341081560; Mon, 20 May 2019 01:31:21 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7203:2717:7d22:7fdb:b76e:242c]) by smtp.gmail.com with ESMTPSA id s72sm24068220pgc.65.2019.05.20.01.31.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 01:31:21 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 1/5] dt-bindings: pinctrl: Modify pinctrl memory map Date: Mon, 20 May 2019 14:00:57 +0530 Message-Id: <20190520083101.10229-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Earlier, the PWM registers were included as part of the pinctrl memory map, but this turned to be useless as the muxing is being handled by the SoC pin controller itself. So, lets modify the pinctrl memory map to reflect the same. Fixes: 07b734fbdea2 ("dt-bindings: pinctrl: Add BM1880 pinctrl binding") Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt index ed34bb1ee81c..cc9a89aa4170 100644 --- a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt @@ -85,9 +85,9 @@ Required Properties: spi0 Example: - pinctrl: pinctrl@50 { + pinctrl: pinctrl@400 { compatible = "bitmain,bm1880-pinctrl"; - reg = <0x50 0x4B0>; + reg = <0x400 0x120>; pinctrl_uart0_default: uart0-default { pinmux { From patchwork Mon May 20 08:30:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 1101885 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="KyWXseoP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 456sYr6btPz9s9N for ; Mon, 20 May 2019 18:31:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731166AbfETIb2 (ORCPT ); Mon, 20 May 2019 04:31:28 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:35794 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729882AbfETIb2 (ORCPT ); Mon, 20 May 2019 04:31:28 -0400 Received: by mail-pg1-f194.google.com with SMTP id t1so5022353pgc.2 for ; Mon, 20 May 2019 01:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OWo8Uulihvaq9zy3I0w67p1cVDmaIdDDpV04dYtjBE8=; b=KyWXseoPwNWVph/2LYqJ7XtWB++4XFV14lGAlh0XyfkDC+WFnwSAVrpHZ7LnWmVHNE /+OJJm/I2OI/6rwUZL4YNI3DV3sZnUqWe4nbib6CR3PGfaFrxtjJA+ARiJLuKXPl3Phx +IV8YI7LAA1WxsrFW7o8lOnwnfdUpYfktee+Xfhf8BFt9z9OXSsOg2OTQufei6iVkOk5 n0Hf31CIwq3xCOKdcff7Aa3ZMywrRrX0OuIoYetcoEBGCPpFNCPswN+wekoiwwKAsxbp g5VELbnAmdPMNGrjkCRCj4rg6G2ebRtzIxPjYaslK+2OBBXeC/3kod5v1EtN43HxCMJ9 oLIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OWo8Uulihvaq9zy3I0w67p1cVDmaIdDDpV04dYtjBE8=; b=GmyYaA4G5lTA3vM6Kgcuhl2ovNFkE8C1F2WdpCSnz0cs4ko7gshFCeSh2m4sw1vL6f iZhYXsbADqpGmcjR841C25Ll7UmxHcBmcuK6d4vDvRoE55IRcBHiq4tvazKLLKk5zKgq 08JODioCmocBmWcbYRLdLn3gVlOaQbwA1FKPaFyhBsI4/e4XIDK7RpEoIMEe1rvcfOkm NUEKt8lW9h2WVMzyKLRpUkvP4eafC3Y5tc2aUaw9qzoI0HgSFqc+xmD9A2xJ/5y6JY4p 2AXDDmyck9Ijav5e8dhHN2aCk4rfHb5MkPaN1Fr6jLmLkP1XSR+ttjVZEI7tT1bOBrpb ZcwA== X-Gm-Message-State: APjAAAVUT5G7YmqNdl2AKVrlBUMFYLtFrI63p6vsgttkBdaUQ5VHA+4d Uum8EK9KmLPvO+nrOcZ+hVTb X-Google-Smtp-Source: APXvYqwba4qh7qxpJyc9Shot/nunx5rmufZCNsCBbq7hfOm3Lnju8hTbLBzaiGhYCaJd7E7ncz5dew== X-Received: by 2002:a63:e406:: with SMTP id a6mr75142659pgi.132.1558341087636; Mon, 20 May 2019 01:31:27 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7203:2717:7d22:7fdb:b76e:242c]) by smtp.gmail.com with ESMTPSA id s72sm24068220pgc.65.2019.05.20.01.31.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 01:31:27 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 2/5] arm64: dts: bitmain: Modify pin controller memory map Date: Mon, 20 May 2019 14:00:58 +0530 Message-Id: <20190520083101.10229-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Earlier, the PWM registers were included as part of the pinctrl memory map, but this turned to be useless as the muxing is being handled by the SoC pin controller itself. Hence, this commit removes the pwm register mapping from the pinctrl node to make it more clean. Fixes: af2ff87de413 ("arm64: dts: bitmain: Add pinctrl support for BM1880 SoC") Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index ee7e6abcc813..b2497a090402 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -88,9 +88,9 @@ #size-cells = <1>; ranges = <0x0 0x0 0x50010000 0x1000>; - pinctrl: pinctrl@50 { + pinctrl: pinctrl@400 { compatible = "bitmain,bm1880-pinctrl"; - reg = <0x50 0x4B0>; + reg = <0x400 0x120>; }; rst: reset-controller@c00 { From patchwork Mon May 20 08:30:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 1101886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="bZIN8dUi"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 456sZ32Gdnz9s9N for ; Mon, 20 May 2019 18:31:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727572AbfETIbi (ORCPT ); Mon, 20 May 2019 04:31:38 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:33018 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731153AbfETIbe (ORCPT ); Mon, 20 May 2019 04:31:34 -0400 Received: by mail-pg1-f194.google.com with SMTP id h17so6452764pgv.0 for ; Mon, 20 May 2019 01:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Si56RYW0rDfcSDqNug0vtP93R/nK3dxtiVT54Kdd1dY=; b=bZIN8dUi+6eyNtKyt78Diu6rM48ITAzE9t3Aw9BfX0IZleiHbCYbVzt77+o352lDqj tOrBepTN8Zl43i8WVs377jsTQC8JpeN2UKVor1oS+LX1tdNn8uale8BGVbgdmf/qO8Xy azFiE6NMQIdYDdKvKdNk3UyWKzjOl7njNb9K1JibaS2ZVPLInz7nA8dZLs/ETKNaeQJS 7cyDfPddQxmXxmirkyLGZA8BoI13Tqmxmbd9igyfRl0dvQhYS2nD0HkxBtLAreq+/iR0 VclaBsjIs7VBWxAzxB/BCpHEgftOT3QydBz3k/YHks/pJ+RtAt5szBWItGirp9GYaOVP iF5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Si56RYW0rDfcSDqNug0vtP93R/nK3dxtiVT54Kdd1dY=; b=EbbuxKfeLhQ5GHb2su83Mz71HmKlP6ft+YNMZX9VoDkpH1qvdAhIMvD8HDx2I+4urs HpPizxnkY7bi59wiVpmyhRQ6NHPQgF8UmsElD+FDQP9oS7mqsQKFLpiGrgHFaxRycSrd 7pfs1D/+dgKfMsGfmHNeYbPgOFtsZTOKDsInemMzW0rX7T70TFNiQwBKikg7aiMwc54V WUWGGMrae+0QEYYXT3a61761de7Lzt9Es6vo4L4Ii13ySEG026XYwOId6M5WwKimD45h pjPSKgdI4aZ/Ex4dkw61d/wepSIdOu9BfO5eGjXDW95U+6BMWU8F2Zuad3cZBqRGJ9fj hBiA== X-Gm-Message-State: APjAAAUwC6hW6gXfftTuS6hqOwz9LB01Keg6q0Bl0l+VvIOBWfnTYUF6 OBoeyNhHSIPR+EZofaQB8+nZ X-Google-Smtp-Source: APXvYqxAHZiNQs06FzMcON/FZ1IGTEzy70/qPNePj4tc5VVBAHYNGtKcCQNnnf5BsLeu5RxKvYfm0w== X-Received: by 2002:a05:6a00:43:: with SMTP id i3mr599628pfk.113.1558341093415; Mon, 20 May 2019 01:31:33 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7203:2717:7d22:7fdb:b76e:242c]) by smtp.gmail.com with ESMTPSA id s72sm24068220pgc.65.2019.05.20.01.31.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 01:31:32 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 3/5] pinctrl: Rework the pinmux handling for BM1880 SoC Date: Mon, 20 May 2019 14:00:59 +0530 Message-Id: <20190520083101.10229-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Rework the BM1880 SoC pinmux handling by removing the BM1880_PINMUX_FUNCTION_MUX define and merging it with the BM1880_PINMUX_FUNCTION definition. Since the PWM muxing is handled by generic pin controller in the SoC itself, there is no need to have a dedicated code to do the muxing in PWM registers. So, lets club all pinmux handling in the same per pin mux handling code. Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/pinctrl-bm1880.c | 323 ++++++++++++++----------------- 1 file changed, 149 insertions(+), 174 deletions(-) diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index 446b07d8fbfc..bddb705ea142 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -55,7 +55,6 @@ struct bm1880_pctrl_group { * @groups: List of pingroups for this function. * @ngroups: Number of entries in @groups. * @mux_val: Selector for this function - * @mux_mask: Mask for function specific selector * @mux: Offset of function specific mux * @mux_shift: Shift for function specific selector */ @@ -64,7 +63,6 @@ struct bm1880_pinmux_function { const char * const *groups; unsigned int ngroups; u32 mux_val; - u32 mux_mask; u32 mux; u8 mux_shift; }; @@ -636,165 +634,153 @@ static const char * const i2s1_group[] = { "i2s1_grp" }; static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" }; static const char * const spi0_group[] = { "spi0_grp" }; -#define BM1880_PINMUX_FUNCTION(fname, mval, mask) \ +#define BM1880_PINMUX_FUNCTION(fname, mval) \ [F_##fname] = { \ .name = #fname, \ .groups = fname##_group, \ .ngroups = ARRAY_SIZE(fname##_group), \ .mux_val = mval, \ - .mux_mask = mask, \ - } - -#define BM1880_PINMUX_FUNCTION_MUX(fname, mval, mask, offset, shift)\ - [F_##fname] = { \ - .name = #fname, \ - .groups = fname##_group, \ - .ngroups = ARRAY_SIZE(fname##_group), \ - .mux_val = mval, \ - .mux_mask = mask, \ - .mux = offset, \ - .mux_shift = shift, \ } static const struct bm1880_pinmux_function bm1880_pmux_functions[] = { - BM1880_PINMUX_FUNCTION(nand, 2, 0x03), - BM1880_PINMUX_FUNCTION(spi, 0, 0x03), - BM1880_PINMUX_FUNCTION(emmc, 1, 0x03), - BM1880_PINMUX_FUNCTION(sdio, 0, 0x03), - BM1880_PINMUX_FUNCTION(eth0, 0, 0x03), - BM1880_PINMUX_FUNCTION_MUX(pwm0, 2, 0x0F, 0x50, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm1, 2, 0x0F, 0x50, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm2, 2, 0x0F, 0x50, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm3, 2, 0x0F, 0x50, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm4, 2, 0x0F, 0x50, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm5, 2, 0x0F, 0x50, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm6, 2, 0x0F, 0x50, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm7, 2, 0x0F, 0x50, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm8, 2, 0x0F, 0x54, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm9, 2, 0x0F, 0x54, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm10, 2, 0x0F, 0x54, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm11, 2, 0x0F, 0x54, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm12, 2, 0x0F, 0x54, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm13, 2, 0x0F, 0x54, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm14, 2, 0x0F, 0x54, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm15, 2, 0x0F, 0x54, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm16, 2, 0x0F, 0x58, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm17, 2, 0x0F, 0x58, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm18, 2, 0x0F, 0x58, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm19, 2, 0x0F, 0x58, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm20, 2, 0x0F, 0x58, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm21, 2, 0x0F, 0x58, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm22, 2, 0x0F, 0x58, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm23, 2, 0x0F, 0x58, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm24, 2, 0x0F, 0x5C, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm25, 2, 0x0F, 0x5C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm26, 2, 0x0F, 0x5C, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm27, 2, 0x0F, 0x5C, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm28, 2, 0x0F, 0x5C, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm29, 2, 0x0F, 0x5C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm30, 2, 0x0F, 0x5C, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm31, 2, 0x0F, 0x5C, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm32, 2, 0x0F, 0x60, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm33, 2, 0x0F, 0x60, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm34, 2, 0x0F, 0x60, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm35, 2, 0x0F, 0x60, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm36, 2, 0x0F, 0x60, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm37, 2, 0x0F, 0x60, 0x1C), - BM1880_PINMUX_FUNCTION(i2c0, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c1, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c2, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c3, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c4, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart0, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart1, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart2, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart3, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart4, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart5, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart6, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart7, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart8, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart9, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart10, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart11, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart12, 3, 0x03), - BM1880_PINMUX_FUNCTION(uart13, 3, 0x03), - BM1880_PINMUX_FUNCTION(uart14, 3, 0x03), - BM1880_PINMUX_FUNCTION(uart15, 3, 0x03), - BM1880_PINMUX_FUNCTION_MUX(gpio0, 0, 0x03, 0x4E0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio1, 0, 0x03, 0x4E4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio2, 0, 0x03, 0x4E4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio3, 0, 0x03, 0x4E8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio4, 0, 0x03, 0x4E8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio5, 0, 0x03, 0x4EC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio6, 0, 0x03, 0x4EC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio7, 0, 0x03, 0x4F0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio8, 0, 0x03, 0x4F0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio9, 0, 0x03, 0x4F4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio10, 0, 0x03, 0x4F4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio11, 0, 0x03, 0x4F8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio12, 1, 0x03, 0x4F8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio13, 1, 0x03, 0x4FC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio14, 0, 0x03, 0x474, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio15, 0, 0x03, 0x478, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio16, 0, 0x03, 0x478, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio17, 0, 0x03, 0x47C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio18, 0, 0x03, 0x47C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio19, 0, 0x03, 0x480, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio20, 0, 0x03, 0x480, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio21, 0, 0x03, 0x484, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio22, 0, 0x03, 0x484, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio23, 0, 0x03, 0x488, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio24, 0, 0x03, 0x488, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio25, 0, 0x03, 0x48C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio26, 0, 0x03, 0x48C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio27, 0, 0x03, 0x490, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio28, 0, 0x03, 0x490, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio29, 0, 0x03, 0x494, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio30, 0, 0x03, 0x494, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio31, 0, 0x03, 0x498, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio32, 0, 0x03, 0x498, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio33, 0, 0x03, 0x49C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio34, 0, 0x03, 0x49C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio35, 0, 0x03, 0x4A0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio36, 0, 0x03, 0x4A0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio37, 0, 0x03, 0x4A4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio38, 0, 0x03, 0x4A4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio39, 0, 0x03, 0x4A8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio40, 0, 0x03, 0x4A8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio41, 0, 0x03, 0x4AC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio42, 0, 0x03, 0x4AC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio43, 0, 0x03, 0x4B0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio44, 0, 0x03, 0x4B0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio45, 0, 0x03, 0x4B4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio46, 0, 0x03, 0x4B4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio47, 0, 0x03, 0x4B8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio48, 0, 0x03, 0x4B8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio49, 0, 0x03, 0x4BC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio50, 0, 0x03, 0x4BC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio51, 0, 0x03, 0x4C0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio52, 0, 0x03, 0x4C0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio53, 0, 0x03, 0x4C4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio54, 0, 0x03, 0x4C4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio55, 0, 0x03, 0x4C8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio56, 0, 0x03, 0x4C8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio57, 0, 0x03, 0x4CC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio58, 0, 0x03, 0x4CC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio59, 0, 0x03, 0x4D0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio60, 0, 0x03, 0x4D0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio61, 0, 0x03, 0x4D4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio62, 0, 0x03, 0x4D4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio63, 0, 0x03, 0x4D8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio64, 0, 0x03, 0x4D8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio65, 0, 0x03, 0x4DC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio66, 0, 0x03, 0x4DC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio67, 0, 0x03, 0x4E0, 0x04), - BM1880_PINMUX_FUNCTION(eth1, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2s0, 2, 0x03), - BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2s1, 2, 0x03), - BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1, 0x03), - BM1880_PINMUX_FUNCTION(spi0, 1, 0x03), + BM1880_PINMUX_FUNCTION(nand, 2), + BM1880_PINMUX_FUNCTION(spi, 0), + BM1880_PINMUX_FUNCTION(emmc, 1), + BM1880_PINMUX_FUNCTION(sdio, 0), + BM1880_PINMUX_FUNCTION(eth0, 0), + BM1880_PINMUX_FUNCTION(pwm0, 2), + BM1880_PINMUX_FUNCTION(pwm1, 2), + BM1880_PINMUX_FUNCTION(pwm2, 2), + BM1880_PINMUX_FUNCTION(pwm3, 2), + BM1880_PINMUX_FUNCTION(pwm4, 2), + BM1880_PINMUX_FUNCTION(pwm5, 2), + BM1880_PINMUX_FUNCTION(pwm6, 2), + BM1880_PINMUX_FUNCTION(pwm7, 2), + BM1880_PINMUX_FUNCTION(pwm8, 2), + BM1880_PINMUX_FUNCTION(pwm9, 2), + BM1880_PINMUX_FUNCTION(pwm10, 2), + BM1880_PINMUX_FUNCTION(pwm11, 2), + BM1880_PINMUX_FUNCTION(pwm12, 2), + BM1880_PINMUX_FUNCTION(pwm13, 2), + BM1880_PINMUX_FUNCTION(pwm14, 2), + BM1880_PINMUX_FUNCTION(pwm15, 2), + BM1880_PINMUX_FUNCTION(pwm16, 2), + BM1880_PINMUX_FUNCTION(pwm17, 2), + BM1880_PINMUX_FUNCTION(pwm18, 2), + BM1880_PINMUX_FUNCTION(pwm19, 2), + BM1880_PINMUX_FUNCTION(pwm20, 2), + BM1880_PINMUX_FUNCTION(pwm21, 2), + BM1880_PINMUX_FUNCTION(pwm22, 2), + BM1880_PINMUX_FUNCTION(pwm23, 2), + BM1880_PINMUX_FUNCTION(pwm24, 2), + BM1880_PINMUX_FUNCTION(pwm25, 2), + BM1880_PINMUX_FUNCTION(pwm26, 2), + BM1880_PINMUX_FUNCTION(pwm27, 2), + BM1880_PINMUX_FUNCTION(pwm28, 2), + BM1880_PINMUX_FUNCTION(pwm29, 2), + BM1880_PINMUX_FUNCTION(pwm30, 2), + BM1880_PINMUX_FUNCTION(pwm31, 2), + BM1880_PINMUX_FUNCTION(pwm32, 2), + BM1880_PINMUX_FUNCTION(pwm33, 2), + BM1880_PINMUX_FUNCTION(pwm34, 2), + BM1880_PINMUX_FUNCTION(pwm35, 2), + BM1880_PINMUX_FUNCTION(pwm36, 2), + BM1880_PINMUX_FUNCTION(pwm37, 2), + BM1880_PINMUX_FUNCTION(i2c0, 1), + BM1880_PINMUX_FUNCTION(i2c1, 1), + BM1880_PINMUX_FUNCTION(i2c2, 1), + BM1880_PINMUX_FUNCTION(i2c3, 1), + BM1880_PINMUX_FUNCTION(i2c4, 1), + BM1880_PINMUX_FUNCTION(uart0, 3), + BM1880_PINMUX_FUNCTION(uart1, 3), + BM1880_PINMUX_FUNCTION(uart2, 3), + BM1880_PINMUX_FUNCTION(uart3, 3), + BM1880_PINMUX_FUNCTION(uart4, 1), + BM1880_PINMUX_FUNCTION(uart5, 1), + BM1880_PINMUX_FUNCTION(uart6, 1), + BM1880_PINMUX_FUNCTION(uart7, 1), + BM1880_PINMUX_FUNCTION(uart8, 1), + BM1880_PINMUX_FUNCTION(uart9, 1), + BM1880_PINMUX_FUNCTION(uart10, 1), + BM1880_PINMUX_FUNCTION(uart11, 1), + BM1880_PINMUX_FUNCTION(uart12, 3), + BM1880_PINMUX_FUNCTION(uart13, 3), + BM1880_PINMUX_FUNCTION(uart14, 3), + BM1880_PINMUX_FUNCTION(uart15, 3), + BM1880_PINMUX_FUNCTION(gpio0, 0), + BM1880_PINMUX_FUNCTION(gpio1, 0), + BM1880_PINMUX_FUNCTION(gpio2, 0), + BM1880_PINMUX_FUNCTION(gpio3, 0), + BM1880_PINMUX_FUNCTION(gpio4, 0), + BM1880_PINMUX_FUNCTION(gpio5, 0), + BM1880_PINMUX_FUNCTION(gpio6, 0), + BM1880_PINMUX_FUNCTION(gpio7, 0), + BM1880_PINMUX_FUNCTION(gpio8, 0), + BM1880_PINMUX_FUNCTION(gpio9, 0), + BM1880_PINMUX_FUNCTION(gpio10, 0), + BM1880_PINMUX_FUNCTION(gpio11, 0), + BM1880_PINMUX_FUNCTION(gpio12, 1), + BM1880_PINMUX_FUNCTION(gpio13, 1), + BM1880_PINMUX_FUNCTION(gpio14, 0), + BM1880_PINMUX_FUNCTION(gpio15, 0), + BM1880_PINMUX_FUNCTION(gpio16, 0), + BM1880_PINMUX_FUNCTION(gpio17, 0), + BM1880_PINMUX_FUNCTION(gpio18, 0), + BM1880_PINMUX_FUNCTION(gpio19, 0), + BM1880_PINMUX_FUNCTION(gpio20, 0), + BM1880_PINMUX_FUNCTION(gpio21, 0), + BM1880_PINMUX_FUNCTION(gpio22, 0), + BM1880_PINMUX_FUNCTION(gpio23, 0), + BM1880_PINMUX_FUNCTION(gpio24, 0), + BM1880_PINMUX_FUNCTION(gpio25, 0), + BM1880_PINMUX_FUNCTION(gpio26, 0), + BM1880_PINMUX_FUNCTION(gpio27, 0), + BM1880_PINMUX_FUNCTION(gpio28, 0), + BM1880_PINMUX_FUNCTION(gpio29, 0), + BM1880_PINMUX_FUNCTION(gpio30, 0), + BM1880_PINMUX_FUNCTION(gpio31, 0), + BM1880_PINMUX_FUNCTION(gpio32, 0), + BM1880_PINMUX_FUNCTION(gpio33, 0), + BM1880_PINMUX_FUNCTION(gpio34, 0), + BM1880_PINMUX_FUNCTION(gpio35, 0), + BM1880_PINMUX_FUNCTION(gpio36, 0), + BM1880_PINMUX_FUNCTION(gpio37, 0), + BM1880_PINMUX_FUNCTION(gpio38, 0), + BM1880_PINMUX_FUNCTION(gpio39, 0), + BM1880_PINMUX_FUNCTION(gpio40, 0), + BM1880_PINMUX_FUNCTION(gpio41, 0), + BM1880_PINMUX_FUNCTION(gpio42, 0), + BM1880_PINMUX_FUNCTION(gpio43, 0), + BM1880_PINMUX_FUNCTION(gpio44, 0), + BM1880_PINMUX_FUNCTION(gpio45, 0), + BM1880_PINMUX_FUNCTION(gpio46, 0), + BM1880_PINMUX_FUNCTION(gpio47, 0), + BM1880_PINMUX_FUNCTION(gpio48, 0), + BM1880_PINMUX_FUNCTION(gpio49, 0), + BM1880_PINMUX_FUNCTION(gpio50, 0), + BM1880_PINMUX_FUNCTION(gpio51, 0), + BM1880_PINMUX_FUNCTION(gpio52, 0), + BM1880_PINMUX_FUNCTION(gpio53, 0), + BM1880_PINMUX_FUNCTION(gpio54, 0), + BM1880_PINMUX_FUNCTION(gpio55, 0), + BM1880_PINMUX_FUNCTION(gpio56, 0), + BM1880_PINMUX_FUNCTION(gpio57, 0), + BM1880_PINMUX_FUNCTION(gpio58, 0), + BM1880_PINMUX_FUNCTION(gpio59, 0), + BM1880_PINMUX_FUNCTION(gpio60, 0), + BM1880_PINMUX_FUNCTION(gpio61, 0), + BM1880_PINMUX_FUNCTION(gpio62, 0), + BM1880_PINMUX_FUNCTION(gpio63, 0), + BM1880_PINMUX_FUNCTION(gpio64, 0), + BM1880_PINMUX_FUNCTION(gpio65, 0), + BM1880_PINMUX_FUNCTION(gpio66, 0), + BM1880_PINMUX_FUNCTION(gpio67, 0), + BM1880_PINMUX_FUNCTION(eth1, 1), + BM1880_PINMUX_FUNCTION(i2s0, 2), + BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1), + BM1880_PINMUX_FUNCTION(i2s1, 2), + BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1), + BM1880_PINMUX_FUNCTION(spi0, 1), }; static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev) @@ -870,28 +856,17 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, const struct bm1880_pinmux_function *func = &pctrl->funcs[function]; int i; - if (func->mux) { + for (i = 0; i < pgrp->npins; i++) { + unsigned int pin = pgrp->pins[i]; + u32 offset = (pin >> 1) << 2; + u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4); u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + - func->mux); - - regval &= ~(func->mux_mask << func->mux_shift); - regval |= func->mux_val << func->mux_shift; - writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + - func->mux); - } else { - for (i = 0; i < pgrp->npins; i++) { - unsigned int pin = pgrp->pins[i]; - u32 offset = (pin >> 1) << 2; - u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4); - u32 regval = readl_relaxed(pctrl->base + - BM1880_REG_MUX + offset); - - regval &= ~(func->mux_mask << mux_offset); - regval |= func->mux_val << mux_offset; - - writel_relaxed(regval, pctrl->base + - BM1880_REG_MUX + offset); - } + offset); + + regval &= ~(0x03 << mux_offset); + regval |= func->mux_val << mux_offset; + + writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); } return 0; From patchwork Mon May 20 08:31:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 1101887 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="dm6WPKZx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 456sZ417Nbz9sDn for ; Mon, 20 May 2019 18:31:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730315AbfETIbj (ORCPT ); Mon, 20 May 2019 04:31:39 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:35809 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728619AbfETIbj (ORCPT ); Mon, 20 May 2019 04:31:39 -0400 Received: by mail-pg1-f194.google.com with SMTP id t1so5022575pgc.2 for ; Mon, 20 May 2019 01:31:39 -0700 (PDT) DKIM-Signature: v=1; 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[PATCH 4/5] dt-bindings: pinctrl: Document pinconf bindings for BM1880 SoC Date: Mon, 20 May 2019 14:01:00 +0530 Message-Id: <20190520083101.10229-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document pinconf bindings for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam --- .../pinctrl/bitmain,bm1880-pinctrl.txt | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt index cc9a89aa4170..4eb089bcb5f3 100644 --- a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt @@ -14,7 +14,8 @@ phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration for BM1880 SoC -includes only pinmux as there is no pinconf support available in SoC. +includes pinmux and various pin configuration parameters, such as pull-up, +slew rate etc... Each configuration node can consist of multiple nodes describing the pinmux options. The name of each subnode is not important; all subnodes should be @@ -84,6 +85,22 @@ Required Properties: gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, spi0 +Optional Properties: + +- bias-disable: No arguments. Disable pin bias. +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- slew-rate: Integer. Sets slew rate for the specified pins. + Valid values are: + <0> - Slow + <1> - Fast + Example: pinctrl: pinctrl@400 { compatible = "bitmain,bm1880-pinctrl"; From patchwork Mon May 20 08:31:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 1101889 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="wYliaoyk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 456sZ94Q1nz9s55 for ; Mon, 20 May 2019 18:31:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731408AbfETIbo (ORCPT ); Mon, 20 May 2019 04:31:44 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:47020 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729325AbfETIbo (ORCPT ); Mon, 20 May 2019 04:31:44 -0400 Received: by mail-pf1-f196.google.com with SMTP id y11so6844969pfm.13 for ; Mon, 20 May 2019 01:31:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wZmd2sSqxBswncIP49DIhHiOiWPLqbCT+QWxEkOy/co=; b=wYliaoykTkMBfrBtk1tyMUrq5pCqug2hVNjNDCjfWMPgRZxZ6r8MN4oCs0as2iaX94 l49bbHxM/Ti/+pMIToe0NVyxo05Q8o0gotf2D7drpAiFeSQyPFce7ouk2hWMIO2ewDcH JC6lsKRqIABuvaVlrXyQqTXmgbzAWszMlw2xm1zaJUoJFg4G7hfuhMLQ9iRwbHUhtoM9 lj3mGApdgSgzKfp+rtMsHkY1r/mdKPtaLoBvgCZlvTPz3/Dza8DVB6dRnSx3bBJi6tTW OWmmmVXz7I6sDmRs1+j8SrGk7+yGW4Pknp8FJigwuR1P747ZiuG9Xsu2ZmtYbaJSdj7i UaKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wZmd2sSqxBswncIP49DIhHiOiWPLqbCT+QWxEkOy/co=; b=aIfhE/wDVETzgcB9YLr6g57bQzJLiTo86fO0RtXSHqn4HwCAmEfKrS+5mYunstla4I RYEiywTC4nHgnmAzK5shkU374gs1cg3dS/o4ZOEOiA7sON5cvs++gAyQFklm/aFC4Zcc 6XiZjG7iCxV4eFBhpGIvd8yFzRGYLlgoL1vzelSNT3ROOAHIPPplXr6UGx4sbzJKsUDa 8/6uAJ2PYFcKUKqqi5/MqE0op19VjuNvuq1IFOezdNHBJaejCgCFHdf8xqyNS7mlU7tt ZGixLE2MVLO+9n27JmLvqqTET+JwaE26obdVEnjntJ3+gBpNhcHK5j1TwxLfuY29c+Lm K9og== X-Gm-Message-State: APjAAAXa6LOFfFzdLHEnPuLygImTjZlxZqQOgl+Ha8qfxWMuEfn7r84y cX4YQ7dAqbUvDUzgCloBHdGZ X-Google-Smtp-Source: APXvYqxtgRk9hUYeKzUqFkTBf75l2tsN0xCN0ekdZ9P/6ymdT9+k/j2ax6QYys17dUs7LvLpFXwXGQ== X-Received: by 2002:a62:86c4:: with SMTP id x187mr77900616pfd.34.1558341103495; Mon, 20 May 2019 01:31:43 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7203:2717:7d22:7fdb:b76e:242c]) by smtp.gmail.com with ESMTPSA id s72sm24068220pgc.65.2019.05.20.01.31.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 01:31:43 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 5/5] pinctrl: Add pinconf support for BM1880 SoC Date: Mon, 20 May 2019 14:01:01 +0530 Message-Id: <20190520083101.10229-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinconf support for Bitmain BM1880 SoC. Pinconf support includes pin bias, slew rate and schmitt trigger. Drive strength support will be added later. Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/pinctrl-bm1880.c | 134 +++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index bddb705ea142..1aaed46d5c30 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -4,6 +4,8 @@ * * Copyright (c) 2019 Linaro Ltd. * Author: Manivannan Sadhasivam + * + * TODO: Drive strength support */ #include @@ -872,6 +874,137 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +#define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx) +#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0) +#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1) +#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2) +#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9) +#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10) + +static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg = 0; + u32 regval, offset, bit_offset; + + offset = (pin >> 1) << 2; + regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bit_offset = BM1880_PINCONF_PULLUP(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bit_offset = BM1880_PINCONF_PULLDOWN(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_BIAS_DISABLE: + bit_offset = BM1880_PINCONF_PULLCTRL(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bit_offset = BM1880_PINCONF_SCHMITT(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_SLEW_RATE: + bit_offset = BM1880_PINCONF_SLEW(pin); + arg = !!(regval & BIT(bit_offset)); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 regval, offset, bit_offset; + int i; + + offset = (pin >> 1) << 2; + regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); + + for (i = 0; i < num_configs; i++) { + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bit_offset = BM1880_PINCONF_PULLUP(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bit_offset = BM1880_PINCONF_PULLDOWN(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_BIAS_DISABLE: + bit_offset = BM1880_PINCONF_PULLCTRL(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bit_offset = BM1880_PINCONF_SCHMITT(pin); + if (arg) + regval |= BIT(bit_offset); + else + regval &= ~BIT(bit_offset); + break; + case PIN_CONFIG_SLEW_RATE: + bit_offset = BM1880_PINCONF_SLEW(pin); + if (arg) + regval |= BIT(bit_offset); + else + regval &= ~BIT(bit_offset); + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter '%u'\n", + param); + continue; + } + + writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); + } + + return 0; +} + +static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector]; + + for (i = 0; i < pgrp->npins; i++) { + ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops bm1880_pinconf_ops = { + .is_generic = true, + .pin_config_get = bm1880_pinconf_cfg_get, + .pin_config_set = bm1880_pinconf_cfg_set, + .pin_config_group_set = bm1880_pinconf_group_set, +}; + static const struct pinmux_ops bm1880_pinmux_ops = { .get_functions_count = bm1880_pmux_get_functions_count, .get_function_name = bm1880_pmux_get_function_name, @@ -885,6 +1018,7 @@ static struct pinctrl_desc bm1880_desc = { .npins = ARRAY_SIZE(bm1880_pins), .pctlops = &bm1880_pctrl_ops, .pmxops = &bm1880_pinmux_ops, + .confops = &bm1880_pinconf_ops, .owner = THIS_MODULE, };