From patchwork Thu May 16 09:02:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 1100426 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 454QSW42M6z9sDn for ; Thu, 16 May 2019 19:03:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726363AbfEPJCf (ORCPT ); Thu, 16 May 2019 05:02:35 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:44447 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726425AbfEPJCe (ORCPT ); Thu, 16 May 2019 05:02:34 -0400 X-UUID: cb01de0f6bc54836a75e57e9a99ef435-20190516 X-UUID: cb01de0f6bc54836a75e57e9a99ef435-20190516 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 115543635; Thu, 16 May 2019 17:02:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:02:26 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:02:26 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU CC: Daniel Kurtz , Sascha Hauer , , , , , , Sascha Hauer , Philipp Zabel , Nicolas Boichat , YT Shen , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Houlong Wei , , Bibby Hsieh Subject: [PATCH v6 01/12] dt-binding: gce: remove thread-num property Date: Thu, 16 May 2019 17:02:13 +0800 Message-ID: <20190516090224.59070-2-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190516090224.59070-1-bibby.hsieh@mediatek.com> References: <20190516090224.59070-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 21B5A56CDC34775FA7A32B331C09D724A0D0ADB9E3D6E5F5204451690EC899952000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org "thread-num" is an unused property so we remove it from example. Signed-off-by: Bibby Hsieh Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 7d72b21c9e94..cfe40b01d164 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -39,7 +39,6 @@ Example: interrupts = ; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - thread-num = CMDQ_THR_MAX_COUNT; #mbox-cells = <3>; }; From patchwork Thu May 16 09:02:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 1100421 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 454QRs4m5Nz9sDn for ; Thu, 16 May 2019 19:02:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727179AbfEPJCs (ORCPT ); Thu, 16 May 2019 05:02:48 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16135 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727149AbfEPJCr (ORCPT ); Thu, 16 May 2019 05:02:47 -0400 X-UUID: 15780a2c534643ed9c426ba8c3c97898-20190516 X-UUID: 15780a2c534643ed9c426ba8c3c97898-20190516 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 263066350; Thu, 16 May 2019 17:02:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:02:27 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:02:26 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU CC: Daniel Kurtz , Sascha Hauer , , , , , , "Sascha Hauer" , Philipp Zabel , Nicolas Boichat , YT Shen , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Houlong Wei , , "Bibby Hsieh" Subject: [PATCH v6 02/12] dt-binding: gce: add gce header file for mt8183 Date: Thu, 16 May 2019 17:02:14 +0800 Message-ID: <20190516090224.59070-3-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190516090224.59070-1-bibby.hsieh@mediatek.com> References: <20190516090224.59070-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the mt8183 gce. Add gce header file defined the gce hardware event, subsys number and constant for mt8183. Signed-off-by: Bibby Hsieh Reviewed-by: Rob Herring --- .../devicetree/bindings/mailbox/mtk-gce.txt | 6 +- include/dt-bindings/gce/mt8183-gce.h | 177 ++++++++++++++++++ 2 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/gce/mt8183-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index cfe40b01d164..1f7f8f2a3f49 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to mailbox.txt for generic information about mailbox device-tree bindings. Required properties: -- compatible: Must be "mediatek,mt8173-gce" +- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce" - reg: Address range of the GCE unit - interrupts: The interrupt signal from the GCE block - clock: Clocks according to the common clock binding @@ -28,8 +28,8 @@ Required properties for a client device: - mediatek,gce-subsys: u32, specify the sub-system id which is corresponding to the register address. -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as -sub-system ids, thread priority, event ids. +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' +or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/include/dt-bindings/gce/mt8183-gce.h b/include/dt-bindings/gce/mt8183-gce.h new file mode 100644 index 000000000000..aeb95154fac2 --- /dev/null +++ b/include/dt-bindings/gce/mt8183-gce.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Bibby Hsieh + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8183_H +#define _DT_BINDINGS_GCE_MT8183_H + +#define CMDQ_NO_TIMEOUT 0xffffffff + +#define CMDQ_THR_MAX_COUNT 24 + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1502XXXX 4 +#define SUBSYS_1880XXXX 5 +#define SUBSYS_1881XXXX 6 +#define SUBSYS_1882XXXX 7 +#define SUBSYS_1883XXXX 8 +#define SUBSYS_1884XXXX 9 +#define SUBSYS_1000XXXX 10 +#define SUBSYS_1001XXXX 11 +#define SUBSYS_1002XXXX 12 +#define SUBSYS_1003XXXX 13 +#define SUBSYS_1004XXXX 14 +#define SUBSYS_1005XXXX 15 +#define SUBSYS_1020XXXX 16 +#define SUBSYS_1028XXXX 17 +#define SUBSYS_1700XXXX 18 +#define SUBSYS_1701XXXX 19 +#define SUBSYS_1702XXXX 20 +#define SUBSYS_1703XXXX 21 +#define SUBSYS_1800XXXX 22 +#define SUBSYS_1801XXXX 23 +#define SUBSYS_1802XXXX 24 +#define SUBSYS_1804XXXX 25 +#define SUBSYS_1805XXXX 26 +#define SUBSYS_1808XXXX 27 +#define SUBSYS_180aXXXX 28 +#define SUBSYS_180bXXXX 29 + +#define CMDQ_EVENT_DISP_RDMA0_SOF 0 +#define CMDQ_EVENT_DISP_RDMA1_SOF 1 +#define CMDQ_EVENT_MDP_RDMA0_SOF 2 +#define CMDQ_EVENT_MDP_RSZ0_SOF 4 +#define CMDQ_EVENT_MDP_RSZ1_SOF 5 +#define CMDQ_EVENT_MDP_TDSHP_SOF 6 +#define CMDQ_EVENT_MDP_WROT0_SOF 7 +#define CMDQ_EVENT_MDP_WDMA0_SOF 8 +#define CMDQ_EVENT_DISP_OVL0_SOF 9 +#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10 +#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11 +#define CMDQ_EVENT_DISP_WDMA0_SOF 12 +#define CMDQ_EVENT_DISP_COLOR0_SOF 13 +#define CMDQ_EVENT_DISP_CCORR0_SOF 14 +#define CMDQ_EVENT_DISP_AAL0_SOF 15 +#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 +#define CMDQ_EVENT_DISP_DITHER0_SOF 17 +#define CMDQ_EVENT_DISP_PWM0_SOF 18 +#define CMDQ_EVENT_DISP_DSI0_SOF 19 +#define CMDQ_EVENT_DISP_DPI0_SOF 20 +#define CMDQ_EVENT_DISP_RSZ_SOF 22 +#define CMDQ_EVENT_MDP_AAL_SOF 23 +#define CMDQ_EVENT_MDP_CCORR_SOF 24 +#define CMDQ_EVENT_DISP_DBI_SOF 25 +#define CMDQ_EVENT_DISP_RDMA0_EOF 26 +#define CMDQ_EVENT_DISP_RDMA1_EOF 27 +#define CMDQ_EVENT_MDP_RDMA0_EOF 28 +#define CMDQ_EVENT_MDP_RSZ0_EOF 30 +#define CMDQ_EVENT_MDP_RSZ1_EOF 31 +#define CMDQ_EVENT_MDP_TDSHP_EOF 32 +#define CMDQ_EVENT_MDP_WROT0_EOF 33 +#define CMDQ_EVENT_MDP_WDMA0_EOF 34 +#define CMDQ_EVENT_DISP_OVL0_EOF 35 +#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36 +#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37 +#define CMDQ_EVENT_DISP_WDMA0_EOF 38 +#define CMDQ_EVENT_DISP_COLOR0_EOF 39 +#define CMDQ_EVENT_DISP_CCORR0_EOF 40 +#define CMDQ_EVENT_DISP_AAL0_EOF 41 +#define CMDQ_EVENT_DISP_GAMMA0_EOF 42 +#define CMDQ_EVENT_DISP_DITHER0_EOF 43 +#define CMDQ_EVENT_DSI0_EOF 44 +#define CMDQ_EVENT_DPI0_EOF 45 +#define CMDQ_EVENT_DISP_RSZ_EOF 47 +#define CMDQ_EVENT_MDP_AAL_EOF 48 +#define CMDQ_EVENT_MDP_CCORR_EOF 49 +#define CMDQ_EVENT_DBI_EOF 50 +#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130 +#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131 +#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132 +#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133 +#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134 +#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135 +#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136 +#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137 +#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138 +#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139 +#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140 +#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141 +#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142 +#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143 +#define CMDQ_EVENT_DSI0_TE_EVENT 144 +#define CMDQ_EVENT_DSI0_IRQ_EVENT 145 +#define CMDQ_EVENT_DSI0_DONE_EVENT 146 +#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150 +#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151 +#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152 +#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154 +#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155 +#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156 +#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275 +#define CMDQ_EVENT_AMD_FRAME_DONE 276 +#define CMDQ_EVENT_DVE_DONE 277 +#define CMDQ_EVENT_WMFE_DONE 278 +#define CMDQ_EVENT_RSC_DONE 279 +#define CMDQ_EVENT_MFB_DONE 280 +#define CMDQ_EVENT_WPE_A_DONE 281 +#define CMDQ_EVENT_SPE_B_DONE 282 +#define CMDQ_EVENT_OCC_DONE 283 +#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289 +#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290 +#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291 +#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292 +#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293 +#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 +#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 +#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323 +#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324 +#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325 +#define CMDQ_EVENT_TSF_DONE 326 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334 +#define CMDQ_EVENT_IPU_CORE0_DONE0 353 +#define CMDQ_EVENT_IPU_CORE0_DONE1 354 +#define CMDQ_EVENT_IPU_CORE0_DONE2 355 +#define CMDQ_EVENT_IPU_CORE0_DONE3 356 +#define CMDQ_EVENT_IPU_CORE1_DONE0 385 +#define CMDQ_EVENT_IPU_CORE1_DONE1 386 +#define CMDQ_EVENT_IPU_CORE1_DONE2 387 +#define CMDQ_EVENT_IPU_CORE1_DONE3 388 + +#endif From patchwork Thu May 16 09:02:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 1100422 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 454QS64XjQz9sBK for ; Thu, 16 May 2019 19:03:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726503AbfEPJC5 (ORCPT ); Thu, 16 May 2019 05:02:57 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:2422 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727176AbfEPJCu (ORCPT ); Thu, 16 May 2019 05:02:50 -0400 X-UUID: daf842882f6c4d03a417a182f73ed000-20190516 X-UUID: daf842882f6c4d03a417a182f73ed000-20190516 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 153919159; Thu, 16 May 2019 17:02:29 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:02:27 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:02:27 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU CC: Daniel Kurtz , Sascha Hauer , , , , , , Sascha Hauer , Philipp Zabel , Nicolas Boichat , YT Shen , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Houlong Wei , , Bibby Hsieh Subject: [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property Date: Thu, 16 May 2019 17:02:15 +0800 Message-ID: <20190516090224.59070-4-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190516090224.59070-1-bibby.hsieh@mediatek.com> References: <20190516090224.59070-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 133ABA43BC3171D96E19DE5D7CE24F57DF595CB91A101F3EBF67AE96D240CE432000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org tcmdq driver provide a function that get the relationship of sub system number from device node for client. add specification for #subsys-cells, mediatek,gce-subsys. Signed-off-by: Bibby Hsieh --- .../devicetree/bindings/mailbox/mtk-gce.txt | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 1f7f8f2a3f49..dceab63ccd06 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -21,11 +21,19 @@ Required properties: priority: Priority of GCE thread. atomic_exec: GCE processing continuous packets of commands in atomic way. +- #subsys-cells: Should be 3. + <&phandle subsys_number start_offset size> + phandle: Label name of a gce node. + subsys_number: specify the sub-system id which is corresponding + to the register address. + start_offset: the start offset of register address that GCE can access. + size: the total size of register address that GCE can access. Required properties for a client device: - mboxes: Client use mailbox to communicate with GCE, it should have this property and list of phandle, mailbox specifiers. -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding +Optional properties for a client device: +- mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding to the register address. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' @@ -40,6 +48,7 @@ Example: clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; #mbox-cells = <3>; + #subsys-cells = <3>; }; Example for a client device: @@ -48,9 +57,9 @@ Example for a client device: compatible = "mediatek,mt8173-mmsys"; mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; - mediatek,gce-subsys = ; mutex-event-eof = ; - + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, + <&gce SUBSYS_1401XXXX 0x2000 0x100>; ... }; From patchwork Thu May 16 09:02:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 1100425 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 454QSW0Qk4z9sBp for ; Thu, 16 May 2019 19:03:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727128AbfEPJCn (ORCPT ); Thu, 16 May 2019 05:02:43 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16135 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726799AbfEPJCn (ORCPT ); Thu, 16 May 2019 05:02:43 -0400 X-UUID: 0ff615d77074456d8ee8f9ec5c460fab-20190516 X-UUID: 0ff615d77074456d8ee8f9ec5c460fab-20190516 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 365224691; Thu, 16 May 2019 17:02:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:02:27 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:02:27 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU CC: Daniel Kurtz , Sascha Hauer , , , , , , Sascha Hauer , Philipp Zabel , Nicolas Boichat , YT Shen , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Houlong Wei , , Bibby Hsieh Subject: [PATCH v6 04/12] dt-binding: gce: add binding for gce event property Date: Thu, 16 May 2019 17:02:16 +0800 Message-ID: <20190516090224.59070-5-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190516090224.59070-1-bibby.hsieh@mediatek.com> References: <20190516090224.59070-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Client hardware would send event to GCE hardware, mediatek,gce-event-names and mediatek,gce-events can be used to present the event. Signed-off-by: Bibby Hsieh --- Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index dceab63ccd06..265bb58da7bd 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -35,6 +35,8 @@ Required properties for a client device: Optional properties for a client device: - mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding to the register address. +- mediatek,gce-events: u32, the event number defined in + 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. @@ -57,8 +59,8 @@ Example for a client device: compatible = "mediatek,mt8173-mmsys"; mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; - mutex-event-eof = ; + mediatek,gce-events = , + ; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, <&gce SUBSYS_1401XXXX 0x2000 0x100>; ...