From patchwork Tue Apr 16 13:50:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086329 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6HN2z6jz9s3l for ; Tue, 16 Apr 2019 23:52:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0A6EAC21C6A; Tue, 16 Apr 2019 13:51:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 42380C21DD3; Tue, 16 Apr 2019 13:51:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7EA34C21C2F; Tue, 16 Apr 2019 13:51:15 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134]) by lists.denx.de (Postfix) with ESMTPS id D3F6CC21C50 for ; Tue, 16 Apr 2019 13:51:14 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.158]) by lucky1.263xmail.com (Postfix) with ESMTP id CC7202FE4B; Tue, 16 Apr 2019 21:51:10 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 0 X-SKE-CHECKED: 0 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P7953T140108858644224S1555422667931136_; Tue, 16 Apr 2019 21:51:11 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:50:53 +0800 Message-Id: <20190416135102.26667-2-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 01/10] pinctrl: rockchip: Add pull-pin-default param and remove unused param X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - Add some commit message drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index b84b079064..77ac981c40 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -509,9 +509,8 @@ static const struct pinconf_param rockchip_conf_params[] = { { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, - { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, - { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, }; From patchwork Tue Apr 16 13:50:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086331 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6Jw5nc2z9s3l for ; Tue, 16 Apr 2019 23:53:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3BED2C21E13; Tue, 16 Apr 2019 13:52:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 274EDC21E70; Tue, 16 Apr 2019 13:51:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B8C43C21C2F; Tue, 16 Apr 2019 13:51:22 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130]) by lists.denx.de (Postfix) with ESMTPS id 3D2E3C21E29 for ; Tue, 16 Apr 2019 13:51:19 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.158]) by lucky1.263xmail.com (Postfix) with ESMTP id 7A08257B74; Tue, 16 Apr 2019 21:51:13 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 0 X-SKE-CHECKED: 0 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P7953T140108858644224S1555422667931136_; Tue, 16 Apr 2019 21:51:13 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <7ec62331087f637ff77e7d3962907dd3> X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:50:54 +0800 Message-Id: <20190416135102.26667-3-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 02/10] pinctrl: rockchip: Remove redundant spaces X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some files have the redundant spaces, remove them. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++++++------ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++++++------ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18 ++++++++--------- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 20 +++++++++---------- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 24 +++++++++++------------ drivers/pinctrl/rockchip/pinctrl-rk3368.c | 16 +++++++-------- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 24 +++++++++++------------ 7 files changed, 63 insertions(+), 63 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 2729b03443..2a651cd9b8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -36,12 +36,12 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3036_pin_ctrl = { - .pin_banks = rk3036_pin_banks, - .nr_banks = ARRAY_SIZE(rk3036_pin_banks), - .label = "RK3036-GPIO", - .type = RK3036, - .grf_mux_offset = 0xa8, - .pull_calc_reg = rk3036_calc_pull_reg_and_bit, + .pin_banks = rk3036_pin_banks, + .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .label = "RK3036-GPIO", + .type = RK3036, + .grf_mux_offset = 0xa8, + .pull_calc_reg = rk3036_calc_pull_reg_and_bit, }; static const struct udevice_id rk3036_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 5ed9aec938..7cc52c0075 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -55,12 +55,12 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3188_pin_ctrl = { - .pin_banks = rk3188_pin_banks, - .nr_banks = ARRAY_SIZE(rk3188_pin_banks), - .label = "RK3188-GPIO", - .type = RK3188, - .grf_mux_offset = 0x60, - .pull_calc_reg = rk3188_calc_pull_reg_and_bit, + .pin_banks = rk3188_pin_banks, + .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .label = "RK3188-GPIO", + .type = RK3188, + .grf_mux_offset = 0x60, + .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; static const struct udevice_id rk3188_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index d2a6cd7055..d67b48a06a 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -183,15 +183,15 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3228_pin_ctrl = { - .pin_banks = rk3228_pin_banks, - .nr_banks = ARRAY_SIZE(rk3228_pin_banks), - .label = "RK3228-GPIO", - .type = RK3288, - .grf_mux_offset = 0x0, - .iomux_routes = rk3228_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), - .pull_calc_reg = rk3228_calc_pull_reg_and_bit, - .drv_calc_reg = rk3228_calc_drv_reg_and_bit, + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .iomux_routes = rk3228_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, }; static const struct udevice_id rk3228_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 60585f3208..3648f37207 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -124,16 +124,16 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3288_pin_ctrl = { - .pin_banks = rk3288_pin_banks, - .nr_banks = ARRAY_SIZE(rk3288_pin_banks), - .label = "RK3288-GPIO", - .type = RK3288, - .grf_mux_offset = 0x0, - .pmu_mux_offset = 0x84, - .iomux_routes = rk3288_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), - .pull_calc_reg = rk3288_calc_pull_reg_and_bit, - .drv_calc_reg = rk3288_calc_drv_reg_and_bit, + .pin_banks = rk3288_pin_banks, + .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .label = "RK3288-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x84, + .iomux_routes = rk3288_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), + .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; static const struct udevice_id rk3288_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index f1b3d10dbe..ab634c1123 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -192,18 +192,18 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3328_pin_ctrl = { - .pin_banks = rk3328_pin_banks, - .nr_banks = ARRAY_SIZE(rk3328_pin_banks), - .label = "RK3328-GPIO", - .type = RK3288, - .grf_mux_offset = 0x0, - .iomux_recalced = rk3328_mux_recalced_data, - .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), - .iomux_routes = rk3328_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), - .pull_calc_reg = rk3328_calc_pull_reg_and_bit, - .drv_calc_reg = rk3328_calc_drv_reg_and_bit, - .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, + .pin_banks = rk3328_pin_banks, + .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .label = "RK3328-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .iomux_recalced = rk3328_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), + .iomux_routes = rk3328_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), + .pull_calc_reg = rk3328_calc_pull_reg_and_bit, + .drv_calc_reg = rk3328_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; static const struct udevice_id rk3328_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index f5cd6ff24e..8bdaf5e4d2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -85,14 +85,14 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3368_pin_ctrl = { - .pin_banks = rk3368_pin_banks, - .nr_banks = ARRAY_SIZE(rk3368_pin_banks), - .label = "RK3368-GPIO", - .type = RK3368, - .grf_mux_offset = 0x0, - .pmu_mux_offset = 0x0, - .pull_calc_reg = rk3368_calc_pull_reg_and_bit, - .drv_calc_reg = rk3368_calc_drv_reg_and_bit, + .pin_banks = rk3368_pin_banks, + .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .label = "RK3368-GPIO", + .type = RK3368, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .drv_calc_reg = rk3368_calc_drv_reg_and_bit, }; static const struct udevice_id rk3368_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index c5aab647a5..06276b14ef 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -158,18 +158,18 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3399_pin_ctrl = { - .pin_banks = rk3399_pin_banks, - .nr_banks = ARRAY_SIZE(rk3399_pin_banks), - .label = "RK3399-GPIO", - .type = RK3399, - .grf_mux_offset = 0xe000, - .pmu_mux_offset = 0x0, - .grf_drv_offset = 0xe100, - .pmu_drv_offset = 0x80, - .iomux_routes = rk3399_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), - .pull_calc_reg = rk3399_calc_pull_reg_and_bit, - .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + .pin_banks = rk3399_pin_banks, + .nr_banks = ARRAY_SIZE(rk3399_pin_banks), + .label = "RK3399-GPIO", + .type = RK3399, + .grf_mux_offset = 0xe000, + .pmu_mux_offset = 0x0, + .grf_drv_offset = 0xe100, + .pmu_drv_offset = 0x80, + .iomux_routes = rk3399_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), + .pull_calc_reg = rk3399_calc_pull_reg_and_bit, + .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; static const struct udevice_id rk3399_pinctrl_ids[] = { From patchwork Tue Apr 16 13:50:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086330 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6J40vdqz9s3l for ; Tue, 16 Apr 2019 23:52:36 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 609EDC21E29; Tue, 16 Apr 2019 13:51:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AF036C21E52; Tue, 16 Apr 2019 13:51:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 167D7C21DF9; Tue, 16 Apr 2019 13:51:23 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130]) by lists.denx.de (Postfix) with ESMTPS id 9E20FC21DFA for ; Tue, 16 Apr 2019 13:51:19 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.158]) by lucky1.263xmail.com (Postfix) with ESMTP id 5909757B5B; Tue, 16 Apr 2019 21:51:15 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 0 X-SKE-CHECKED: 0 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P7953T140108858644224S1555422667931136_; Tue, 16 Apr 2019 21:51:15 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <7d7ec79cb7f9e5096c29127bc0a5be03> X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:50:55 +0800 Message-Id: <20190416135102.26667-4-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 03/10] pinctrl: rockchip: Split the common set_mux() into per Soc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk3036.c | 25 +++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 +++++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 25 +++++++++++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 34 +++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++++++++++++++- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 37 +++++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3368.c | 25 +++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 34 +++++++++++++++ .../pinctrl/rockchip/pinctrl-rockchip-core.c | 41 +++++-------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 8 ++++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 28 +++++++++++++ 11 files changed, 297 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 2a651cd9b8..8969aea2e3 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -11,6 +11,30 @@ #include "pinctrl-rockchip.h" +static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3036_PULL_OFFSET 0x118 #define RK3036_PULL_PINS_PER_REG 16 #define RK3036_PULL_BANK_STRIDE 8 @@ -41,6 +65,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .label = "RK3036-GPIO", .type = RK3036, .grf_mux_offset = 0xa8, + .set_mux = rk3036_set_mux, .pull_calc_reg = rk3036_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 43a6c173a0..de203334c7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -98,6 +98,42 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { }, }; +static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3128_PULL_OFFSET 0x118 #define RK3128_PULL_PINS_PER_REG 16 #define RK3128_PULL_BANK_STRIDE 8 @@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), .iomux_routes = rk3128_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), + .set_mux = rk3128_set_mux, .pull_calc_reg = rk3128_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 7cc52c0075..617ae28ac8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -11,6 +11,30 @@ #include "pinctrl-rockchip.h" +static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3188_PULL_OFFSET 0x164 #define RK3188_PULL_PMU_OFFSET 0x64 @@ -60,6 +84,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .label = "RK3188-GPIO", .type = RK3188, .grf_mux_offset = 0x60, + .set_mux = rk3188_set_mux, .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index d67b48a06a..442c40ce0b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -141,6 +141,39 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = { }, }; +static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3228_PULL_OFFSET 0x100 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, @@ -190,6 +223,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .grf_mux_offset = 0x0, .iomux_routes = rk3228_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), + .set_mux = rk3228_set_mux, .pull_calc_reg = rk3228_calc_pull_reg_and_bit, .drv_calc_reg = rk3228_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 3648f37207..1fa601d954 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "pinctrl-rockchip.h" @@ -29,6 +28,39 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = { }, }; +static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3288_PULL_OFFSET 0x140 #define RK3288_PULL_PMU_OFFSET 0x64 @@ -132,6 +164,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pmu_mux_offset = 0x84, .iomux_routes = rk3288_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), + .set_mux = rk3288_set_mux, .pull_calc_reg = rk3288_calc_pull_reg_and_bit, .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index ab634c1123..de21fba69c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -121,6 +121,42 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { }, }; +static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3328_PULL_OFFSET 0x100 static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, @@ -201,6 +237,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), .iomux_routes = rk3328_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), + .set_mux = rk3328_set_mux, .pull_calc_reg = rk3328_calc_pull_reg_and_bit, .drv_calc_reg = rk3328_calc_drv_reg_and_bit, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 8bdaf5e4d2..c1f692a1cf 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -11,6 +11,30 @@ #include "pinctrl-rockchip.h" +static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -91,6 +115,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .type = RK3368, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, + .set_mux = rk3368_set_mux, .pull_calc_reg = rk3368_calc_pull_reg_and_bit, .drv_calc_reg = rk3368_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 06276b14ef..9e8dc2ef82 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -50,6 +50,39 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { }, }; +static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3399_PULL_GRF_OFFSET 0xe040 #define RK3399_PULL_PMU_OFFSET 0x40 @@ -168,6 +201,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pmu_drv_offset = 0x80, .iomux_routes = rk3399_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), + .set_mux = rk3399_set_mux, .pull_calc_reg = rk3399_calc_pull_reg_and_bit, .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 77ac981c40..355fa6c8ad 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -35,8 +35,8 @@ static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) return 0; } -static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, - int *reg, u8 *bit, int *mask) +void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + int *reg, u8 *bit, int *mask) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; @@ -58,8 +58,8 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; } -static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value) +bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; @@ -82,7 +82,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, return true; } -static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) +int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) { int offset = 0; @@ -193,11 +193,9 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; int iomux_num = (pin / 8); - struct regmap *regmap; - int reg, ret, mask, mux_type; - u8 bit; - u32 data, route_reg, route_val; + int ret; ret = rockchip_verify_mux(bank, pin, mux); if (ret < 0) @@ -208,29 +206,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); - regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) - ? priv->regmap_pmu : priv->regmap_base; - - /* get basic quadrupel of mux registers and the correct reg inside */ - mux_type = bank->iomux[iomux_num].type; - reg = bank->iomux[iomux_num].offset; - reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); - - if (bank->recalced_mask & BIT(pin)) - rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); - - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } + if (!ctrl->set_mux) + return -ENOTSUPP; - data = (mask << (bit + 16)); - data |= (mux & mask) << bit; - ret = regmap_write(regmap, reg, data); + ret = ctrl->set_mux(bank, pin, mux); return ret; } diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index bc809630c1..db89b49238 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -277,6 +277,9 @@ struct rockchip_pin_ctrl { struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; + int (*set_mux)(struct rockchip_pin_bank *bank, + int pin, int mux); + void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -298,5 +301,10 @@ struct rockchip_pinctrl_priv { extern const struct pinctrl_ops rockchip_pinctrl_ops; int rockchip_pinctrl_probe(struct udevice *dev); +void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + int *reg, u8 *bit, int *mask); +bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value); +int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index f4a09a6824..c28b504634 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -75,6 +75,33 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { }, }; +static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 @@ -177,6 +204,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pmu_mux_offset = 0x0, .iomux_recalced = rv1108_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), + .set_mux = rv1108_set_mux, .pull_calc_reg = rv1108_calc_pull_reg_and_bit, .drv_calc_reg = rv1108_calc_drv_reg_and_bit, .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, From patchwork Tue Apr 16 13:50:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086332 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6KC0Yqbz9s4Y for ; Tue, 16 Apr 2019 23:53:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A1D24C21E68; Tue, 16 Apr 2019 13:52:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C1036C21E6A; Tue, 16 Apr 2019 13:51:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E1FDC21E1B; Tue, 16 Apr 2019 13:51:24 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.199]) by lists.denx.de (Postfix) with ESMTPS id F4040C21E08 for ; Tue, 16 Apr 2019 13:51:20 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.158]) by regular1.263xmail.com (Postfix) with ESMTP id CD51A39F; Tue, 16 Apr 2019 21:51:17 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P7953T140108858644224S1555422667931136_; Tue, 16 Apr 2019 21:51:16 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <07410fdc9dd82f11f488cbcbbb4cf6e5> X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:50:56 +0800 Message-Id: <20190416135102.26667-5-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 04/10] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - Add some comment drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 1fa601d954..5040cd8f48 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -54,7 +54,15 @@ static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) } } - data = (mask << (bit + 16)); + /* bank0 is special, there are no higher 16 bit writing bits. */ + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(mask << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = (mask << (bit + 16)); + } + data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); From patchwork Tue Apr 16 13:55:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086333 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6Mk65GLz9s4Y for ; Tue, 16 Apr 2019 23:55:46 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 7E0FDC21E16; Tue, 16 Apr 2019 13:55:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C5E0C21C6A; Tue, 16 Apr 2019 13:55:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4887AC21C6A; Tue, 16 Apr 2019 13:55:39 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.197]) by lists.denx.de (Postfix) with ESMTPS id 21C5CC21C50 for ; Tue, 16 Apr 2019 13:55:38 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.171]) by regular1.263xmail.com (Postfix) with ESMTP id A46B75EA; Tue, 16 Apr 2019 21:55:34 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P18934T140364264490752S1555422931915148_; Tue, 16 Apr 2019 21:55:33 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <77f7dc3d69ed3c137546c8e641eb0898> X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:55:26 +0800 Message-Id: <20190416135526.26947-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 05/10] pinctrl: rockchip: Split the common set_drive() func into per Soc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 ++++- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++++-- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 26 ++++- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 36 +++++-- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 75 ++++++++++++++- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 95 ++++--------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 6 +- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 26 ++++- 8 files changed, 224 insertions(+), 100 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 442c40ce0b..10200ff3c8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -208,6 +208,29 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } +static int rk3228_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3228_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + return ret; +} + static struct rockchip_pin_bank rk3228_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -225,7 +248,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), .set_mux = rk3228_set_mux, .pull_calc_reg = rk3228_calc_pull_reg_and_bit, - .drv_calc_reg = rk3228_calc_drv_reg_and_bit, + .set_drive = rk3228_set_drive, }; static const struct udevice_id rk3228_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 5040cd8f48..6ae9f1c76e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -113,10 +113,6 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3288_DRV_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3288_DRV_GRF_OFFSET; @@ -124,11 +120,34 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + } + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} - *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +static int rk3288_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + return ret; } static struct rockchip_pin_bank rk3288_pin_banks[] = { @@ -174,7 +193,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), .set_mux = rk3288_set_mux, .pull_calc_reg = rk3288_calc_pull_reg_and_bit, - .drv_calc_reg = rk3288_calc_drv_reg_and_bit, + .set_drive = rk3288_set_drive, }; static const struct udevice_id rk3288_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index de21fba69c..0ad5669d26 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -191,6 +191,30 @@ static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } +static int rk3328_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3328_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3328_SCHMITT_BITS_PER_PIN 1 #define RK3328_SCHMITT_PINS_PER_REG 16 #define RK3328_SCHMITT_BANK_STRIDE 8 @@ -239,7 +263,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), .set_mux = rk3328_set_mux, .pull_calc_reg = rk3328_calc_pull_reg_and_bit, - .drv_calc_reg = rk3328_calc_drv_reg_and_bit, + .set_drive = rk3328_set_drive, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index c1f692a1cf..40cc846fa8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -79,10 +79,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3368_DRV_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3368_DRV_GRF_OFFSET; @@ -90,11 +86,35 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + } + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} - *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +static int rk3368_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3368_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } static struct rockchip_pin_bank rk3368_pin_banks[] = { @@ -117,7 +137,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pmu_mux_offset = 0x0, .set_mux = rk3368_set_mux, .pull_calc_reg = rk3368_calc_pull_reg_and_bit, - .drv_calc_reg = rk3368_calc_drv_reg_and_bit, + .set_drive = rk3368_set_drive, }; static const struct udevice_id rk3368_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 9e8dc2ef82..82c8feeb7b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -137,6 +137,79 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit = (pin_num % 8) * 2; } +static int rk3399_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data, rmask_bits, temp; + u8 bit; + int drv_type = bank->drv[pin_num / 8].drv_type; + + rk3399_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(drv_type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + switch (drv_type) { + case DRV_TYPE_IO_1V8_3V0_AUTO: + case DRV_TYPE_IO_3V3_ONLY: + rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; + switch (bit) { + case 0 ... 12: + /* regular case, nothing to do */ + break; + case 15: + /* + * drive-strength offset is special, as it is spread + * over 2 registers, the bit data[15] contains bit 0 + * of the value while temp[1:0] contains bits 2 and 1 + */ + data = (ret & 0x1) << 15; + temp = (ret >> 0x1) & 0x3; + + data |= BIT(31); + ret = regmap_write(regmap, reg, data); + if (ret) + return ret; + + temp |= (0x3 << 16); + reg += 0x4; + ret = regmap_write(regmap, reg, temp); + + return ret; + case 18 ... 21: + /* setting fully enclosed in the second register */ + reg += 4; + bit -= 16; + break; + default: + debug("unsupported bit: %d for pinctrl drive type: %d\n", + bit, drv_type); + return -EINVAL; + } + break; + case DRV_TYPE_IO_DEFAULT: + case DRV_TYPE_IO_1V8_OR_3V0: + case DRV_TYPE_IO_1V8_ONLY: + rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; + break; + default: + debug("unsupported pinctrl drive type: %d\n", + drv_type); + return -EINVAL; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3399_pin_banks[] = { PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, @@ -203,7 +276,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), .set_mux = rk3399_set_mux, .pull_calc_reg = rk3399_calc_pull_reg_and_bit, - .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + .set_drive = rk3399_set_drive, }; static const struct udevice_id rk3399_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 355fa6c8ad..439e8ba1b5 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -222,93 +222,37 @@ static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { { 4, 7, 10, 13, 16, 19, 22, 26 } }; -static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, - int pin_num, int strength) +int rockchip_translate_drive_value(int type, int strength) { - struct rockchip_pinctrl_priv *priv = bank->priv; - struct rockchip_pin_ctrl *ctrl = priv->ctrl; - struct regmap *regmap; - int reg, ret, i; - u32 data, rmask_bits, temp; - u8 bit; - int drv_type = bank->drv[pin_num / 8].drv_type; - - debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, - pin_num, strength); - - ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); + int i, ret; ret = -EINVAL; - for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { - if (rockchip_perpin_drv_list[drv_type][i] == strength) { + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) { + if (rockchip_perpin_drv_list[type][i] == strength) { ret = i; break; - } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { - ret = rockchip_perpin_drv_list[drv_type][i]; + } else if (rockchip_perpin_drv_list[type][i] < 0) { + ret = rockchip_perpin_drv_list[type][i]; break; } } - if (ret < 0) { - debug("unsupported driver strength %d\n", strength); - return ret; - } - - switch (drv_type) { - case DRV_TYPE_IO_1V8_3V0_AUTO: - case DRV_TYPE_IO_3V3_ONLY: - rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; - switch (bit) { - case 0 ... 12: - /* regular case, nothing to do */ - break; - case 15: - /* - * drive-strength offset is special, as it is spread - * over 2 registers, the bit data[15] contains bit 0 - * of the value while temp[1:0] contains bits 2 and 1 - */ - data = (ret & 0x1) << 15; - temp = (ret >> 0x1) & 0x3; - - data |= BIT(31); - ret = regmap_write(regmap, reg, data); - if (ret) - return ret; + return ret; +} - temp |= (0x3 << 16); - reg += 0x4; - ret = regmap_write(regmap, reg, temp); +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; - return ret; - case 18 ... 21: - /* setting fully enclosed in the second register */ - reg += 4; - bit -= 16; - break; - default: - debug("unsupported bit: %d for pinctrl drive type: %d\n", - bit, drv_type); - return -EINVAL; - } - break; - case DRV_TYPE_IO_DEFAULT: - case DRV_TYPE_IO_1V8_OR_3V0: - case DRV_TYPE_IO_1V8_ONLY: - rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; - break; - default: - debug("unsupported pinctrl drive type: %d\n", - drv_type); - return -EINVAL; - } + debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, + pin_num, strength); - /* enable the write to the equivalent lower bits */ - data = ((1 << rmask_bits) - 1) << (bit + 16); - data |= (ret << bit); + if (!ctrl->set_drive) + return -ENOTSUPP; - ret = regmap_write(regmap, reg, data); - return ret; + return ctrl->set_drive(bank, pin_num, strength); } static int rockchip_pull_list[PULL_TYPE_MAX][4] = { @@ -459,9 +403,6 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, break; case PIN_CONFIG_DRIVE_STRENGTH: - if (!ctrl->drv_calc_reg) - return -ENOTSUPP; - rc = rockchip_set_drive_perpin(bank, pin, arg); if (rc < 0) return rc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index db89b49238..2ef24dce6c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -283,9 +283,8 @@ struct rockchip_pin_ctrl { void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); - void (*drv_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); + int (*set_drive)(struct rockchip_pin_bank *bank, + int pin_num, int strength); int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -306,5 +305,6 @@ void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *reg, u32 *value); int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); +int rockchip_translate_drive_value(int type, int strength); #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index c28b504634..1a150ff0f1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -155,6 +155,30 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } +static int rv1108_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rv1108_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + return ret; +} + #define RV1108_SCHMITT_PMU_OFFSET 0x30 #define RV1108_SCHMITT_GRF_OFFSET 0x388 #define RV1108_SCHMITT_BANK_STRIDE 8 @@ -206,7 +230,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), .set_mux = rv1108_set_mux, .pull_calc_reg = rv1108_calc_pull_reg_and_bit, - .drv_calc_reg = rv1108_calc_drv_reg_and_bit, + .set_drive = rv1108_set_drive, .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, }; From patchwork Tue Apr 16 13:56:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086334 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6Nw155wz9s55 for ; Tue, 16 Apr 2019 23:56:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D1DECC21E12; Tue, 16 Apr 2019 13:56:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A3131C21C6A; Tue, 16 Apr 2019 13:56:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C48D6C21C6A; Tue, 16 Apr 2019 13:56:39 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.201]) by lists.denx.de (Postfix) with ESMTPS id 51AD5C21C50 for ; Tue, 16 Apr 2019 13:56:39 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.229]) by regular1.263xmail.com (Postfix) with ESMTP id 90A0722B; Tue, 16 Apr 2019 21:56:37 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P18891T139806387517184S1555422995957789_; Tue, 16 Apr 2019 21:56:37 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:56:34 +0800 Message-Id: <20190416135634.27041-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 06/10] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strength X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - Add some comment drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 6ae9f1c76e..d1b9aeb3d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -143,8 +143,15 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, return ret; } - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + /* bank0 is special, there are no higher 16 bit writing bits. */ + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); return ret; From patchwork Tue Apr 16 13:57:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086335 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6PZ07WPz9s55 for ; Tue, 16 Apr 2019 23:57:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3BE8FC21DC1; Tue, 16 Apr 2019 13:57:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 563A2C21DD3; Tue, 16 Apr 2019 13:57:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5D2E0C21DD3; Tue, 16 Apr 2019 13:57:13 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) by lists.denx.de (Postfix) with ESMTPS id 6A1B7C21DC1 for ; Tue, 16 Apr 2019 13:57:12 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.84]) by lucky1.263xmail.com (Postfix) with ESMTP id 9A99A572FA; Tue, 16 Apr 2019 21:57:08 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 0 X-SKE-CHECKED: 0 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P7849T140068974999296S1555423026440287_; Tue, 16 Apr 2019 21:57:08 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:57:05 +0800 Message-Id: <20190416135705.27106-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 07/10] pinctrl: rockchip: Split the common set_pull() func into per Soc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 ++++- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 ++++- drivers/pinctrl/rockchip/pinctrl-rk3188.c | 29 +++++- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 29 +++++- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 40 ++++++-- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 29 +++++- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 40 ++++++-- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 40 ++++++-- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 97 ++++--------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 7 +- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 30 +++++- 11 files changed, 275 insertions(+), 112 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 8969aea2e3..498b633f22 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -53,6 +53,27 @@ static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit = pin_num % RK3036_PULL_PINS_PER_REG; }; +static int rk3036_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return -ENOTSUPP; + + rk3036_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3036_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -66,7 +87,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .type = RK3036, .grf_mux_offset = 0xa8, .set_mux = rk3036_set_mux, - .pull_calc_reg = rk3036_calc_pull_reg_and_bit, + .set_pull = rk3036_set_pull, }; static const struct udevice_id rk3036_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index de203334c7..104b76c19e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -152,6 +152,27 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit = pin_num % RK3128_PULL_PINS_PER_REG; } +static int rk3128_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return -ENOTSUPP; + + rk3128_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3128_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -170,7 +191,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .iomux_routes = rk3128_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), .set_mux = rk3128_set_mux, - .pull_calc_reg = rk3128_calc_pull_reg_and_bit, + .set_pull = rk3128_set_pull, }; static const struct udevice_id rk3128_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 617ae28ac8..e09c799e72 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -71,6 +71,33 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, } } +static int rk3188_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3188_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), PIN_BANK(1, 32, "gpio1"), @@ -85,7 +112,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .type = RK3188, .grf_mux_offset = 0x60, .set_mux = rk3188_set_mux, - .pull_calc_reg = rk3188_calc_pull_reg_and_bit, + .set_pull = rk3188_set_pull, }; static const struct udevice_id rk3188_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 10200ff3c8..b69d9795bb 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -191,6 +191,33 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } +static int rk3228_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3228_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3228_DRV_GRF_OFFSET 0x200 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, @@ -247,7 +274,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .iomux_routes = rk3228_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), .set_mux = rk3228_set_mux, - .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .set_pull = rk3228_set_pull, .set_drive = rk3228_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index d1b9aeb3d9..9192aa3949 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -82,10 +82,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3288_PULL_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3288_PULL_OFFSET; @@ -93,11 +89,39 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +static int rk3288_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } #define RK3288_DRV_PMU_OFFSET 0x70 @@ -199,7 +223,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .iomux_routes = rk3288_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), .set_mux = rk3288_set_mux, - .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .set_pull = rk3288_set_pull, .set_drive = rk3288_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 0ad5669d26..7ac5c0226e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -174,6 +174,33 @@ static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } +static int rk3328_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3328_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3328_DRV_GRF_OFFSET 0x200 static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, @@ -262,7 +289,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .iomux_routes = rk3328_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), .set_mux = rk3328_set_mux, - .pull_calc_reg = rk3328_calc_pull_reg_and_bit, + .set_pull = rk3328_set_pull, .set_drive = rk3328_set_drive, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 40cc846fa8..06de27aa30 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -48,10 +48,6 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3368_PULL_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3368_PULL_GRF_OFFSET; @@ -59,11 +55,39 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +static int rk3368_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3368_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } #define RK3368_DRV_PMU_OFFSET 0x20 @@ -136,7 +160,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, .set_mux = rk3368_set_mux, - .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .set_pull = rk3368_set_pull, .set_drive = rk3368_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 82c8feeb7b..68bb492a6b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -98,10 +98,6 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *reg = RK3399_PULL_PMU_OFFSET; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3399_PULL_GRF_OFFSET; @@ -109,11 +105,39 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 3rd bank */ *reg -= 0x20; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +static int rk3399_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3399_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, @@ -275,7 +299,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .iomux_routes = rk3399_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), .set_mux = rk3399_set_mux, - .pull_calc_reg = rk3399_calc_pull_reg_and_bit, + .set_pull = rk3399_set_pull, .set_drive = rk3399_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 439e8ba1b5..b3379a0d3f 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -270,61 +270,35 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = { }, }; +int rockchip_translate_pull_value(int type, int pull) +{ + int i, ret; + + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]); + i++) { + if (rockchip_pull_list[type][i] == pull) { + ret = i; + break; + } + } + + return ret; +} + static int rockchip_set_pull(struct rockchip_pin_bank *bank, int pin_num, int pull) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; - struct regmap *regmap; - int reg, ret, i, pull_type; - u8 bit; - u32 data; debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); - ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); - - switch (ctrl->type) { - case RK3036: - case RK3128: - data = BIT(bit + 16); - if (pull == PIN_CONFIG_BIAS_DISABLE) - data |= BIT(bit); - ret = regmap_write(regmap, reg, data); - break; - case RV1108: - case RK3188: - case RK3288: - case RK3368: - case RK3399: - pull_type = bank->pull_type[pin_num / 8]; - ret = -EINVAL; - for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); - i++) { - if (rockchip_pull_list[pull_type][i] == pull) { - ret = i; - break; - } - } - - if (ret < 0) { - debug("unsupported pull setting %d\n", pull); - return ret; - } - - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - data |= (ret << bit); - - ret = regmap_write(regmap, reg, data); - break; - default: - debug("unsupported pinctrl type\n"); - return -EINVAL; - } + if (!ctrl->set_pull) + return -ENOTSUPP; - return ret; + return ctrl->set_pull(bank, pin_num, pull); } static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, @@ -350,28 +324,6 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, return regmap_write(regmap, reg, data); } -/* - * Pinconf_ops handling - */ -static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, - unsigned int pull) -{ - switch (ctrl->type) { - case RK3036: - case RK3128: - return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || - pull == PIN_CONFIG_BIAS_DISABLE); - case RV1108: - case RK3188: - case RK3288: - case RK3368: - case RK3399: - return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); - } - - return false; -} - /* set the pin config settings for a specified pin */ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, u32 pin, u32 param, u32 arg) @@ -382,21 +334,10 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - rc = rockchip_set_pull(bank, pin, param); - if (rc) - return rc; - break; - case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: case PIN_CONFIG_BIAS_BUS_HOLD: - if (!rockchip_pinconf_pull_valid(ctrl, param)) - return -ENOTSUPP; - - if (!arg) - return -EINVAL; - rc = rockchip_set_pull(bank, pin, param); if (rc) return rc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 2ef24dce6c..c21b79602c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -279,10 +279,8 @@ struct rockchip_pin_ctrl { int (*set_mux)(struct rockchip_pin_bank *bank, int pin, int mux); - - void (*pull_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); + int (*set_pull)(struct rockchip_pin_bank *bank, + int pin_num, int pull); int (*set_drive)(struct rockchip_pin_bank *bank, int pin_num, int strength); int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, @@ -306,5 +304,6 @@ bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *reg, u32 *value); int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); int rockchip_translate_drive_value(int type, int strength); +int rockchip_translate_pull_value(int type, int pull); #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 1a150ff0f1..6456483e36 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -128,6 +128,34 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } +static int rv1108_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rv1108_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RV1108_DRV_PMU_OFFSET 0x20 #define RV1108_DRV_GRF_OFFSET 0x210 @@ -229,7 +257,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .iomux_recalced = rv1108_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), .set_mux = rv1108_set_mux, - .pull_calc_reg = rv1108_calc_pull_reg_and_bit, + .set_pull = rv1108_set_pull, .set_drive = rv1108_set_drive, .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, }; From patchwork Tue Apr 16 13:57:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086336 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6QD1Bp0z9s3l for ; Tue, 16 Apr 2019 23:57:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C7881C21C6A; Tue, 16 Apr 2019 13:57:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 136E1C21DED; Tue, 16 Apr 2019 13:57:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4FCCCC21DC1; Tue, 16 Apr 2019 13:57:45 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.196]) by lists.denx.de (Postfix) with ESMTPS id DA3CCC21DF8 for ; Tue, 16 Apr 2019 13:57:44 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.12]) by regular1.263xmail.com (Postfix) with ESMTP id C0C26792; Tue, 16 Apr 2019 21:57:41 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P16374T140683648231168S1555423060028318_; Tue, 16 Apr 2019 21:57:41 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:57:28 +0800 Message-Id: <20190416135728.27163-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 08/10] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pull X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 9192aa3949..24af3597ec 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -116,8 +116,15 @@ static int rk3288_set_pull(struct rockchip_pin_bank *bank, return ret; } - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + /* bank0 is special, there are no higher 16 bit writing bits */ + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); From patchwork Tue Apr 16 13:57:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086337 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6Qt3gGWz9s55 for ; Tue, 16 Apr 2019 23:58:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 31653C21E29; Tue, 16 Apr 2019 13:58:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9083DC21E12; Tue, 16 Apr 2019 13:58:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D6472C21E4F; Tue, 16 Apr 2019 13:58:04 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id CB269C21E29 for ; Tue, 16 Apr 2019 13:58:00 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.235]) by lucky1.263xmail.com (Postfix) with ESMTP id 4A89956D9A; Tue, 16 Apr 2019 21:57:57 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 0 X-SKE-CHECKED: 0 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P26148T140233928587008S1555423075043994_; Tue, 16 Apr 2019 21:57:56 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:57:54 +0800 Message-Id: <20190416135754.27223-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 09/10] pinctrl: rockchip: Clean the unused type and label X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 12 ------------ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 2 -- 10 files changed, 30 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 498b633f22..28c905129b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -83,8 +83,6 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), - .label = "RK3036-GPIO", - .type = RK3036, .grf_mux_offset = 0xa8, .set_mux = rk3036_set_mux, .set_pull = rk3036_set_pull, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 104b76c19e..3eb4d952bb 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -183,8 +183,6 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), - .label = "RK3128-GPIO", - .type = RK3128, .grf_mux_offset = 0xa8, .iomux_recalced = rk3128_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index e09c799e72..043764fc92 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -108,8 +108,6 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), - .label = "RK3188-GPIO", - .type = RK3188, .grf_mux_offset = 0x60, .set_mux = rk3188_set_mux, .set_pull = rk3188_set_pull, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index b69d9795bb..c5e4fe30a7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -268,8 +268,6 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), - .label = "RK3228-GPIO", - .type = RK3288, .grf_mux_offset = 0x0, .iomux_routes = rk3228_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 24af3597ec..7ae147f304 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -223,8 +223,6 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), - .label = "RK3288-GPIO", - .type = RK3288, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x84, .iomux_routes = rk3288_mux_route_data, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 7ac5c0226e..d4d37af206 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -281,8 +281,6 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), - .label = "RK3328-GPIO", - .type = RK3288, .grf_mux_offset = 0x0, .iomux_recalced = rk3328_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 06de27aa30..6cb7bb45d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -155,8 +155,6 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), - .label = "RK3368-GPIO", - .type = RK3368, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, .set_mux = rk3368_set_mux, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 68bb492a6b..75634e9f4d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -290,8 +290,6 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), - .label = "RK3399-GPIO", - .type = RK3399, .grf_mux_offset = 0xe000, .pmu_mux_offset = 0x0, .grf_drv_offset = 0xe100, diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index c21b79602c..1c6fc2c5b2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -8,16 +8,6 @@ #include -enum rockchip_pinctrl_type { - RV1108, - RK3036, - RK3128, - RK3188, - RK3288, - RK3368, - RK3399, -}; - /** * Encode variants of iomux registers into a type variable */ @@ -266,8 +256,6 @@ struct rockchip_pin_ctrl { struct rockchip_pin_bank *pin_banks; u32 nr_banks; u32 nr_pins; - char *label; - enum rockchip_pinctrl_type type; int grf_mux_offset; int pmu_mux_offset; int grf_drv_offset; diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 6456483e36..0bcf11bb41 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -250,8 +250,6 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), - .label = "RV1108-GPIO", - .type = RV1108, .grf_mux_offset = 0x10, .pmu_mux_offset = 0x0, .iomux_recalced = rv1108_mux_recalced_data, From patchwork Tue Apr 16 13:58:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1086338 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44k6Rs4Cl0z9s7T for ; Tue, 16 Apr 2019 23:59:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3D0E4C21E57; Tue, 16 Apr 2019 13:58:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 27626C21E2F; Tue, 16 Apr 2019 13:58:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 90BCAC21DD4; Tue, 16 Apr 2019 13:58:24 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) by lists.denx.de (Postfix) with ESMTPS id 4E6D4C21E2B for ; Tue, 16 Apr 2019 13:58:20 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.228]) by lucky1.263xmail.com (Postfix) with ESMTP id 3112657289; Tue, 16 Apr 2019 21:58:17 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 0 X-SKE-CHECKED: 0 X-ANTISPAM-LEVEL: 2 Received: from thinkpad-p51.mshome.net (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P8430T139999016093440S1555423095293896_; Tue, 16 Apr 2019 21:58:17 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 16 Apr 2019 21:58:13 +0800 Message-Id: <20190416135813.27281-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190416135102.26667-1-david.wu@rock-chips.com> References: <20190416135102.26667-1-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: xypron.glpk@gmx.de, David Wu , jay.xu@rock-chips.com Subject: [U-Boot] [PATCH v3 10/10] pinctrl: rockchip: Also move common set_schmitter func into per Soc file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu Reviewed-by: Kever Yang --- Change in v3: - None drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17 ++++++++++++++++- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 19 +++---------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 5 ++--- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 17 ++++++++++++++++- 4 files changed, 37 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index d4d37af206..8d37a6f945 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -264,6 +264,21 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +static int rk3328_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u8 bit; + u32 data; + + rk3328_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), @@ -289,7 +304,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .set_mux = rk3328_set_mux, .set_pull = rk3328_set_pull, .set_drive = rk3328_set_drive, - .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, + .set_schmitt = rk3328_set_schmitt, }; static const struct udevice_id rk3328_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index b3379a0d3f..80dc431d20 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -306,30 +306,20 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; - struct regmap *regmap; - int reg, ret; - u8 bit; - u32 data; debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, pin_num, enable); - ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); - if (ret) - return ret; - - /* enable the write to the equivalent lower bits */ - data = BIT(bit + 16) | (enable << bit); + if (!ctrl->set_schmitt) + return -ENOTSUPP; - return regmap_write(regmap, reg, data); + return ctrl->set_schmitt(bank, pin_num, enable); } /* set the pin config settings for a specified pin */ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, u32 pin, u32 param, u32 arg) { - struct rockchip_pinctrl_priv *priv = bank->priv; - struct rockchip_pin_ctrl *ctrl = priv->ctrl; int rc; switch (param) { @@ -350,9 +340,6 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - if (!ctrl->schmitt_calc_reg) - return -ENOTSUPP; - rc = rockchip_set_schmitt(bank, pin, arg); if (rc < 0) return rc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 1c6fc2c5b2..9651e9c7a6 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -271,9 +271,8 @@ struct rockchip_pin_ctrl { int pin_num, int pull); int (*set_drive)(struct rockchip_pin_bank *bank, int pin_num, int strength); - int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); + int (*set_schmitt)(struct rockchip_pin_bank *bank, + int pin_num, int enable); }; /** diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 0bcf11bb41..54610a3e90 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -237,6 +237,21 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +static int rv1108_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u8 bit; + u32 data; + + rv1108_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -257,7 +272,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .set_mux = rv1108_set_mux, .set_pull = rv1108_set_pull, .set_drive = rv1108_set_drive, - .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, + .set_schmitt = rv1108_set_schmitt, }; static const struct udevice_id rv1108_pinctrl_ids[] = {