From patchwork Thu Apr 11 15:59:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Bauer X-Patchwork-Id: 1084134 X-Patchwork-Delegate: chunkeey@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=david-bauer.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="BMATlV3a"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44g5Mx6Nmqz9s47 for ; Fri, 12 Apr 2019 02:00:29 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Subject:MIME-Version:Message-Id:Date:To :From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=C2WDPp4pTE7JNzYn3YO1tGBxbDnHu3ukH9netk1EKKI=; b=BMATlV3a9B812e 5iaTW1IkcjWLzfPDQqar8+Anjt+G4LilmlGfoqPQz/9g3qz58USoIwg5nxKUZ0CCXZVbUto2SyUS5 k2yUKA08vRCH5TibKQGsNnBcv+1xTmWCqB79o+TI/VAcdN9nNONprGI6UuJFHL2Fm14TC+hzW/1yt 09KOuWv0u0L2YhoVim7nqk+75FSI6Zn463biC/5nfmgQUmw7bW/eHJBsNp3JrlVpBxt+CnOICS4HH dcnQ7+ZA2lxX5cNqaV8bCqEF2Z4PgneCvRZgnOF0lcbiRLIcAG3Lo5atH9fACPjS8aZvY+Li5x55H n1iqgc4vAGacvOq2HjFA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc7N-0001uR-P8; Thu, 11 Apr 2019 16:00:01 +0000 Received: from mars.blocktrron.ovh ([51.254.112.43] helo=mail.blocktrron.ovh) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc7K-0001iZ-T8 for openwrt-devel@lists.openwrt.org; Thu, 11 Apr 2019 16:00:00 +0000 Received: from localhost.localdomain (p200300E53F099C0093B6E161A050D22A.dip0.t-ipconnect.de [IPv6:2003:e5:3f09:9c00:93b6:e161:a050:d22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.blocktrron.ovh (Postfix) with ESMTPSA id 900E3221C9 for ; Thu, 11 Apr 2019 17:59:53 +0200 (CEST) From: David Bauer To: openwrt-devel@lists.openwrt.org Date: Thu, 11 Apr 2019 17:59:42 +0200 Message-Id: <20190411155945.28600-1-mail@david-bauer.net> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_085959_091321_8967CCFC X-CRM114-Status: GOOD ( 10.34 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 1/4] ath79: fix QCA955x GMAC register size X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The register size of the QCA955x currently matches the size stated in the datasheet. However, there are more hidden GMAC registers which are needed for the SGMII workaround to work. Signed-off-by: David Bauer --- target/linux/ath79/dts/qca9557.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi index fefb91c39a..b726a382ee 100644 --- a/target/linux/ath79/dts/qca9557.dtsi +++ b/target/linux/ath79/dts/qca9557.dtsi @@ -223,7 +223,7 @@ gmac: gmac@18070000 { compatible = "qca,qca9550-gmac"; - reg = <0x18070000 0x14>; + reg = <0x18070000 0x58>; }; wmac: wmac@18100000 { From patchwork Thu Apr 11 15:59:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Bauer X-Patchwork-Id: 1084137 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=david-bauer.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cCAACP3M"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44g5NP4PXCz9s47 for ; Fri, 12 Apr 2019 02:00:53 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Subject:MIME-Version:References: In-Reply-To:Message-Id:Date:To:From:Reply-To:Cc:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=qmSYmmmj4y5WBg9u1/AtO8L/CrZDqUJnU5UzBv8Yhn0=; b=cCAACP3MzmoUEJbs7N1bUN4ZVw ogOfUJhPkbTRwaE43NHoQqK7jQdC2WcPtwMSP7lHjvMeIo30+UhxxdBoR/GXxVWotzHmaAtLWDKUa awvslHUlmzz1tpaKO407q8MgXzaMZVGJrOmsDhUf6b4EH1/SQPTvShT9wQKrGreNqO+wo01XddbMg GCm+xVAwo0aJbayTk+4+ZO0t4KGC8O+TPMS7uuyXprgQFbOpHXdAa1/8cDHZMlJ8cDAy0JrA2MC/w H+wfGaJqzuGHOl72Wlo645+v2P9COG0EoKSnfz/GSylzKk/XyRcsTSqRgI9qLj4MwSjwu4IfdxXxu OmW1HOhw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc80-0003rE-7w; Thu, 11 Apr 2019 16:00:40 +0000 Received: from mars.blocktrron.ovh ([51.254.112.43] helo=mail.blocktrron.ovh) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc7K-0001iW-Pu for openwrt-devel@lists.openwrt.org; Thu, 11 Apr 2019 16:00:02 +0000 Received: from localhost.localdomain (p200300E53F099C0093B6E161A050D22A.dip0.t-ipconnect.de [IPv6:2003:e5:3f09:9c00:93b6:e161:a050:d22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.blocktrron.ovh (Postfix) with ESMTPSA id E7EBD221DF for ; Thu, 11 Apr 2019 17:59:53 +0200 (CEST) From: David Bauer To: openwrt-devel@lists.openwrt.org Date: Thu, 11 Apr 2019 17:59:43 +0200 Message-Id: <20190411155945.28600-2-mail@david-bauer.net> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190411155945.28600-1-mail@david-bauer.net> References: <20190411155945.28600-1-mail@david-bauer.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_085959_146377_079BF470 X-CRM114-Status: GOOD ( 19.45 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 2/4] ath79: add QCA955x SGMII link loss workaround X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org This commit adds a workaround for the loss of the SGMII link observed on the QCA955x generation of SoCs. The workaround originates part from the U-Boot source code, part from the implementation from AVM found in the GPL tarball for the AVM FRITZ!WLAN Repeater 450E. The bug results in a stuck SGMII link between the PHY device and the SoC side. This has only been observed with the Atheros AR8033 PHY and most likely all devices using such combination are affected. It is worked around by reading a hidden SGMII status register and issuing a SGMII PHY reset until the link becomes useable again. Signed-off-by: David Bauer --- .../net/ethernet/atheros/ag71xx/ag71xx_main.c | 108 ++++++++++++++++++ ...9-add-missing-QCA955x-GMAC-registers.patch | 91 +++++++++++++++ ...9-add-missing-QCA955x-GMAC-registers.patch | 91 +++++++++++++++ 3 files changed, 290 insertions(+) create mode 100644 target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch create mode 100644 target/linux/ath79/patches-4.19/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c index 8cff56a11a..a7565e6ffb 100644 --- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -559,6 +559,112 @@ static void ath79_set_pll(struct ag71xx *ag) udelay(100); } +static void ag71xx_bit_set(void __iomem *reg, u32 bit) +{ + u32 val; + + val = __raw_readl(reg) | bit; + __raw_writel(val, reg); + __raw_readl(reg); +} + +static void ag71xx_bit_clear(void __iomem *reg, u32 bit) +{ + u32 val; + + val = __raw_readl(reg) & ~bit; + __raw_writel(val, reg); + __raw_readl(reg); +} + +static void ag71xx_sgmii_init_qca955x(struct device_node *np) +{ + struct device_node *np_dev; + void __iomem *gmac_base; + u32 mr_an_status; + u32 sgmii_status; + u8 tries = 0; + int err = 0; + + np = of_get_child_by_name(np, "gmac-config"); + if (!np) + return; + + np_dev = of_parse_phandle(np, "device", 0); + if (!np_dev) + goto out; + + gmac_base = of_iomap(np_dev, 0); + if (!gmac_base) { + pr_err("%pOF: can't map GMAC registers\n", np_dev); + err = -ENOMEM; + goto err_iomap; + } + + mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS); + if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY)) + goto sgmii_out; + + /* SGMII reset sequence */ + __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET, + gmac_base + QCA955X_GMAC_REG_SGMII_RESET); + __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET); + udelay(10); + + ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, + QCA955X_SGMII_RESET_HW_RX_125M_N); + udelay(10); + + ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, + QCA955X_SGMII_RESET_RX_125M_N); + udelay(10); + + ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, + QCA955X_SGMII_RESET_TX_125M_N); + udelay(10); + + ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, + QCA955X_SGMII_RESET_RX_CLK_N); + udelay(10); + + ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, + QCA955X_SGMII_RESET_TX_CLK_N); + udelay(10); + + /* + * The following is what QCA has to say about what happens here: + * + * Across resets SGMII link status goes to weird state. + * If SGMII_DEBUG register reads other than 0x1f or 0x10, + * we are for sure in a bad state. + * + * Issue a PHY reset in MR_AN_CONTROL to keep going. + */ + do { + ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL, + QCA955X_MR_AN_CONTROL_PHY_RESET | + QCA955X_MR_AN_CONTROL_AN_ENABLE); + udelay(200); + ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL, + QCA955X_MR_AN_CONTROL_PHY_RESET); + mdelay(300); + sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & + QCA955X_SGMII_DEBUG_TX_STATE_MASK; + + if (tries++ >= 20) { + pr_err("ag71xx: max retries for SGMII fixup exceeded\n"); + break; + } + } while (!(sgmii_status == 0xf || sgmii_status == 0x10)); + +sgmii_out: + iounmap(gmac_base); +err_iomap: + of_node_put(np_dev); +out: + of_node_put(np); +} + static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if) { u32 t; @@ -705,6 +811,8 @@ __ag71xx_link_adjust(struct ag71xx *ag, bool update) of_device_is_compatible(np, "qca,qca9550-eth") || of_device_is_compatible(np, "qca,qca9560-eth")) { ath79_set_pllval(ag); + if (of_property_read_bool(np, "qca955x-sgmii-fixup")) + ag71xx_sgmii_init_qca955x(np); } } diff --git a/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch new file mode 100644 index 0000000000..111c1553d3 --- /dev/null +++ b/target/linux/ath79/patches-4.14/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch @@ -0,0 +1,91 @@ +From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Mon, 18 Mar 2019 00:54:06 +0100 +Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers + +This adds missing GMAC register definitions for the Qualcomm Atheros +QCA955X series MIPS SoCs. + +They originate from the platforms U-Boot code and the AVM FRITZ!WLAN +Repeater 450E's GPL tarball. + +Signed-off-by: David Bauer +--- + .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1245,7 +1245,12 @@ + */ + + #define QCA955X_GMAC_REG_ETH_CFG 0x00 ++#define QCA955X_GMAC_REG_SGMII_RESET 0x14 + #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 ++#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34 ++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 + + #define QCA955X_ETH_CFG_RGMII_EN BIT(0) + #define QCA955X_ETH_CFG_MII_GE0 BIT(1) +@@ -1267,9 +1272,58 @@ + #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 + #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + ++#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0 ++#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) ++#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) ++#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) ++#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) ++#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) ++ + #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) + #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 + #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++ ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) ++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) ++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) ++ ++#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0) ++#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2) ++#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) ++#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4) ++#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5) ++#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6) ++#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7) ++ ++#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 ++#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) ++#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) ++#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5) ++#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6 ++#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0 ++#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) ++#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) ++#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10) ++#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11) ++#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) ++#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13) ++#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14) ++ ++#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00 ++#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000 ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000 ++#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++ + /* + * QCA956X GMAC Interface + */ + diff --git a/target/linux/ath79/patches-4.19/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-4.19/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch new file mode 100644 index 0000000000..111c1553d3 --- /dev/null +++ b/target/linux/ath79/patches-4.19/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch @@ -0,0 +1,91 @@ +From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Mon, 18 Mar 2019 00:54:06 +0100 +Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers + +This adds missing GMAC register definitions for the Qualcomm Atheros +QCA955X series MIPS SoCs. + +They originate from the platforms U-Boot code and the AVM FRITZ!WLAN +Repeater 450E's GPL tarball. + +Signed-off-by: David Bauer +--- + .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1245,7 +1245,12 @@ + */ + + #define QCA955X_GMAC_REG_ETH_CFG 0x00 ++#define QCA955X_GMAC_REG_SGMII_RESET 0x14 + #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 ++#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34 ++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 + + #define QCA955X_ETH_CFG_RGMII_EN BIT(0) + #define QCA955X_ETH_CFG_MII_GE0 BIT(1) +@@ -1267,9 +1272,58 @@ + #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 + #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + ++#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0 ++#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) ++#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) ++#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) ++#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) ++#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) ++ + #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) + #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 + #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++ ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) ++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) ++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) ++ ++#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0) ++#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2) ++#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) ++#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4) ++#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5) ++#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6) ++#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7) ++ ++#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 ++#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) ++#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) ++#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5) ++#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6 ++#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0 ++#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) ++#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) ++#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10) ++#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11) ++#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) ++#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13) ++#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14) ++ ++#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00 ++#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000 ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000 ++#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++ + /* + * QCA956X GMAC Interface + */ + From patchwork Thu Apr 11 15:59:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Bauer X-Patchwork-Id: 1084136 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=david-bauer.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FeB4RVXj"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44g5N55tHLz9s47 for ; Fri, 12 Apr 2019 02:00:37 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Subject:MIME-Version:References: In-Reply-To:Message-Id:Date:To:From:Reply-To:Cc:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=GZZYyzk3jSclhlG2iUIo7exUG92aOTxtNJny5N7a8ec=; b=FeB4RVXjLCZJ1JIHZVRTkUdltg G8qBbxEy3qZ/9/FgHm8/MLe4bx+Fcg9hxE6rd9pKYeshRlWArzbflXL4YxH2KsWMn2vMFYmfUfeF/ v+wz+5b8Tirw1bqgo+o+i2rH1Seehi8kaAVy6HW2Cdw3HgW3dTSu0vp91+Rb8cHOoBh2azoKZofj4 Ovn/RJNqKD/Ij0WWTc7Di0jxPVr8rElOWv644yViVkwgWHgKWizPhHUEcke0qImlEUkT5DXN4p6ef u5zeYAlLaI8tiPBbCq/U7G64pLTPcfh80LIUTekB1Bpy5TukyBRVCh9NtUijzgpjdkk5LpKvPJnxh xzxrnEng==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc7n-0003YV-Fq; Thu, 11 Apr 2019 16:00:27 +0000 Received: from mars.blocktrron.ovh ([2001:41d0:401:3000::cbd] helo=mail.blocktrron.ovh) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc7L-0001iX-60 for openwrt-devel@lists.openwrt.org; Thu, 11 Apr 2019 16:00:02 +0000 Received: from localhost.localdomain (p200300E53F099C0093B6E161A050D22A.dip0.t-ipconnect.de [IPv6:2003:e5:3f09:9c00:93b6:e161:a050:d22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.blocktrron.ovh (Postfix) with ESMTPSA id 423D9221E0 for ; Thu, 11 Apr 2019 17:59:54 +0200 (CEST) From: David Bauer To: openwrt-devel@lists.openwrt.org Date: Thu, 11 Apr 2019 17:59:44 +0200 Message-Id: <20190411155945.28600-3-mail@david-bauer.net> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190411155945.28600-1-mail@david-bauer.net> References: <20190411155945.28600-1-mail@david-bauer.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_085959_365889_794167AE X-CRM114-Status: GOOD ( 11.11 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 3/4] ath79: allow to override AR8033 SGMII aneg status X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org In order to make the QCA955x SGMII workaround work, the unsuccessful SGMII autonegotiation on the AR8033 should not block the PHY state-machine. Otherwise, the ag71xx driver never becomes aware of the copper-side link-establishment and the workaround is never executed. Signed-off-by: David Bauer --- .../425-at803x-allow-sgmii-aneg-override.patch | 16 ++++++++++++++++ .../425-at803x-allow-sgmii-aneg-override.patch | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch create mode 100644 target/linux/ath79/patches-4.19/425-at803x-allow-sgmii-aneg-override.patch diff --git a/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch b/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch new file mode 100644 index 0000000000..0ac6af38f3 --- /dev/null +++ b/target/linux/ath79/patches-4.14/425-at803x-allow-sgmii-aneg-override.patch @@ -0,0 +1,16 @@ +--- a/drivers/net/phy/at803x.c ++++ b/drivers/net/phy/at803x.c +@@ -484,6 +484,13 @@ static int at803x_aneg_done(struct phy_d + if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { + pr_warn("803x_aneg_done: SGMII link is not ok\n"); + aneg_done = 0; ++#ifdef CONFIG_OF_MDIO ++ if (phydev->mdio.dev.of_node && ++ of_property_read_bool(phydev->mdio.dev.of_node, ++ "at803x-override-sgmii-link-check")) { ++ aneg_done = 1; ++ } ++#endif + } + /* switch back to copper page */ + phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); diff --git a/target/linux/ath79/patches-4.19/425-at803x-allow-sgmii-aneg-override.patch b/target/linux/ath79/patches-4.19/425-at803x-allow-sgmii-aneg-override.patch new file mode 100644 index 0000000000..0ac6af38f3 --- /dev/null +++ b/target/linux/ath79/patches-4.19/425-at803x-allow-sgmii-aneg-override.patch @@ -0,0 +1,16 @@ +--- a/drivers/net/phy/at803x.c ++++ b/drivers/net/phy/at803x.c +@@ -484,6 +484,13 @@ static int at803x_aneg_done(struct phy_d + if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { + pr_warn("803x_aneg_done: SGMII link is not ok\n"); + aneg_done = 0; ++#ifdef CONFIG_OF_MDIO ++ if (phydev->mdio.dev.of_node && ++ of_property_read_bool(phydev->mdio.dev.of_node, ++ "at803x-override-sgmii-link-check")) { ++ aneg_done = 1; ++ } ++#endif + } + /* switch back to copper page */ + phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); From patchwork Thu Apr 11 15:59:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Bauer X-Patchwork-Id: 1084135 X-Patchwork-Delegate: mail@david-bauer.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=lists.openwrt.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=david-bauer.net Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Crq4cIiy"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44g5N070Xzz9s47 for ; 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Thu, 11 Apr 2019 16:00:15 +0000 Received: from mars.blocktrron.ovh ([51.254.112.43] helo=mail.blocktrron.ovh) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEc7K-0001ib-Oo for openwrt-devel@lists.openwrt.org; Thu, 11 Apr 2019 16:00:00 +0000 Received: from localhost.localdomain (p200300E53F099C0093B6E161A050D22A.dip0.t-ipconnect.de [IPv6:2003:e5:3f09:9c00:93b6:e161:a050:d22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.blocktrron.ovh (Postfix) with ESMTPSA id 78F8C221E3 for ; Thu, 11 Apr 2019 17:59:54 +0200 (CEST) From: David Bauer To: openwrt-devel@lists.openwrt.org Date: Thu, 11 Apr 2019 17:59:45 +0200 Message-Id: <20190411155945.28600-4-mail@david-bauer.net> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190411155945.28600-1-mail@david-bauer.net> References: <20190411155945.28600-1-mail@david-bauer.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_085958_959873_FA74F034 X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record Subject: [OpenWrt-Devel] [PATCH 4/4] ath79: enable QCA955x SGMII workaround X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org Enable the QCA955x SGMII workaround for all devices which sport the AR8033 + QCA955x combination which is known to show the link-stuck symptoms. Signed-off-by: David Bauer --- target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi | 6 ++++++ target/linux/ath79/dts/qca9558_ocedo_ursus.dts | 6 ++++++ target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi index 9937186b1e..e2d1b7cc94 100644 --- a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi +++ b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi @@ -131,6 +131,7 @@ &mdio1 { phy1: ethernet-phy@1 { reg = <1>; + at803x-override-sgmii-link-check; }; }; @@ -139,6 +140,11 @@ mtd-mac-address-increment = <1>; phy-handle = <&phy1>; pll-data = <0x03000101 0x00000101 0x00001313>; + qca955x-sgmii-fixup; + + gmac-config { + device = <&gmac>; + }; }; &wmac { diff --git a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts index 1a92da3946..53bfa51fd2 100644 --- a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts +++ b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts @@ -119,6 +119,7 @@ phy2: ethernet-phy@2 { reg = <2>; + at803x-override-sgmii-link-check; }; }; @@ -144,4 +145,9 @@ mtd-mac-address = <&art 0x12>; phy-handle = <&phy2>; pll-data = <0x3000101 0x101 0x1313>; + qca955x-sgmii-fixup; + + gmac-config { + device = <&gmac>; + }; }; diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts index 1e3cf40f71..d05e844d63 100644 --- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts +++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts @@ -146,6 +146,7 @@ phy1: ethernet-phy@1 { reg = <1>; phy-mode = "sgmii"; + at803x-override-sgmii-link-check; }; }; @@ -165,4 +166,9 @@ phy-handle = <&phy1>; phy-mode = "sgmii"; + qca955x-sgmii-fixup; + + gmac-config { + device = <&gmac>; + }; };