From patchwork Wed Apr 3 09:08:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075624 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0dq4XYhz9sS3 for ; Wed, 3 Apr 2019 20:09:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nIjiFQeR"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Z0dq2szGzDqQX for ; Wed, 3 Apr 2019 20:09:51 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::643; helo=mail-pl1-x643.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nIjiFQeR"; dkim-atps=neutral Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Z0dc59MfzDqFK for ; Wed, 3 Apr 2019 20:09:39 +1100 (AEDT) Received: by mail-pl1-x643.google.com with SMTP id ck15so6524445plb.3 for ; Wed, 03 Apr 2019 02:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XV9wTmrmmxHAlZxRxX0gnqCXXbBkxx3LCdVXnUZ2WFs=; b=nIjiFQeRckKxFzLMZqbgew7QOSrjXCbMbkRH5Ervzm4QGvjVFlcHzGM4NXkuVps5IQ +W3oUmcrNBuTpsw84fQrRaG6AkjraiNJ+2tNjLWaP5HGSQhNvpu3tXw0dJ/KHqVvcZbO nL92U+XEArWvgdqpK3z9QxXRnorgA4ciE1IemF3/6tH0LostQ1tCMDx1sPns4gnff05r 4lsFCNoYi2fwZDR8De1Z9s2PLzQLeWfJiHuk7C/C9gblzbgonV4uNzHzDQe3aMQHVLNY 8ry5sE9wy5JFMAVsFPyiVcOIBViTr9XhYhmh2C3fq+tMxIp7+479UeJjbDVK7uFtTI4E Iu6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XV9wTmrmmxHAlZxRxX0gnqCXXbBkxx3LCdVXnUZ2WFs=; b=IC5NxEJsCnyAezO/EtE1KLF9q2mDyKCnFZXIuMg1E6GQV1Qgdh+x/fuhd9iCL6UOtx rbsPRqhtOoj3aUk8dE/zS0LBhqtyLARpuBalJKJ9KrakcAnlW0yM1kdGuU6FM0C96+aM bmLEcS6Z40pvoz+3ZZK+oZK/pjTv0qJfiYVN3o0ZT4Db/kSWJzIfRGnE5dXxPdrnT1eA BqTUReXpUYWuxcIHbNE5IJ6HmT8H224VqKvsuL+m+/OUk2HlA7QLwKaXCwVoGPqSf80g TaZo7PsdwVamK3YDYZaluyytu2vxyHm99filARXzypwAaiOcn710EA7efi9r9ZmuEuz9 071w== X-Gm-Message-State: APjAAAUol3J3x/fmvoVMHXuR03xkSEIR0oft2NG0DUw2Ri5jInqXuesU aZnM4mexDxPhTJP+nN5EmdmMkLIB X-Google-Smtp-Source: APXvYqyKGgqcsAuH/byH4hWomZgvWDuYpzdEmTJdgD02hZfRzlRiisLfIJR1Csog7IkztdXhT+cbvA== X-Received: by 2002:a17:902:e109:: with SMTP id cc9mr23141427plb.148.1554282577036; Wed, 03 Apr 2019 02:09:37 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:36 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:08:58 +1100 Message-Id: <20190403090920.362-2-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 01/23] platform/firenze-pci: Remove freset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The pci slot set_power_state() method is being converted to use a polling based API rather than async completion callbacks. This patch removes the firenze-pci freset method and the associated i2c competion callback since keeping them complicates the rework and they're going to be deleted later anyway. The set_power_state and get_power_state methods are retained and marked __unused since they will be reworked in a later patch. Signed-off-by: Oliver O'Halloran --- platforms/ibm-fsp/firenze-pci.c | 272 +------------------------------- 1 file changed, 4 insertions(+), 268 deletions(-) diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c index ac2580fb4a9a..0ed53301485e 100644 --- a/platforms/ibm-fsp/firenze-pci.c +++ b/platforms/ibm-fsp/firenze-pci.c @@ -360,268 +360,7 @@ bail: firenze_inv_cnt = 0; } -/* The function is called when the I2C request is completed - * successfully, or with errors. - */ -static void firenze_i2c_req_done(int rc, struct i2c_request *req) -{ - struct pci_slot *slot = req->user_data; - uint32_t state; - - /* Check if there are errors for the completion */ - if (rc) { - /** - * @fwts-label FirenzePCII2CError - * @fwts-advice On Firenze platforms, I2C is used to control - * power to PCI slots. Errors here mean we may be in trouble - * in regards to PCI slot power on/off. - */ - prlog(PR_ERR, "Error %d from I2C request on slot %016llx\n", - rc, slot->id); - return; - } - - /* Check the request type */ - if (req->op != SMBUS_READ && req->op != SMBUS_WRITE) { - /** - * @fwts-label FirenzePCII2CInvalid - * @fwts-advice Likely a coding error: invalid I2C request. - */ - prlog(PR_ERR, "Invalid I2C request %d on slot %016llx\n", - req->op, slot->id); - return; - } - - /* After writting power status to I2C slave, we need at least - * 5ms delay for the slave to settle down. We also have the - * delay after reading the power status as well. - */ - switch (slot->state) { - case FIRENZE_PCI_SLOT_FRESET_WAIT_RSP: - prlog(PR_DEBUG, "%016llx FRESET: I2C request completed\n", - slot->id); - state = FIRENZE_PCI_SLOT_FRESET_DELAY; - break; - case FIRENZE_PCI_SLOT_SPOWER_START: - prlog(PR_DEBUG, "%016llx SPOWER: I2C request completed\n", - slot->id); - state = FIRENZE_PCI_SLOT_SPOWER_DONE; - break; - default: - /** - * @fwts-label FirenzePCISlotI2CStateError - * @fwts-advice The Firenze platform uses I2C to control - * power to PCI slots. Something went wrong in the state - * machine controlling that. Slots may/may not have power. - */ - prlog(PR_ERR, "Wrong state %08x on slot %016llx\n", - slot->state, slot->id); - return; - } - - /* Switch to net state */ - pci_slot_set_state(slot, state); -} - -/* This function is called to setup normal PCI device or PHB slot. - * For the later case, the slot doesn't have the associated PCI - * device. Besides, the I2C response timeout is set to 5s. We might - * improve I2C in future to support priorized requests so that the - * timeout can be shortened. - */ -static int64_t firenze_pci_slot_freset(struct pci_slot *slot) -{ - struct firenze_pci_slot *plat_slot = slot->data; - uint8_t *pval, presence = 1; - uint32_t timeout; - - switch (slot->state) { - case FIRENZE_PCI_SLOT_NORMAL: - case FIRENZE_PCI_SLOT_FRESET_START: - prlog(PR_DEBUG, "%016llx FRESET: Starts\n", - slot->id); - - /* Bail if nothing is connected */ - if (slot->ops.get_presence_state) - slot->ops.get_presence_state(slot, &presence); - if (!presence) { - prlog(PR_DEBUG, "%016llx FRESET: No device\n", - slot->id); - return OPAL_SUCCESS; - } - - /* Prepare link down */ - if (slot->ops.prepare_link_change) { - prlog(PR_DEBUG, "%016llx FRESET: Prepares link down\n", - slot->id); - slot->ops.prepare_link_change(slot, false); - } - - /* Send I2C request */ - prlog(PR_DEBUG, "%016llx FRESET: Check power state\n", - slot->id); - plat_slot->next_state = - FIRENZE_PCI_SLOT_FRESET_POWER_STATE; - plat_slot->req->op = SMBUS_READ; - slot->retries = FIRENZE_PCI_SLOT_RETRIES; - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_FRESET_WAIT_RSP); - if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP)) - plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT; - else - plat_slot->req->timeout = 0ul; - i2c_queue_req(plat_slot->req); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_WAIT_RSP: - if (slot->retries-- == 0) { - prlog(PR_DEBUG, "%016llx FRESET: Timeout waiting for %08x\n", - slot->id, plat_slot->next_state); - goto out; - } - - check_timers(false); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_DELAY: - prlog(PR_DEBUG, "%016llx FRESET: Delay %dms on I2C completion\n", - slot->id, FIRENZE_PCI_SLOT_DELAY); - pci_slot_set_state(slot, plat_slot->next_state); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_POWER_STATE: - /* Update last power status */ - pval = (uint8_t *)(plat_slot->req->rw_buf); - *plat_slot->power_status = *pval; - - /* Power is on, turn it off */ - if (((*pval) & plat_slot->power_mask) == plat_slot->power_on) { - prlog(PR_DEBUG, "%016llx FRESET: Power (%02x) on, turn off\n", - slot->id, *pval); - (*pval) &= ~plat_slot->power_mask; - (*pval) |= plat_slot->power_off; - plat_slot->req->op = SMBUS_WRITE; - slot->retries = FIRENZE_PCI_SLOT_RETRIES; - plat_slot->next_state = - FIRENZE_PCI_SLOT_FRESET_POWER_OFF; - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_FRESET_WAIT_RSP); - - if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP)) - timeout = FIRENZE_PCI_I2C_TIMEOUT; - else - timeout = 0ul; - plat_slot->req->timeout = timeout; - - i2c_queue_req(plat_slot->req); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - } - - /* Power is off, turn it on */ - /* Fallthrough */ - case FIRENZE_PCI_SLOT_FRESET_POWER_OFF: - /* Update last power status */ - pval = (uint8_t *)(plat_slot->req->rw_buf); - *plat_slot->power_status = *pval; - - prlog(PR_DEBUG, "%016llx FRESET: Power (%02x) off, turn on\n", - slot->id, *pval); - (*pval) &= ~plat_slot->power_mask; - (*pval) |= plat_slot->power_on; - plat_slot->req->op = SMBUS_WRITE; - plat_slot->next_state = - FIRENZE_PCI_SLOT_FRESET_POWER_ON; - slot->retries = FIRENZE_PCI_SLOT_RETRIES; - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_FRESET_WAIT_RSP); - - if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP)) - plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT; - else - plat_slot->req->timeout = 0ul; - i2c_queue_req(plat_slot->req); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_POWER_ON: - /* Update last power status */ - pval = (uint8_t *)(plat_slot->req->rw_buf); - *plat_slot->power_status = *pval; - - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_LINK_START); - return slot->ops.poll_link(slot); - default: - prlog(PR_DEBUG, "%016llx FRESET: Unexpected state %08x\n", - slot->id, slot->state); - } - -out: - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_NORMAL); - return OPAL_HARDWARE; -} - -static int64_t firenze_pci_slot_perst(struct pci_slot *slot) -{ - struct firenze_pci_slot *plat_slot = slot->data; - uint8_t presence = 1; - uint16_t ctrl; - - switch (slot->state) { - case FIRENZE_PCI_SLOT_NORMAL: - case FIRENZE_PCI_SLOT_FRESET_START: - prlog(PR_DEBUG, "%016llx PERST: Starts\n", - slot->id); - - /* Bail if nothing is connected */ - if (slot->ops.get_presence_state) - slot->ops.get_presence_state(slot, &presence); - if (!presence) { - prlog(PR_DEBUG, "%016llx PERST: No device\n", - slot->id); - return OPAL_SUCCESS; - } - - /* Prepare link down */ - if (slot->ops.prepare_link_change) { - prlog(PR_DEBUG, "%016llx PERST: Prepare link down\n", - slot->id); - slot->ops.prepare_link_change(slot, false); - } - - /* Assert PERST */ - prlog(PR_DEBUG, "%016llx PERST: Assert\n", - slot->id); - pci_cfg_read16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, &ctrl); - ctrl |= plat_slot->perst_bit; - pci_cfg_write16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, ctrl); - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_PERST_DEASSERT); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(250)); - case FIRENZE_PCI_SLOT_PERST_DEASSERT: - /* Deassert PERST */ - pci_cfg_read16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, &ctrl); - ctrl &= ~plat_slot->perst_bit; - pci_cfg_write16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, ctrl); - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_PERST_DELAY); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(1500)); - case FIRENZE_PCI_SLOT_PERST_DELAY: - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_LINK_START); - return slot->ops.poll_link(slot); - default: - prlog(PR_DEBUG, "%016llx PERST: Unexpected state %08x\n", - slot->id, slot->state); - } - - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_NORMAL); - return OPAL_HARDWARE; -} - -static int64_t firenze_pci_slot_get_power_state(struct pci_slot *slot, +static int64_t __unused firenze_pci_slot_get_power_state(struct pci_slot *slot, uint8_t *val) { if (slot->state != FIRENZE_PCI_SLOT_NORMAL) @@ -640,7 +379,7 @@ static int64_t firenze_pci_slot_get_power_state(struct pci_slot *slot, return OPAL_SUCCESS; } -static int64_t firenze_pci_slot_set_power_state(struct pci_slot *slot, +static int64_t __unused firenze_pci_slot_set_power_state(struct pci_slot *slot, uint8_t val) { struct firenze_pci_slot *plat_slot = slot->data; @@ -835,7 +574,6 @@ static void firenze_pci_setup_power_mgt(struct pci_slot *slot, plat_slot->req->offset_bytes = 1; plat_slot->req->rw_buf = plat_slot->i2c_rw_buf; plat_slot->req->rw_len = 1; - plat_slot->req->completion = firenze_i2c_req_done; plat_slot->req->user_data = slot; plat_slot->req->bus = plat_slot->i2c_bus; @@ -907,9 +645,7 @@ static void firenze_pci_slot_init(struct pci_slot *slot) * configuration after we have a blocking API for that. */ if (plat_slot->req) { - slot->ops.freset = firenze_pci_slot_freset; - slot->ops.get_power_state = firenze_pci_slot_get_power_state; - slot->ops.set_power_state = firenze_pci_slot_set_power_state; + /* placeholder */ prlog(PR_DEBUG, "%016llx: External power mgt initialized\n", slot->id); } else if (info->inband_perst) { @@ -927,7 +663,7 @@ static void firenze_pci_slot_init(struct pci_slot *slot) case 0x874810b5: /* PLX8748 */ plat_slot->perst_reg = 0x80; plat_slot->perst_bit = 0x0400; - slot->ops.freset = firenze_pci_slot_perst; + /* placeholder */ break; } } From patchwork Wed Apr 3 09:08:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075625 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0fY2Vtgz9sS3 for ; Wed, 3 Apr 2019 20:10:29 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oyBCEcmz"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Z0fY0nHdzDqRH for ; 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Wed, 03 Apr 2019 02:09:39 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:38 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:08:59 +1100 Message-Id: <20190403090920.362-3-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 02/23] core/pcie-slot: Make power control synchronous X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Hack in a synchronus wait rather than returning OPAL_ASYNC_TOKEN so the the caller waits for the POWER_ON operation to finish. We want to convert the existing users of the set_power_state() API to use a polling based API rather than the crapshoot of async completion callbacks we have now. Signed-off-by: Oliver O'Halloran --- core/pcie-slot.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/core/pcie-slot.c b/core/pcie-slot.c index ead767de01e4..0ed903501178 100644 --- a/core/pcie-slot.c +++ b/core/pcie-slot.c @@ -256,7 +256,6 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val, */ } - pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_START); slot->power_state = val; ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false); pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state); @@ -269,16 +268,20 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val, state |= (PCIE_INDIC_ON << 8); break; default: - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); prlog(PR_ERR, PCIE_SLOT_PREFIX "Invalid power state (0x%x)\n", slot->id, val); return OPAL_PARAMETER; } pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state); - pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_DONE); - return OPAL_ASYNC_COMPLETION; + /* + * HACK: wait a bit for the link to come up. Drop this once we've + * converted users of set_power_state to use the new interface + */ + time_wait_ms(10); + + return OPAL_SUCCESS; } static int64_t pcie_slot_set_power_state(struct pci_slot *slot, uint8_t val) From patchwork Wed Apr 3 09:09:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075627 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0g25tLGz9sS3 for ; Wed, 3 Apr 2019 20:10:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eUNAVLpk"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Z0g23rj2zDqTs for ; Wed, 3 Apr 2019 20:10:54 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eUNAVLpk"; dkim-atps=neutral Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Z0dg3XbzzDqCl for ; Wed, 3 Apr 2019 20:09:43 +1100 (AEDT) Received: by mail-pg1-x541.google.com with SMTP id p6so7982952pgh.9 for ; Wed, 03 Apr 2019 02:09:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UHiRNCR8QX1cjUzG1DSauT0EMr2br0VaM8ZDak2D7jE=; b=eUNAVLpk7POUedGpfnG8ofY8/rx0TKWO7AFiiQk6RKUGHDG/duuexq27l/N5duuZwo 4VPuRRuKjMfyadMj5b5zODNNqhShi0MU6tXlhaS0DuPYXi6AyhAc7f+X3XqBUJaIiZuv gcFtyshpZe0XQ07ZJx/eC42QC2k1mXwO1/8Vp8m+Fo8XJ5Qv6VCdWhkKxj3T5xgYeP7C 30djyJcIMeLuH63XEhB2pneOHlQyn25NUb2PCVLiKHKM0sfRLDk9A/kPZ6AMKj0Oe75o IbiVh7h0dhZjVmjVq3ecTsBKDGzXaienGcqdO7GNw1jAiGg4fryny1I48kHinyDjYoOE 4I7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UHiRNCR8QX1cjUzG1DSauT0EMr2br0VaM8ZDak2D7jE=; b=cPe1uyikAyJHx/udEuoQgHDIE0jwNaIhi+YvJIULzZS/qFOrsh2okpr5ZmcXxkLwiv bKl9KRDd9QEUiRdrjVS01t5vuTJd91PWqo23jKtG3AZ7o4RTmd6IQlk9NmGMxjcTRgk/ Y4Sw+S1MyE4oA/r0kDMZlRJGGAFpXrOW0uiIv6at5aJ3m3NDQoZTOwr3epnm8XzwPlxJ bpSoIQjcwxntfvyyQRrrLB8Dr9ABz7jOMoxzb3gwTmO6px3pB00Y3H9nWDjGQdHcjMNX 331cXt8cBfH/+MfQM1O7hlLaxdjUwhTIySpQqQ4ITVY6xSexGRyz89IuWikX43NLrPjZ XnOw== X-Gm-Message-State: APjAAAVYnMw9yinaRiINhoq/xojgm1xy+ED/bigAIRbq+oY0kdtHqC/c 9VjNjKuh1+Zyvppcb9SH6DmzBYg+ X-Google-Smtp-Source: APXvYqzhRrhaA1hLFqgojw8FFrZyvPO67t0F3nlETIby5Anru3QFK+ije+6DwwrE9cAeAVnTEb7PTw== X-Received: by 2002:aa7:9151:: with SMTP id 17mr37903496pfi.192.1554282581028; Wed, 03 Apr 2019 02:09:41 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:40 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:00 +1100 Message-Id: <20190403090920.362-4-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 03/23] core/pci-opal: Convert set_power_state timer X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Crack this in two so that we bring the slot power up, then bring up the link using the slot state machine. This allows us to properly handle hotplug on root complex slots since we can't rely on the generic code to bring the link up properly. Signed-off-by: Oliver O'Halloran --- core/pci-opal.c | 187 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 127 insertions(+), 60 deletions(-) diff --git a/core/pci-opal.c b/core/pci-opal.c index d7abb15b2bad..68406f3b31ba 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -709,7 +709,7 @@ static int64_t opal_pci_get_power_state(uint64_t id, uint64_t data) } opal_call(OPAL_PCI_GET_POWER_STATE, opal_pci_get_power_state, 2); -static void set_power_timer(struct timer *t __unused, void *data, +static void link_up_timer(struct timer *t __unused, void *data, uint64_t now __unused) { struct pci_slot *slot = data; @@ -717,57 +717,118 @@ static void set_power_timer(struct timer *t __unused, void *data, struct pci_device *pd = slot->pd; struct dt_node *dn = pd->dn; uint8_t link; + int64_t rc = OPAL_BUSY; - switch (slot->state) { - case PCI_SLOT_STATE_SPOWER_START: - if (slot->retries-- == 0) { - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, - slot->async_token, dn->phandle, - slot->power_state, OPAL_BUSY); - } else { - schedule_timer(&slot->timer, msecs_to_tb(10)); - } + /* + * PHB slots need to run throught their link up/down procedure + * in order to work, so... let that happen. + * + * NB: We don't decrement retries here since we the PHB slot + * does its own retry accounting. + */ + rc = slot->ops.run_sm(slot); + if (rc < 0) // error, abort + goto done; + if (rc > 0 && slot->retries-- <= 0) // timeout, abort + goto done; + if (rc > 0) { // kick the can down the road + schedule_timer(t, msecs_to_tb(10)); + return; + } - break; - case PCI_SLOT_STATE_SPOWER_DONE: - if (slot->power_state == OPAL_PCI_SLOT_POWER_OFF) { - pci_remove_bus(phb, &pd->children); - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, - slot->async_token, dn->phandle, - OPAL_PCI_SLOT_POWER_OFF, OPAL_SUCCESS); - break; - } + if (slot->ops.get_link_state(slot, &link) != OPAL_SUCCESS) + link = 0; + if (link) { + prerror("scanning slot...\n"); + slot->ops.prepare_link_change(slot, true); - /* Power on */ - if (slot->ops.get_link_state(slot, &link) != OPAL_SUCCESS) - link = 0; - if (link) { - slot->ops.prepare_link_change(slot, true); - pci_scan_bus(phb, pd->secondary_bus, - pd->subordinate_bus, - &pd->children, pd, true); - pci_add_device_nodes(phb, &pd->children, dn, - &phb->lstate, 0); - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, - slot->async_token, dn->phandle, - OPAL_PCI_SLOT_POWER_ON, OPAL_SUCCESS); - } else if (slot->retries-- == 0) { - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, - slot->async_token, dn->phandle, - OPAL_PCI_SLOT_POWER_ON, OPAL_BUSY); - } else { + pci_scan_bus(phb, pd->secondary_bus, + pd->subordinate_bus, + &pd->children, pd, true); + pci_add_device_nodes(phb, &pd->children, dn, + &phb->lstate, 0); + } + +done: + /* + * We need to send a completion message back to the kernel, otherwise + * it'll sit there forever. + */ + pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); + + opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, + slot->async_token, dn->phandle, + slot->power_state, rc <= 0 ? rc : OPAL_BUSY); + prerror("sent competition state = %lld from %s\n", rc, __func__); +} + +static void set_power_timer(struct timer *t, void *data, uint64_t now) +{ + struct pci_slot *slot = data; + //struct phb *phb = slot->phb; + struct pci_device *pd = slot->pd; + struct dt_node *dn = pd->dn; + //uint8_t link; + struct phb *phb = slot->phb; + int64_t rc = OPAL_BUSY; + + /* XXX: Do we need to take the phb lock here? */ + + prlog(PR_TRACE, "%s: state = %x, retries: %lld, link_retries: %lld\n", + __func__, slot->state, slot->retries, slot->link_retries); + + // FIXME: We should do something better than just calling it repeatedly, + // a seperate poll_power_state() function might be a better thing. + // Maybe have get_power_state() return the in-progress thing. + rc = slot->ops.set_power_state(slot, slot->power_state); + + /* error occured! oh no! */ + if (rc < OPAL_SUCCESS) + goto done; + if (rc > OPAL_SUCCESS) { + if (slot->retries) { + slot->retries--; schedule_timer(&slot->timer, msecs_to_tb(10)); + return; + } else { + goto done; } + } - break; - default: - prlog(PR_ERR, "PCI SLOT %016llx: Unexpected state 0x%08x\n", - slot->id, slot->state); + /* + * In the power off case we're done, so notify the OS + * + * FIXME: We should probably do something to put the slot back into + * the POLLING state or something... + */ + if (slot->power_state == OPAL_PCI_SLOT_POWER_OFF) { + pci_remove_bus(phb, &pd->children); + rc = OPAL_SUCCESS; + goto done; } + + /* + * In the power up case run through the FRESET handler. This is hella + * dumb and we need to do something less stupid in future. + */ + pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL); + + // switch to using the link poll timer + init_timer(&slot->timer, link_up_timer, slot); + link_up_timer(t, data, now); + + return; +done: + /* + * We need to send a completion message back to the kernel, otherwise + * it'll sit there forever. + */ + pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); + + opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, + slot->async_token, dn->phandle, + slot->power_state, rc <= 0 ? rc : OPAL_BUSY); + prerror("sent competition state = %lld from %s\n", rc, __func__); } static int64_t opal_pci_set_power_state(uint64_t async_token, @@ -834,25 +895,31 @@ static int64_t opal_pci_set_power_state(uint64_t async_token, } /* - * OPAL_ASYNC_COMPLETION is returned when delay is needed to change - * the power state in the backend. When it can be finished without - * delay, OPAL_SUCCESS is returned. The PCI topology needs to be - * updated in both cases. + * set_power_state returning > 0 indicates we need to wait + * a bit, so setup a timer and return ASYNC_COMPLETION. + * + * FIXME: Use the wait information set_power_state returns. */ - if (rc == OPAL_ASYNC_COMPLETION) { + if (rc > 0) { slot->retries = 500; init_timer(&slot->timer, set_power_timer, slot); schedule_timer(&slot->timer, msecs_to_tb(10)); - } else if (rc == OPAL_SUCCESS) { - if (*state == OPAL_PCI_SLOT_POWER_OFF) { - pci_remove_bus(phb, &pd->children); - } else { - slot->ops.prepare_link_change(slot, true); - pci_scan_bus(phb, pd->secondary_bus, - pd->subordinate_bus, &pd->children, pd, true); - pci_add_device_nodes(phb, &pd->children, pd->dn, - &phb->lstate, 0); - } + rc = OPAL_ASYNC_COMPLETION; + } + if (rc != OPAL_SUCCESS) { + phb_unlock(phb); + return rc; + } + + /* Otherwise scan the slot so we have the new device in the DT */ + if (*state == OPAL_PCI_SLOT_POWER_ON) { + slot->ops.prepare_link_change(slot, true); + pci_scan_bus(phb, pd->secondary_bus, + pd->subordinate_bus, &pd->children, pd, true); + pci_add_device_nodes(phb, &pd->children, pd->dn, + &phb->lstate, 0); + } else { + pci_remove_bus(phb, &pd->children); } phb_unlock(phb); From patchwork Wed Apr 3 09:09:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0gY1vXNz9sS3 for ; Wed, 3 Apr 2019 20:11:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 03 Apr 2019 02:09:42 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:42 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:01 +1100 Message-Id: <20190403090920.362-5-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 04/23] core/pci: Convert set_power_state X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Oliver O'Halloran --- core/pci.c | 55 ++++++++++++++++-------------------------------------- 1 file changed, 16 insertions(+), 39 deletions(-) diff --git a/core/pci.c b/core/pci.c index a20268b18e1e..c1959197d06d 100644 --- a/core/pci.c +++ b/core/pci.c @@ -365,7 +365,6 @@ static void pci_slot_set_power_state(struct phb *phb, uint8_t state) { struct pci_slot *slot; - uint8_t cur_state; int32_t wait = 100; int64_t rc; @@ -378,58 +377,36 @@ static void pci_slot_set_power_state(struct phb *phb, !slot->ops.set_power_state) return; - if (state == PCI_SLOT_POWER_OFF) { - /* Bail if there're something connected */ - if (!list_empty(&pd->children)) { - PCIERR(phb, pd->bdfn, "Attempted to power off slot with attached devices!\n"); - return; - } - - pci_slot_add_flags(slot, PCI_SLOT_FLAG_BOOTUP); - rc = slot->ops.get_power_state(slot, &cur_state); - if (rc != OPAL_SUCCESS) { - PCINOTICE(phb, pd->bdfn, "Error %lld getting slot power state\n", rc); - cur_state = PCI_SLOT_POWER_OFF; - } - - pci_slot_remove_flags(slot, PCI_SLOT_FLAG_BOOTUP); - if (cur_state == PCI_SLOT_POWER_OFF) - return; + if (state == PCI_SLOT_POWER_OFF && !list_empty(&pd->children)) { + PCIERR(phb, pd->bdfn, "Attempted to power off slot with attached devices!\n"); + return; } pci_slot_add_flags(slot, (PCI_SLOT_FLAG_BOOTUP | PCI_SLOT_FLAG_ENFORCE)); - rc = slot->ops.set_power_state(slot, state); - if (rc == OPAL_SUCCESS) - goto success; - if (rc != OPAL_ASYNC_COMPLETION) { - PCINOTICE(phb, pd->bdfn, "Error %lld powering %s slot\n", - rc, state == PCI_SLOT_POWER_ON ? "on" : "off"); - goto error; - } /* Wait until the operation is completed */ do { - if (slot->state == PCI_SLOT_STATE_SPOWER_DONE) + rc = slot->ops.set_power_state(slot, state); + if (rc <= 0) break; - + time_wait(rc > 10 ? 10 : rc); check_timers(false); - time_wait_ms(10); - } while (--wait >= 0); + } while (--wait); - if (wait < 0) { - PCINOTICE(phb, pd->bdfn, "Timeout powering %s slot\n", - state == PCI_SLOT_POWER_ON ? "on" : "off"); - goto error; + if (!wait && rc >= 0) + rc = OPAL_TIMEOUT; + + if (rc < 0) { + PCIERR(phb, pd->bdfn, "Error %lld powering %s slot\n", + rc, state == PCI_SLOT_POWER_ON ? "on" : "off"); + } else { + PCIDBG(phb, pd->bdfn, "Powered %s hotpluggable slot\n", + state == PCI_SLOT_POWER_ON ? "on" : "off"); } -success: - PCIDBG(phb, pd->bdfn, "Powering %s hotpluggable slot\n", - state == PCI_SLOT_POWER_ON ? "on" : "off"); -error: pci_slot_remove_flags(slot, (PCI_SLOT_FLAG_BOOTUP | PCI_SLOT_FLAG_ENFORCE)); - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); } static int64_t pci_slot_get_link_width(struct pci_slot *slot) From patchwork Wed Apr 3 09:09:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075629 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0gv4F0xz9sSN for ; Wed, 3 Apr 2019 20:11:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="F3ew50sa"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Z0gv160dzDqTh for ; Wed, 3 Apr 2019 20:11:39 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="F3ew50sa"; dkim-atps=neutral Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Z0dl4B6rzDqCl for ; Wed, 3 Apr 2019 20:09:47 +1100 (AEDT) Received: by mail-pf1-x441.google.com with SMTP id y13so7823242pfm.11 for ; Wed, 03 Apr 2019 02:09:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5ssAcvUXc1deVixJTGnNxLzryO4a5Mr/ITwrOU4ZR0I=; b=F3ew50sahAJ+WYnEbZsg21xpgOPP9Q8T2FuVnEG1IbGmwJ+QcSKXrKeL3uBB6cEAPB HIjwqHQJWT7aCVvn6lay2cjm75XTJ+UzjePy3WE2Y04/WgaHClLi/a1saCdl2FRG3Z4B Q77p+xXJVia5bg7M58KTGqtetl99aGHY4UlpPn1CZCn3wok0vxDk/bNEoniTy3bmi2Va 5x+wyKRh+4Zvof0+b2w9Z9nIByp9RUCBK1DDnTMrcVZW3PYNpDlaifHXkqdQCNYTyqR6 DIXeevtjmSCkxx2DpSvAkpWjQwE4fz6H+ERs7dpyRU3kW1+1WEdbvhNUtgP27zAjJ7Kw Qn6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5ssAcvUXc1deVixJTGnNxLzryO4a5Mr/ITwrOU4ZR0I=; b=U6RrkKV0vxVAyB5HD8GhobpqDoyIOZP/l3t9vylbyIHR/w4U2+drfIXNzOYZ8d/KUE Dp4jrvegI5+H37rRbaspnVnXRssaMwe22yyZNmIJKSHSMS7SSSdejibfpYOl2r1MK3pM SjF7VqP6ou+QNlPXol821FYv4xMdnpaEiWx+CvPkKXOyaD3WAq9ME6ZZGhCA4p+ttXkL fJp2JwPUPlyXPhaqWsm3uqoj3GpzTXUjcpQpiSw3KJes+nna3Cpb87LHqX6tvgugyCFy hEwrsAjr9ybN08nT6ylceysQ1dXRr8sxQJ/19k8uQ+Z9rmrqVtrstJtmWTI4R13f65bd xDrw== X-Gm-Message-State: APjAAAURGRmVwashUL5bOUwE4WVmR69ZSRQ0NDriPZBJK4ZlRyVubGEk zoZz+hO/6xden3jGhNoDRNWVhQou X-Google-Smtp-Source: APXvYqz3khsAINghZyBThd1crN6vB8+bD3gT80U2SKg4CJPeoioR89vbmBbe8F2PlgdlZgCtuaxqGA== X-Received: by 2002:a63:ef09:: with SMTP id u9mr8412761pgh.126.1554282584990; Wed, 03 Apr 2019 02:09:44 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:44 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:02 +1100 Message-Id: <20190403090920.362-6-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 05/23] core/pci-slot: Add assert_perst() operation X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a seperate slot operation to control a PCI slot's PERST signal. This is to allow generic code to perform a fundemental reset of the slot without needing to know any hardware (or platform) specific details about the slot. Signed-off-by: Oliver O'Halloran --- include/pci-slot.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci-slot.h b/include/pci-slot.h index ac1cfbef8f46..cb36d7b6df5a 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -102,6 +102,7 @@ struct pci_slot_ops { int64_t (*get_latch_state)(struct pci_slot *slot, uint8_t *val); int64_t (*set_power_state)(struct pci_slot *slot, uint8_t val); int64_t (*set_attention_state)(struct pci_slot *slot, uint8_t val); + int64_t (*assert_perst)(struct pci_slot *slot, bool val); /* SM based functions for reset */ void (*prepare_link_change)(struct pci_slot *slot, bool is_up); From patchwork Wed Apr 3 09:09:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075630 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0h92yRJz9sSJ for ; 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Wed, 03 Apr 2019 02:09:46 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:03 +1100 Message-Id: <20190403090920.362-7-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 06/23] core/pci-slot: Add pci_slot_generic_freset() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a generic function that can use the assert_perst() and set_power_state() slot operations to do fundemental reset of the slot. Signed-off-by: Oliver O'Halloran --- core/pci-slot.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ hw/phb4.c | 5 ++-- include/pci-slot.h | 6 ++++ 3 files changed, 81 insertions(+), 2 deletions(-) diff --git a/core/pci-slot.c b/core/pci-slot.c index 497d0a47f426..14dd95ec0dd1 100644 --- a/core/pci-slot.c +++ b/core/pci-slot.c @@ -19,6 +19,7 @@ #include #include #include +#include /* Debugging options */ #define PCI_SLOT_PREFIX "PCI-SLOT-%016llx " @@ -114,6 +115,77 @@ static int64_t pci_slot_run_sm(struct pci_slot *slot) return ret; } +int64_t pci_slot_generic_freset(struct pci_slot *slot) +{ + uint16_t bdfn = slot->pd ? slot->pd->bdfn : 0; + struct phb *phb = slot->phb; + int64_t rc; + + /* We need atleast one of them to do an FRESET */ + assert(slot->ops.set_power_state || slot->ops.assert_perst); + // not strictly required... + assert(slot->ops.prepare_link_change); + + switch(slot->state) { + case PCI_SLOT_STATE_NORMAL: + case PCI_SLOT_FRESET_START: + PCIERR(phb, bdfn, "FRESET: Prepare for link down\n"); + + // FIXME: Handle errors + if (slot->ops.prepare_link_change) + slot->ops.prepare_link_change(slot, false); + if (slot->ops.assert_perst) + slot->ops.assert_perst(slot, true); + + /* + * If we don't have power control then skip those states + * and go straight to de-assert after 250ms. + */ + if (!slot->ops.set_power_state) { + pci_slot_set_state(slot, PCI_SLOT_FRESET_LIFT_PERST); + return pci_slot_set_sm_timeout(slot, msecs_to_tb(250)); + } + + pci_slot_set_state(slot, PCI_SLOT_FRESET_POWER_OFF); + + /* fallthrough */ + case PCI_SLOT_FRESET_POWER_OFF: + rc = slot->ops.set_power_state(slot, PCI_SLOT_POWER_OFF); + if (rc > 0) + return pci_slot_set_sm_timeout(slot, msecs_to_tb(rc)); + /* XXX: error handling */ + + /* leave power off for 250ms before turning the slot back on */ + PCIERR(phb, bdfn, "FRESET: Slot powered off\n"); + pci_slot_set_state(slot, PCI_SLOT_FRESET_POWER_ON); + return pci_slot_set_sm_timeout(slot, msecs_to_tb(250)); + + case PCI_SLOT_FRESET_POWER_ON: + rc = slot->ops.set_power_state(slot, PCI_SLOT_POWER_ON); + if (rc > 0) + return pci_slot_set_sm_timeout(slot, msecs_to_tb(rc)); + /* XXX: error handling */ + PCIERR(phb, bdfn, "FRESET: Slot powered on\n"); + + /* fallthrough */ + case PCI_SLOT_FRESET_LIFT_PERST: + PCIDBG(phb, bdfn, "FRESET: Deassert\n"); + if (slot->ops.assert_perst) + slot->ops.assert_perst(slot, false); + + pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL); + return slot->ops.poll_link(slot); + default: + PCIERR(phb, bdfn, "Unexpected slot state %08x\n", slot->state); + } + + PCIERR(phb, bdfn, "Uhh how did we get here???\n"); + backtrace(); + pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); + + return OPAL_HARDWARE; +} + void pci_slot_add_dt_properties(struct pci_slot *slot, struct dt_node *np) { diff --git a/hw/phb4.c b/hw/phb4.c index bcd998d910af..591872c31c02 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2939,6 +2939,9 @@ static void phb4_assert_perst(struct pci_slot *slot, bool assert) } else { linkctl &= ~PCICAP_EXP_LCTL_LINK_DIS; reg |= PHB_PCIE_CRESET_PERST_N; + + /* Clear link errors before we deassert PERST */ + phb4_err_clear_regb(p); } out_be64(p->regs + PHB_PCIE_CRESET, reg); @@ -3034,8 +3037,6 @@ static int64_t phb4_freset(struct pci_slot *slot) p->skip_perst = false; /* fall through */ case PHB4_SLOT_FRESET_ASSERT_DELAY: - /* Clear link errors before we deassert PERST */ - phb4_err_clear_regb(p); if (pci_tracing) { /* Enable tracing */ diff --git a/include/pci-slot.h b/include/pci-slot.h index cb36d7b6df5a..fec11ccf46c2 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -134,6 +134,10 @@ struct pci_slot_ops { #define PCI_SLOT_STATE_HRESET_HOLD (PCI_SLOT_STATE_HRESET + 2) #define PCI_SLOT_STATE_FRESET 0x00000300 #define PCI_SLOT_STATE_FRESET_POWER_OFF (PCI_SLOT_STATE_FRESET + 1) +#define PCI_SLOT_FRESET_START (PCI_SLOT_STATE_FRESET + 1) +#define PCI_SLOT_FRESET_POWER_OFF (PCI_SLOT_STATE_FRESET + 2) +#define PCI_SLOT_FRESET_POWER_ON (PCI_SLOT_STATE_FRESET + 3) +#define PCI_SLOT_FRESET_LIFT_PERST (PCI_SLOT_STATE_FRESET + 4) #define PCI_SLOT_STATE_CRESET 0x00000400 #define PCI_SLOT_STATE_CRESET_START (PCI_SLOT_STATE_CRESET + 1) #define PCI_SLOT_STATE_GPOWER 0x00000500 @@ -282,6 +286,8 @@ extern struct pci_slot *pci_slot_find(uint64_t id); extern void pci_slot_add_loc(struct pci_slot *slot, struct dt_node *np, const char *label); +int64_t pci_slot_generic_freset(struct pci_slot *slot); + /* DT based slot map */ extern struct dt_node *dt_slots; From patchwork Wed Apr 3 09:09:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0hR6g0Qz9sSJ for ; Wed, 3 Apr 2019 20:12:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 03 Apr 2019 02:09:48 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:48 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:04 +1100 Message-Id: <20190403090920.362-8-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 07/23] core/pci-slot: add power_ctl_state X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a state variable for tracking where the set_power_state() function is in the process of powering on the slot. Signed-off-by: Oliver O'Halloran --- We probably want a timer, etc similar to what we have the for slot reset state machine. --- include/pci-slot.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/pci-slot.h b/include/pci-slot.h index fec11ccf46c2..9299ffae92e8 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -181,6 +181,9 @@ struct pci_slot { uint64_t async_token; uint8_t power_state; + /* used by the set_power_state() function */ + uint8_t power_ctl_state; + /* Slot information */ uint8_t pluggable; uint8_t surprise_pluggable; From patchwork Wed Apr 3 09:09:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0hh2Ktsz9sSM for ; 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Wed, 03 Apr 2019 02:09:50 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:05 +1100 Message-Id: <20190403090920.362-9-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 08/23] core/pcie-slot: Use pci_slot_generic_freset() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Switch to the generic method and remove the pcie slot specific one. Signed-off-by: Oliver O'Halloran --- core/pcie-slot.c | 50 +----------------------------------------------- 1 file changed, 1 insertion(+), 49 deletions(-) diff --git a/core/pcie-slot.c b/core/pcie-slot.c index 0ed903501178..213740a683c7 100644 --- a/core/pcie-slot.c +++ b/core/pcie-slot.c @@ -411,54 +411,6 @@ static int64_t pcie_slot_sm_hreset(struct pci_slot *slot) return OPAL_HARDWARE; } -/* - * Usually, individual platforms need to override the power - * management methods for fundamental reset, but the hot - * reset method is commonly shared. - */ -static int64_t pcie_slot_sm_freset(struct pci_slot *slot) -{ - uint8_t power_state = PCI_SLOT_POWER_ON; - - switch (slot->state) { - case PCI_SLOT_STATE_NORMAL: - PCIE_SLOT_DBG(slot, "FRESET: Starts\n"); - if (slot->ops.prepare_link_change) - slot->ops.prepare_link_change(slot, false); - - /* Retrieve power state */ - if (slot->ops.get_power_state) { - PCIE_SLOT_DBG(slot, "FRESET: Retrieve power state\n"); - slot->ops.get_power_state(slot, &power_state); - } - - /* In power on state, power it off */ - if (power_state == PCI_SLOT_POWER_ON) { - PCIE_SLOT_DBG(slot, "FRESET: Power is on, turn off\n"); - pcie_slot_set_power_state_ext(slot, - PCI_SLOT_POWER_OFF, false); - pci_slot_set_state(slot, - PCI_SLOT_STATE_FRESET_POWER_OFF); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(50)); - } - /* No power state change, */ - /* fallthrough */ - case PCI_SLOT_STATE_FRESET_POWER_OFF: - PCIE_SLOT_DBG(slot, "FRESET: Power is off, turn on\n"); - pcie_slot_set_power_state_ext(slot, PCI_SLOT_POWER_ON, false); - - pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(50)); - default: - prlog(PR_ERR, PCIE_SLOT_PREFIX - "FRESET: Unexpected slot state %08x\n", - slot->id, slot->state); - } - - pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - return OPAL_HARDWARE; -} - struct pci_slot *pcie_slot_create(struct phb *phb, struct pci_device *pd) { struct pci_slot *slot; @@ -540,7 +492,7 @@ struct pci_slot *pcie_slot_create(struct phb *phb, struct pci_device *pd) */ slot->ops.poll_link = pcie_slot_sm_poll_link; slot->ops.hreset = pcie_slot_sm_hreset; - slot->ops.freset = pcie_slot_sm_freset; + slot->ops.freset = pci_slot_generic_freset; slot->wired_lanes = PCI_SLOT_WIRED_LANES_UNKNOWN; slot->connector_type = PCI_SLOT_CONNECTOR_PCIE_NS; From patchwork Wed Apr 3 09:09:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0hz5lSMz9sSJ for ; Wed, 3 Apr 2019 20:12:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 03 Apr 2019 02:09:53 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:52 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:06 +1100 Message-Id: <20190403090920.362-10-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 09/23] core/pcie-slot: Remove wait hack X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Now that all the users of slot->ops.set_power_state() have been converted to expect either OPAL_SUCCESS or a wait time we cna remove the synchrnous wait hack. Signed-off-by: Oliver O'Halloran --- core/pcie-slot.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/core/pcie-slot.c b/core/pcie-slot.c index 213740a683c7..b368e5496fab 100644 --- a/core/pcie-slot.c +++ b/core/pcie-slot.c @@ -206,6 +206,9 @@ static int64_t pcie_slot_set_attention_state(struct pci_slot *slot, return OPAL_SUCCESS; } +#define PCIE_SLOT_POWER_IDLE 0 /* Ready to accept another power control cmd */ +#define PCIE_SLOT_POWER_WAIT 1 /* Waiting for a previous power control cmd */ + static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val, bool surprise_check) { @@ -230,6 +233,11 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val, return OPAL_SUCCESS; } + if (slot->power_ctl_state == PCIE_SLOT_POWER_WAIT) { + slot->power_ctl_state = PCIE_SLOT_POWER_IDLE; + return OPAL_SUCCESS; + } + /* * Suprise hotpluggable slots need to be handled with care since * many systems do not implement the presence detect side-band @@ -256,6 +264,9 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val, */ } + + slot->power_ctl_state = PCIE_SLOT_POWER_WAIT; + slot->power_state = val; ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false); pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state); @@ -275,13 +286,7 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val, pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state); - /* - * HACK: wait a bit for the link to come up. Drop this once we've - * converted users of set_power_state to use the new interface - */ - time_wait_ms(10); - - return OPAL_SUCCESS; + return 10; } static int64_t pcie_slot_set_power_state(struct pci_slot *slot, uint8_t val) From patchwork Wed Apr 3 09:09:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0jG6Mqlz9sPF for ; Wed, 3 Apr 2019 20:12:50 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WRH4inCK"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Z0jG59RSzDqRr for ; Wed, 3 Apr 2019 20:12:50 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WRH4inCK"; dkim-atps=neutral Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Z0dw6GwZzDqRb for ; Wed, 3 Apr 2019 20:09:56 +1100 (AEDT) Received: by mail-pg1-x544.google.com with SMTP id 85so8000581pgc.3 for ; Wed, 03 Apr 2019 02:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9M1RD6ZMbI5IjW1N5p0I4n458+yWl4mBOFc7hRJuBlM=; b=WRH4inCKc8bO4oXkczllPZDYChOQCrRDKWzRDYxz90UkQUTrWrWU8ZQ5UNCZDRmaPy H2CPpK0n409zo6BtYldK1GX3JzZHUIyPiUSX2apV9yuKad+g4zuJ9jZfSCa+A6a/y5X8 +EYYFr2rEiOgVwk7nzIvaecMcpdiu5Aupc3Ez+PsZPMy67gD9PcrRTyeOUAC2xWyJql0 CLMJFDn0u9+XMCXSuFFtoj9GZwPKP6IWUD1bwxm03zPAVD2eJoVI26RLFzDynPtTcc9B z5vkJyOzqoX5YYNqAnrRE1ZJzun2D5T4GwdJa7uwfJQAUGv42bjy1oVxn+i6xh6+wy6v Uugg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9M1RD6ZMbI5IjW1N5p0I4n458+yWl4mBOFc7hRJuBlM=; b=Jo190ODpiboP4dEOFZhnfj4V/4g+2J/DxFZuxaTnOO2JcJA7luITjCB00RxOMGMKXQ RcREO022BDuYhgHLCllj3zO1bNdJgdSnHceFYSd/laEcEXYGHW+1KqjQSDaq8Y4+Biq3 OZS7BAaq7RrW/YdAQWNg1CXEWfxHMTOa3ja5+U1Mw7sx80EXTvQu82RuDOjLdk+a7xaf V9/SkuZIEBIgCk8jTys2nixEbHFfRuozc7Xg0gxx0mmvptMbe+l2c1FajH/cmCubMxJP llX0AXFr5FVraZ/FCEw9E7XOiO8kb9kTiqM6hSk9rR8RAS5b2rSqa1YUsoPEMOqQV2pf jx6w== X-Gm-Message-State: APjAAAVMnAnVE3yMExfBmOAYUMEvnrB4zVwSFBlNgpULpiMcYFq9B9om RMc0KIadCekabBmEkwNvjEXk+4sE X-Google-Smtp-Source: APXvYqzsf9lK6LCckf/UMa8s2XQk2+Kav+rbf+zQ35dtfyF0xPDkeXJL+MiaEIP4hwR1pWqgwd+jJg== X-Received: by 2002:a63:c23:: with SMTP id b35mr31232549pgl.298.1554282595036; Wed, 03 Apr 2019 02:09:55 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:54 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:07 +1100 Message-Id: <20190403090920.362-11-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 10/23] platform/firenze-pci: Convert to new power control API X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert firenze-pci slot control methods to use the new wait API. Signed-off-by: Oliver O'Halloran --- platforms/ibm-fsp/firenze-pci.c | 46 ++++++++++++++++----------------- 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c index 0ed53301485e..36414425e80d 100644 --- a/platforms/ibm-fsp/firenze-pci.c +++ b/platforms/ibm-fsp/firenze-pci.c @@ -363,18 +363,6 @@ bail: static int64_t __unused firenze_pci_slot_get_power_state(struct pci_slot *slot, uint8_t *val) { - if (slot->state != FIRENZE_PCI_SLOT_NORMAL) - { - /** - * @fwts-label FirenzePCISlotGPowerState - * @fwts-advice Unexpected state in the FIRENZE PCI Slot - * state machine. This could mean PCI is not functioning - * correctly. - */ - prlog(PR_ERR, "%016llx GPOWER: Unexpected state %08x\n", - slot->id, slot->state); - } - *val = slot->power_state; return OPAL_SUCCESS; } @@ -385,18 +373,27 @@ static int64_t __unused firenze_pci_slot_set_power_state(struct pci_slot *slot, struct firenze_pci_slot *plat_slot = slot->data; uint8_t *pval; - if (slot->state != FIRENZE_PCI_SLOT_NORMAL) - { - /** - * @fwts-label FirenzePCISlotSPowerState - * @fwts-advice Unexpected state in the FIRENZE PCI Slot - * state machine. This could mean PCI is not functioning - * correctly. - */ - prlog(PR_ERR, "%016llx SPOWER: Unexpected state %08x\n", - slot->id, slot->state); + /* check if we have an in-progress i2c operation happening */ + if (slot->power_ctl_state) { + struct i2c_request *req = plat_slot->req; + + prerror("request state: %d\n", req->req_state); + + switch (req->req_state) { + case i2c_req_done: + req->req_state = i2c_req_new; + slot->power_ctl_state = 0; + printf("req result: %d\n", req->result); + return req->result; + case i2c_req_queued: + return 10; // FIXME: Do proper timeout handling, christ + case i2c_req_new: + prerror("u wot m8?\n"); + } } + // otherwise, queue the i2c request to change the power state + if (val != PCI_SLOT_POWER_OFF && val != PCI_SLOT_POWER_ON) return OPAL_PARAMETER; @@ -416,7 +413,6 @@ static int64_t __unused firenze_pci_slot_set_power_state(struct pci_slot *slot, } slot->power_state = val; - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_SPOWER_START); plat_slot->req->op = SMBUS_WRITE; pval = (uint8_t *)plat_slot->req->rw_buf; @@ -436,7 +432,9 @@ static int64_t __unused firenze_pci_slot_set_power_state(struct pci_slot *slot, plat_slot->req->timeout = 0ul; i2c_queue_req(plat_slot->req); - return OPAL_ASYNC_COMPLETION; + slot->power_ctl_state = 1; + + return 10; } static struct i2c_bus *firenze_pci_find_i2c_bus(uint8_t chip, From patchwork Wed Apr 3 09:09:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075637 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0jX10cwz9sNF for ; Wed, 3 Apr 2019 20:13:04 +1100 (AEDT) Authentication-Results: ozlabs.org; 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Wed, 03 Apr 2019 02:09:57 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:56 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:08 +1100 Message-Id: <20190403090920.362-12-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 11/23] platform/firenze-pci: Use generic freset method X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" For slots where we have power control we can use the generic FRESET method. Signed-off-by: Oliver O'Halloran --- platforms/ibm-fsp/firenze-pci.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c index 36414425e80d..3221ba92a83d 100644 --- a/platforms/ibm-fsp/firenze-pci.c +++ b/platforms/ibm-fsp/firenze-pci.c @@ -360,14 +360,32 @@ bail: firenze_inv_cnt = 0; } -static int64_t __unused firenze_pci_slot_get_power_state(struct pci_slot *slot, +static int64_t firenze_pci_inband_perst(struct pci_slot *slot, + bool val) +{ + struct firenze_pci_slot *plat_slot = slot->data; + uint16_t ctrl, bdfn = slot->pd->bdfn; + + pci_cfg_read16(slot->phb, bdfn, plat_slot->perst_reg, &ctrl); + + if (val) + ctrl |= plat_slot->perst_bit; + else + ctrl &= ~plat_slot->perst_bit; + + pci_cfg_write16(slot->phb, bdfn, plat_slot->perst_reg, ctrl); + + return OPAL_SUCCESS; +} + +static int64_t firenze_pci_slot_get_power_state(struct pci_slot *slot, uint8_t *val) { *val = slot->power_state; return OPAL_SUCCESS; } -static int64_t __unused firenze_pci_slot_set_power_state(struct pci_slot *slot, +static int64_t firenze_pci_slot_set_power_state(struct pci_slot *slot, uint8_t val) { struct firenze_pci_slot *plat_slot = slot->data; @@ -644,6 +662,9 @@ static void firenze_pci_slot_init(struct pci_slot *slot) */ if (plat_slot->req) { /* placeholder */ + slot->ops.freset = pci_slot_generic_freset; + slot->ops.get_power_state = firenze_pci_slot_get_power_state; + slot->ops.set_power_state = firenze_pci_slot_set_power_state; prlog(PR_DEBUG, "%016llx: External power mgt initialized\n", slot->id); } else if (info->inband_perst) { From patchwork Wed Apr 3 09:09:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075638 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0js3sXmz9sNF for ; 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Wed, 03 Apr 2019 02:09:58 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:09 +1100 Message-Id: <20190403090920.362-13-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 12/23] platform/firenze-pci: Use inband perst when possible X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Oliver O'Halloran --- platforms/ibm-fsp/firenze-pci.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c index 3221ba92a83d..fa808244c2bd 100644 --- a/platforms/ibm-fsp/firenze-pci.c +++ b/platforms/ibm-fsp/firenze-pci.c @@ -669,20 +669,26 @@ static void firenze_pci_slot_init(struct pci_slot *slot) slot->id); } else if (info->inband_perst) { /* - * For PLX downstream ports, PCI config register can be - * leveraged to do PERST. If the slot doesn't have external - * power management stuff, lets try to stick to the PERST - * logic if applicable + * For PLX downstream ports the slot doesn't have actual power + * control, but the switch will still assert PERST when "power" + * is disabled via the slot power control bit. We can make use + * of that to PERST cards under the switch. */ if (slot->pd->dev_type == PCIE_TYPE_SWITCH_DNPORT) { + uint32_t ecap = pci_cap(slot->pd, PCI_CFG_CAP_ID_EXP, + false); + pci_cfg_read32(slot->phb, slot->pd->bdfn, PCI_CFG_VENDOR_ID, &vdid); switch (vdid) { case 0x873210b5: /* PLX8732 */ case 0x874810b5: /* PLX8748 */ - plat_slot->perst_reg = 0x80; - plat_slot->perst_bit = 0x0400; - /* placeholder */ + plat_slot->perst_reg = + ecap + PCICAP_EXP_SLOTCTL; + plat_slot->perst_bit = + PCICAP_EXP_SLOTCTL_PWRCTLR; + slot->ops.assert_perst = + firenze_pci_inband_perst; break; } } From patchwork Wed Apr 3 09:09:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075639 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0k566l3z9sNF for ; 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Wed, 03 Apr 2019 02:10:00 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:10 +1100 Message-Id: <20190403090920.362-14-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 13/23] hw/phb3: Add phb3_assert_perst() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Wire it up. Signed-off-by: Oliver O'Halloran --- hw/phb3.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index ee98fd51dd79..095fc3153378 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2399,11 +2399,29 @@ static int64_t phb3_hreset(struct pci_slot *slot) return OPAL_HARDWARE; } +static int64_t phb3_assert_perst(struct pci_slot *slot, bool assert) +{ + struct phb3 *p = phb_to_phb3(slot->phb); + uint64_t reg; + + /* + * PPCBIT(2) of PHB_RESET drives PERST directly so we *clear* + * it to assert PERST. + */ + reg = in_be64(p->regs + PHB_RESET); + if (assert) + reg &= ~0x2000000000000000ul; + else + reg |= 0x2000000000000000ul; + out_be64(p->regs + PHB_RESET, reg); + + return OPAL_SUCCESS; +} + static int64_t phb3_freset(struct pci_slot *slot) { struct phb3 *p = phb_to_phb3(slot->phb); uint8_t presence = 1; - uint64_t reg; switch(slot->state) { case PHB3_SLOT_NORMAL: @@ -2425,9 +2443,7 @@ static int64_t phb3_freset(struct pci_slot *slot) case PHB3_SLOT_FRESET_START: if (!p->skip_perst) { PHBDBG(p, "FRESET: Assert\n"); - reg = in_be64(p->regs + PHB_RESET); - reg &= ~0x2000000000000000ul; - out_be64(p->regs + PHB_RESET, reg); + phb3_assert_perst(slot, true); pci_slot_set_state(slot, PHB3_SLOT_FRESET_ASSERT_DELAY); return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); @@ -2440,9 +2456,7 @@ static int64_t phb3_freset(struct pci_slot *slot) /* fall through */ case PHB3_SLOT_FRESET_ASSERT_DELAY: PHBDBG(p, "FRESET: Deassert\n"); - reg = in_be64(p->regs + PHB_RESET); - reg |= 0x2000000000000000ul; - out_be64(p->regs + PHB_RESET, reg); + phb3_assert_perst(slot, false); pci_slot_set_state(slot, PHB3_SLOT_FRESET_DEASSERT_DELAY); From patchwork Wed Apr 3 09:09:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0kN0jdgz9sPF for ; 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Wed, 03 Apr 2019 02:10:02 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:11 +1100 Message-Id: <20190403090920.362-15-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 14/23] hw/phb3: Wire up assert_perst X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The pcie-slot specific method is largely pointless now. --- hw/phb3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/phb3.c b/hw/phb3.c index 095fc3153378..4ac6aa729c4d 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2742,6 +2742,7 @@ static struct pci_slot *phb3_slot_create(struct phb *phb) slot->ops.get_latch_state = NULL; slot->ops.set_power_state = NULL; slot->ops.set_attention_state = NULL; + slot->ops.assert_perst = phb3_assert_perst; /* * For PHB slots, we have to split the fundamental reset From patchwork Wed Apr 3 09:09:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075641 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0kd6Y0Hz9sNF for ; Wed, 3 Apr 2019 20:14:01 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XWXlpe+D"; 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Wed, 03 Apr 2019 02:10:04 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.10.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:10:04 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:12 +1100 Message-Id: <20190403090920.362-16-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 15/23] hw/phb3: Convert to generic FRESET X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" NB: This removes the 1s wait after lifting PERST. This wait was added to allow some FPGA cards time to flash their bitstream since the PCIe interface would not be enabled until the image was flashed. We has since extended the time we spend waiting for an electrical link to 1s so this wait should not be necessary any longer. Signed-off-by: Oliver O'Halloran --- Tested on p83 with an Altera FPGA card with a CAPI image. Seems to work just fine... --- hw/phb3.c | 57 +------------------------------------------------------ 1 file changed, 1 insertion(+), 56 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index 4ac6aa729c4d..d86fb74bbbf9 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2418,61 +2418,6 @@ static int64_t phb3_assert_perst(struct pci_slot *slot, bool assert) return OPAL_SUCCESS; } -static int64_t phb3_freset(struct pci_slot *slot) -{ - struct phb3 *p = phb_to_phb3(slot->phb); - uint8_t presence = 1; - - switch(slot->state) { - case PHB3_SLOT_NORMAL: - PHBDBG(p, "FRESET: Starts\n"); - - /* Nothing to do without adapter connected */ - if (slot->ops.get_presence_state) - slot->ops.get_presence_state(slot, &presence); - if (!presence) { - PHBDBG(p, "FRESET: No device\n"); - return OPAL_SUCCESS; - } - - PHBDBG(p, "FRESET: Prepare for link down\n"); - slot->retry_state = PHB3_SLOT_FRESET_START; - if (slot->ops.prepare_link_change) - slot->ops.prepare_link_change(slot, false); - /* fall through */ - case PHB3_SLOT_FRESET_START: - if (!p->skip_perst) { - PHBDBG(p, "FRESET: Assert\n"); - phb3_assert_perst(slot, true); - pci_slot_set_state(slot, - PHB3_SLOT_FRESET_ASSERT_DELAY); - return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); - } - - /* To skip the assert during boot time */ - PHBDBG(p, "FRESET: Assert skipped\n"); - pci_slot_set_state(slot, PHB3_SLOT_FRESET_ASSERT_DELAY); - p->skip_perst = false; - /* fall through */ - case PHB3_SLOT_FRESET_ASSERT_DELAY: - PHBDBG(p, "FRESET: Deassert\n"); - phb3_assert_perst(slot, false); - pci_slot_set_state(slot, - PHB3_SLOT_FRESET_DEASSERT_DELAY); - - /* CAPP FPGA requires 1s to flash before polling link */ - return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); - case PHB3_SLOT_FRESET_DEASSERT_DELAY: - pci_slot_set_state(slot, PHB3_SLOT_LINK_START); - return slot->ops.poll_link(slot); - default: - PHBERR(p, "Unexpected slot state %08x\n", slot->state); - } - - pci_slot_set_state(slot, PHB3_SLOT_NORMAL); - return OPAL_HARDWARE; -} - static int64_t load_capp_ucode(struct phb3 *p) { int64_t rc; @@ -2753,7 +2698,7 @@ static struct pci_slot *phb3_slot_create(struct phb *phb) slot->ops.prepare_link_change = phb3_prepare_link_change; slot->ops.poll_link = phb3_poll_link; slot->ops.hreset = phb3_hreset; - slot->ops.freset = phb3_freset; + slot->ops.freset = pci_slot_generic_freset; slot->ops.creset = phb3_creset; return slot; From patchwork Wed Apr 3 09:09:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0kv3Yfzz9sNF for ; Wed, 3 Apr 2019 20:14:15 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 03 Apr 2019 02:10:06 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.10.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:10:06 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:13 +1100 Message-Id: <20190403090920.362-17-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 16/23] hw/phb4: Something to do with link retries, dunno if required X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" --- hw/phb4.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 591872c31c02..c63e916da0b7 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2368,6 +2368,7 @@ static int64_t phb4_retry_state(struct pci_slot *slot) return OPAL_HARDWARE; } + slot->link_retries--; pci_slot_set_state(slot, PHB4_SLOT_CRESET_START); return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); } @@ -2856,7 +2857,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot) PHBDBG(p, "LINK: Link is stable\n"); if (!phb4_link_optimal(slot, &vdid)) { PHBDBG(p, "LINK: Link degraded\n"); - if (slot->link_retries) { + if (slot->link_retries > 0) { phb4_lane_eq_change(p, vdid); return phb4_retry_state(slot); } From patchwork Wed Apr 3 09:09:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0lB2TFRz9sNF for ; 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Wed, 03 Apr 2019 02:10:08 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:14 +1100 Message-Id: <20190403090920.362-18-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 17/23] hw/phb4: Move link tracing into poll_link() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently when we bring the link up we'll stay in the and the link training trace is enabled we stay in the FRESET_ASSERT_DELAY state until the link is trained. Although this is not wrong, it does mean that we don't get a link training trace in the HRESET case and it's additional PHB4 specific behavior in the FRESET path. We want to move to a generic FRESET function that correctly deals with power-controlled slots, so this patch moves the link trace into the poll_link() function to handle the HRESET case and make the FRESET path more generic. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index c63e916da0b7..3a6b05b4a5a6 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2789,8 +2789,11 @@ static int64_t phb4_poll_link(struct pci_slot *slot) PHBDBG(p, "LINK: Start polling\n"); slot->retries = PHB4_LINK_ELECTRICAL_RETRIES; pci_slot_set_state(slot, PHB4_SLOT_LINK_WAIT_ELECTRICAL); - /* Polling early here has no chance of a false positive */ - return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); + + if (pci_tracing) + phb4_training_trace(p); + + /* fallthrough */ case PHB4_SLOT_LINK_WAIT_ELECTRICAL: /* * Wait for the link electrical connection to be @@ -3049,8 +3052,6 @@ static int64_t phb4_freset(struct pci_slot *slot) PHBDBG(p, "FRESET: Deassert\n"); phb4_assert_perst(slot, false); - phb4_training_trace(p); - pci_slot_set_state(slot, PHB4_SLOT_LINK_START); return slot->ops.poll_link(slot); default: From patchwork Wed Apr 3 09:09:15 2019 Content-Type: text/plain; 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Wed, 03 Apr 2019 02:10:11 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.10.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:10:10 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:15 +1100 Message-Id: <20190403090920.362-19-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 18/23] hw/phb4: Enable DLP Trace in phb4_init_hw() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Move the link trace enable out of phb4_freset() and into phb4_init_hw(). No functional changes. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 3a6b05b4a5a6..75a1eb45a3d4 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3013,7 +3013,6 @@ static int64_t phb4_hreset(struct pci_slot *slot) static int64_t phb4_freset(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); - uint64_t reg; switch(slot->state) { case PHB4_SLOT_NORMAL: @@ -3042,13 +3041,6 @@ static int64_t phb4_freset(struct pci_slot *slot) /* fall through */ case PHB4_SLOT_FRESET_ASSERT_DELAY: - if (pci_tracing) { - /* Enable tracing */ - reg = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL); - out_be64(p->regs + PHB_PCIE_DLP_TRWCTL, - reg | PHB_PCIE_DLP_TRWCTL_EN); - } - PHBDBG(p, "FRESET: Deassert\n"); phb4_assert_perst(slot, false); @@ -5288,6 +5280,14 @@ static void phb4_init_hw(struct phb4 *p) /* Mark the PHB as functional which enables all the various sequences */ p->broken = false; + /* Enable tracing if needed */ + if (pci_tracing) { + val = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL); + out_be64(p->regs + PHB_PCIE_DLP_TRWCTL, + val | PHB_PCIE_DLP_TRWCTL_EN); + } + + PHBDBG(p, "Initialization complete\n"); return; From patchwork Wed Apr 3 09:09:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075645 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0lp6gRsz9sPF for ; Wed, 3 Apr 2019 20:15:02 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MaHo9lMc"; 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Wed, 03 Apr 2019 02:10:13 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.10.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:10:12 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:16 +1100 Message-Id: <20190403090920.362-20-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 19/23] hw/phb4: Wire up assert_perst() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 75a1eb45a3d4..02dca9e5238f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2921,7 +2921,7 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) return max_link_speed; } -static void phb4_assert_perst(struct pci_slot *slot, bool assert) +static int64_t phb4_assert_perst(struct pci_slot *slot, bool assert) { struct phb4 *p = phb_to_phb4(slot->phb); uint16_t linkctl; @@ -2950,6 +2950,7 @@ static void phb4_assert_perst(struct pci_slot *slot, bool assert) out_be64(p->regs + PHB_PCIE_CRESET, reg); phb4_pcicfg_write16(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, linkctl); + return OPAL_SUCCESS; } static int64_t phb4_hreset(struct pci_slot *slot) @@ -3434,6 +3435,7 @@ static struct pci_slot *phb4_slot_create(struct phb *phb) slot->ops.get_latch_state = NULL; slot->ops.set_power_state = NULL; slot->ops.set_attention_state = NULL; + slot->ops.assert_perst = phb4_assert_perst; /* * For PHB slots, we have to split the fundamental reset From patchwork Wed Apr 3 09:09:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0m4414tz9sNF for ; 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Wed, 03 Apr 2019 02:10:14 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:17 +1100 Message-Id: <20190403090920.362-21-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 20/23] hw/phb4: Convert to generic FRESET X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" At this point phb4_freset doesn't have much real functionality over the generic version, so use the generic version. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 34 ++-------------------------------- 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 02dca9e5238f..99e694059a80 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3018,41 +3018,11 @@ static int64_t phb4_freset(struct pci_slot *slot) switch(slot->state) { case PHB4_SLOT_NORMAL: case PHB4_SLOT_FRESET_START: - PHBDBG(p, "FRESET: Starts\n"); - - /* Reset max link speed for training */ p->max_link_speed = phb4_get_max_link_speed(p, NULL); - - PHBDBG(p, "FRESET: Prepare for link down\n"); - phb4_prepare_link_change(slot, false); - - if (!p->skip_perst) { - PHBDBG(p, "FRESET: Assert\n"); - phb4_assert_perst(slot, true); - pci_slot_set_state(slot, PHB4_SLOT_FRESET_ASSERT_DELAY); - - /* 250ms assert time aligns with powernv */ - return pci_slot_set_sm_timeout(slot, msecs_to_tb(250)); - } - - /* To skip the assert during boot time */ - PHBDBG(p, "FRESET: Assert skipped\n"); - pci_slot_set_state(slot, PHB4_SLOT_FRESET_ASSERT_DELAY); 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Wed, 03 Apr 2019 02:10:16 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:18 +1100 Message-Id: <20190403090920.362-22-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 21/23] platforms/qemu: Add slot table X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a slot table to our QEMU platform file to allow testing of the OPAL PCI hotplug operations. Signed-off-by: Oliver O'Halloran --- platforms/qemu/qemu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/platforms/qemu/qemu.c b/platforms/qemu/qemu.c index 04bf3fb3f0ea..36275ecd50f0 100644 --- a/platforms/qemu/qemu.c +++ b/platforms/qemu/qemu.c @@ -37,6 +37,8 @@ static bool qemu_probe(void) bt_device_present = true; } + slot_table_init(qemu_phb_table); + return true; } @@ -53,6 +55,7 @@ DECLARE_PLATFORM(qemu) = { .name = "Qemu", .probe = qemu_probe, .init = qemu_init, + .pci_get_slot_info = slot_table_get_slot_info, .external_irq = astbmc_ext_irq_serirq_cpld, .cec_power_down = astbmc_ipmi_power_down, .cec_reboot = astbmc_ipmi_reboot, From patchwork Wed Apr 3 09:09:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0mp3Q5Mz9sNF for ; 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Wed, 03 Apr 2019 02:10:18 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:19 +1100 Message-Id: <20190403090920.362-23-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 22/23] platforms/qemu: Add fake power control X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Adds some power control stubs to the QEMU platform's root complex slots. This allows us to test the sync and async slot power control paths. Signed-off-by: Oliver O'Halloran --- platforms/qemu/qemu.c | 74 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/platforms/qemu/qemu.c b/platforms/qemu/qemu.c index 36275ecd50f0..c6db931443d5 100644 --- a/platforms/qemu/qemu.c +++ b/platforms/qemu/qemu.c @@ -18,9 +18,81 @@ #include #include #include +#include +#include +#include #include +ST_PLUGGABLE(qemu_slot0, "Slot0"); +ST_PLUGGABLE(qemu_slot1, "Slot1"); +ST_PLUGGABLE(qemu_slot2, "Slot2"); +ST_PLUGGABLE(qemu_slot3, "Slot3"); +ST_PLUGGABLE(qemu_slot4, "Slot4"); +ST_PLUGGABLE(qemu_slot5, "Slot5"); + +static const struct slot_table_entry qemu_phb_table[] = { + ST_PHB_ENTRY(0, 0, qemu_slot0), + ST_PHB_ENTRY(0, 1, qemu_slot1), + ST_PHB_ENTRY(0, 2, qemu_slot2), + ST_PHB_ENTRY(0, 3, qemu_slot3), + ST_PHB_ENTRY(0, 4, qemu_slot4), + ST_PHB_ENTRY(0, 5, qemu_slot5), + { .etype = st_end }, +}; + +static int64_t qemu_get_power(struct pci_slot *slot, uint8_t *val) +{ + *val = slot->power_state; + return OPAL_SUCCESS; +} + +static int64_t qemu_set_power_delay(struct pci_slot *slot, uint8_t val) +{ + slot->power_state = val; + + PCIERR(slot->phb, 0, "%s: v=%d, ctl_state = %d\n", __func__, val, + slot->power_ctl_state); + switch (slot->power_ctl_state) { + case 0 ... 30: + slot->power_ctl_state += 10; + break; + default: + slot->power_ctl_state = 0; + } + + return slot->power_ctl_state ? 1 : OPAL_SUCCESS; +} + +static int64_t qemu_set_power_immed(struct pci_slot *slot, uint8_t val) +{ + slot->power_state = val; + return OPAL_SUCCESS; +} + +static void qemu_get_slot_info(struct phb *phb, struct pci_device *pd) +{ + struct pci_slot *slot; + + if (pd) { + slot_table_get_slot_info(phb, pd); + if (pd->dev_type != PCIE_TYPE_ROOT_PORT) + return; + slot = pd->slot; + } else { + slot = phb->slot; + } + + /* use the override methods for root ports, and PHB slots */ + slot->ops.get_power_state = qemu_get_power; + slot->ops.poll_link = phb->slot->ops.poll_link; + + if (phb->opal_id & 0x1) + slot->ops.set_power_state = qemu_set_power_delay; + else + slot->ops.set_power_state = qemu_set_power_immed; +} + static bool bt_device_present; static bool qemu_probe(void) @@ -55,7 +127,7 @@ DECLARE_PLATFORM(qemu) = { .name = "Qemu", .probe = qemu_probe, .init = qemu_init, - .pci_get_slot_info = slot_table_get_slot_info, + .pci_get_slot_info = qemu_get_slot_info, .external_irq = astbmc_ext_irq_serirq_cpld, .cec_power_down = astbmc_ipmi_power_down, .cec_reboot = astbmc_ipmi_reboot, From patchwork Wed Apr 3 09:09:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0n55VLtz9sNF for ; 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Wed, 03 Apr 2019 02:10:20 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:09:20 +1100 Message-Id: <20190403090920.362-24-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 23/23] pci-slot: Make skip_perst generic X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Using the generic freset meant that we lose the PERST skipping optimisation. Add it back in to the generic FRESET. Signed-off-by: Oliver O'Halloran --- core/pci-slot.c | 11 +++++++++-- hw/phb3.c | 39 ++++++++++++++++++--------------------- hw/phb4.c | 36 +++++++++++++++++------------------- include/pci-slot.h | 1 + 4 files changed, 45 insertions(+), 42 deletions(-) diff --git a/core/pci-slot.c b/core/pci-slot.c index 14dd95ec0dd1..67e62d089f6a 100644 --- a/core/pci-slot.c +++ b/core/pci-slot.c @@ -126,11 +126,18 @@ int64_t pci_slot_generic_freset(struct pci_slot *slot) // not strictly required... assert(slot->ops.prepare_link_change); - switch(slot->state) { +again: switch(slot->state) { case PCI_SLOT_STATE_NORMAL: case PCI_SLOT_FRESET_START: - PCIERR(phb, bdfn, "FRESET: Prepare for link down\n"); + if (slot->skip_perst) { + PCIDBG(phb, bdfn, "FRESET: Prepare for link down\n"); + slot->skip_perst = false; + pci_slot_set_state(slot, PCI_SLOT_FRESET_LIFT_PERST); + goto again; + } + + PCIERR(phb, bdfn, "FRESET: Prepare for link down\n"); // FIXME: Handle errors if (slot->ops.prepare_link_change) slot->ops.prepare_link_change(slot, false); diff --git a/hw/phb3.c b/hw/phb3.c index d86fb74bbbf9..4618231dee3b 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -4616,27 +4616,6 @@ static void phb3_create(struct dt_node *np) p->spci_xscom = ((const uint32_t *)prop->prop)[1]; p->pci_xscom = ((const uint32_t *)prop->prop)[2]; - /* - * We skip the initial PERST assertion requested by the generic code - * when doing a cold boot because we are coming out of cold boot already - * so we save boot time that way. The PERST state machine will still - * handle waiting for the link to come up, it will just avoid actually - * asserting & deasserting the PERST output - * - * For a hot IPL, we still do a PERST - * - * Note: In absence of property (ie, FSP-less), we stick to the old - * behaviour and set skip_perst to true - */ - p->skip_perst = true; /* Default */ - - iplp = dt_find_by_path(dt_root, "ipl-params/ipl-params"); - if (iplp) { - const char *ipl_type = dt_prop_get_def(iplp, "cec-major-type", NULL); - if (ipl_type && (!strcmp(ipl_type, "hot"))) - p->skip_perst = false; - } - /* By default link is assumed down */ p->has_link = false; @@ -4655,6 +4634,24 @@ static void phb3_create(struct dt_node *np) if (!slot) PHBERR(p, "Cannot create PHB slot\n"); + /* + * We skip the initial PERST assertion requested by the generic code + * when doing a cold boot because we are coming out of cold boot already + * so we save boot time that way. The PERST state machine will still + * handle waiting for the link to come up, it will just avoid actually + * asserting & deasserting the PERST output + * + * For a hot IPL, we still do a PERST + * + * Note: In absence of property (ie, FSP-less), we stick to the old + * behaviour and set skip_perst to true + */ + slot->skip_perst = true; /* Default */ + + iplp = dt_find_by_path(dt_root, "ipl-params/ipl-params"); + if (iplp && dt_has_node_property(iplp, "cec-major-type", "hot")) + slot->skip_perst = false; + /* Hello ! */ path = dt_get_path(np); PHBINF(p, "Found %s @[%d:%d]\n", path, p->chip_id, p->index); diff --git a/hw/phb4.c b/hw/phb4.c index 99e694059a80..bf42ca76410f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3366,7 +3366,7 @@ static int64_t phb4_creset(struct pci_slot *slot) * have waited long enough, so we can skip it in the freset * procedure. */ - p->skip_perst = true; + slot->skip_perst = true; pci_slot_set_state(slot, PHB4_SLOT_NORMAL); return slot->ops.freset(slot); default: @@ -5600,6 +5600,19 @@ static void phb4_create(struct dt_node *np) p->pci_stk_xscom = ((const uint32_t *)prop->prop)[3]; p->etu_xscom = ((const uint32_t *)prop->prop)[4]; + /* By default link is assumed down */ + p->has_link = false; + + /* We register the PHB before we initialize it so we + * get a useful OPAL ID for it + */ + pci_register_phb(&p->phb, phb4_get_opal_id(p->chip_id, p->index)); + + /* Create slot structure */ + slot = phb4_slot_create(&p->phb); + if (!slot) + PHBERR(p, "Cannot create PHB slot\n"); + /* * We skip the initial PERST assertion requested by the generic code * when doing a cold boot because we are coming out of cold boot already @@ -5612,27 +5625,12 @@ static void phb4_create(struct dt_node *np) * Note: In absence of property (ie, FSP-less), we stick to the old * behaviour and set skip_perst to true */ - p->skip_perst = true; /* Default */ + slot->skip_perst = true; /* Default */ iplp = dt_find_by_path(dt_root, "ipl-params/ipl-params"); - if (iplp) { - const char *ipl_type = dt_prop_get_def(iplp, "cec-major-type", NULL); - if (ipl_type && (!strcmp(ipl_type, "hot"))) - p->skip_perst = false; - } - - /* By default link is assumed down */ - p->has_link = false; + if (iplp && dt_has_node_property(iplp, "cec-major-type", "hot")) + slot->skip_perst = false; - /* We register the PHB before we initialize it so we - * get a useful OPAL ID for it - */ - pci_register_phb(&p->phb, phb4_get_opal_id(p->chip_id, p->index)); - - /* Create slot structure */ - slot = phb4_slot_create(&p->phb); - if (!slot) - PHBERR(p, "Cannot create PHB slot\n"); /* Hello ! */ path = dt_get_path(np); diff --git a/include/pci-slot.h b/include/pci-slot.h index 9299ffae92e8..32101db6b84a 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -182,6 +182,7 @@ struct pci_slot { uint8_t power_state; /* used by the set_power_state() function */ + bool skip_perst; uint8_t power_ctl_state; /* Slot information */