From patchwork Tue Oct 24 17:55:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 829979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-465016-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="HTrixgP2"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yM1Dd5Q10z9s1h for ; Wed, 25 Oct 2017 04:56:49 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:date:message-id:cc:from:to; q=dns; s=default; b=uvTbpCU qnPdAGF/rHQqQ/tc/4wm0AvMhwzRodegF6m74rCy+ox9mPz0zByKsRHY+uaGn4ZX /MEtgG6s0bc0j0feq3FjHGQhVLBdntXORnKglvf1Cv2MmE7+9S1ABUYQlXyy97Yx o8Fd/frR5Qzi7x61k19wfvNwzKH0JbDgWtc8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:date:message-id:cc:from:to; s=default; bh=bjtJx3RULCeXv XxMynLw6sCkWnc=; b=HTrixgP2FYxHYe9W48AwYqMOwgd3+CcdqR37pLss09uls /EFCIV9GxX6k+iPAqStJi/1Za+FdWsi3XQU8otpkkc45dpDr0N56va/81ASwSIT+ +fRftqQqrzW8dX4X05uNBsepKeNW4WJuHkpH35GH/LGbAp22TRKUYHvZaiVPRs= Received: (qmail 87255 invoked by alias); 24 Oct 2017 17:56:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 87211 invoked by uid 89); 24 Oct 2017 17:56:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=2599, our X-HELO: mail-pf0-f193.google.com Received: from mail-pf0-f193.google.com (HELO mail-pf0-f193.google.com) (209.85.192.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 24 Oct 2017 17:56:25 +0000 Received: by mail-pf0-f193.google.com with SMTP id d28so20228273pfe.2 for ; Tue, 24 Oct 2017 10:56:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:cc:from:to; bh=8AuPeFK7f9F9QeevVp+RO0x7vYbEZc5+ifhrwuFhTDw=; b=HkO8OqWhMz1QQiPUgXri3qZSinB4JUHMswYZJIFPMr9HS/29UeZekcSrqRLtL5Isqv EucUP6Vo+JycItu7Z9UEICiVj4lIOkiVDbhgvCMhleBoV7iKzOgSKyLuoQ+SCcxzNTRY 3Qt7xDdSDN8DTs7/DgIEcrwdXBs0qJX+MzE5at+OV0R5KrTprx6H2uWGbPuKAXHr5/f4 7+OQV52Qdp5soO5Qqcm88BdhR8WCQBDmh4hBzBujFNDPJxghOQHpYuDBbN5seyXnVdXd Rpprxpj0SI7GGRo22oxov4CP6COCoFswo3WZPKGqR3rZj3Fs4yGgAif+N8NKITY4x76g QkOg== X-Gm-Message-State: AMCzsaVUuqfm/YXwxDwNM0MpXvzyj4hyv3FYUmuexDx3m+hex6RmlumU JFxp8aonS9pTIazElbhnJ9h9zw== X-Google-Smtp-Source: ABhQp+TP5yTRVHOfzP9YKnMh/fGNGOlcZ7INbtAM721eQbGuD0Q3mHUiwUixIL5/FYJlSsvmHkM5Ww== X-Received: by 10.84.244.6 with SMTP id g6mr13814860pll.148.1508867783743; Tue, 24 Oct 2017 10:56:23 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id q13sm1786218pfi.166.2017.10.24.10.56.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Oct 2017 10:56:22 -0700 (PDT) Subject: [PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads Date: Tue, 24 Oct 2017 10:55:46 -0700 Message-Id: <20171024175546.27664-1-palmer@dabbelt.com> Cc: patches@groups.riscv.org, Palmer Dabbelt From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org X-IsSubscribed: yes Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-10-24 Palmer Dabbelt * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s, mark as a sign-extending load. (local_pic_load_u): Define. --- gcc/config/riscv/pic.md | 11 +++++++++-- gcc/config/riscv/riscv.md | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md index 6a29ead32d36..03b8f9bc669e 100644 --- a/gcc/config/riscv/pic.md +++ b/gcc/config/riscv/pic.md @@ -22,13 +22,20 @@ ;; Simplify PIC loads to static variables. ;; These should go away once we figure out how to emit auipc discretely. -(define_insn "*local_pic_load" +(define_insn "*local_pic_load_s" [(set (match_operand:ANYI 0 "register_operand" "=r") - (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))] + (sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))] "USE_LOAD_ADDRESS_MACRO (operands[1])" "\t%0,%1" [(set (attr "length") (const_int 8))]) +(define_insn "*local_pic_load_u" + [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r") + (zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))] + "USE_LOAD_ADDRESS_MACRO (operands[1])" + "u\t%0,%1" + [(set (attr "length") (const_int 8))]) + (define_insn "*local_pic_load" [(set (match_operand:ANYF 0 "register_operand" "=f") (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index fd9236c7c170..9f056bbcda4f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -259,6 +259,9 @@ ;; Iterator for QImode extension patterns. (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) +;; Iterator for extending loads. +(define_mode_iterator ZERO_EXTEND_LOAD [QI HI (SI "TARGET_64BIT")]) + ;; Iterator for hardware integer modes narrower than XLEN. (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])