From patchwork Tue Oct 23 14:55:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 988235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=uclibc-ng.org (client-ip=89.238.66.15; helo=helium.openadk.org; envelope-from=devel-bounces@uclibc-ng.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="jE0v59uo"; dkim-atps=neutral Received: from helium.openadk.org (helium.openadk.org [89.238.66.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42fbzQ6bg0z9s9h for ; Wed, 24 Oct 2018 01:55:29 +1100 (AEDT) Received: from helium.openadk.org (localhost [IPv6:::1]) by helium.openadk.org (Postfix) with ESMTP id 8987C10117; Tue, 23 Oct 2018 16:55:24 +0200 (CEST) X-Original-To: devel@uclibc-ng.org Delivered-To: devel@helium.openadk.org Received: from mail-ua1-f52.google.com (mail-ua1-f52.google.com [209.85.222.52]) by helium.openadk.org (Postfix) with ESMTPS id 9AEAD10117 for ; Tue, 23 Oct 2018 16:55:21 +0200 (CEST) Received: by mail-ua1-f52.google.com with SMTP id w12so602966uam.9 for ; Tue, 23 Oct 2018 07:55:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:from:date:message-id:subject:to; bh=ut3vJz589A8D+PON1PqVxt07EsgfxQtaSRc9KTCU5QU=; b=jE0v59uo/bLHU+dzkkfA7hUvWhjyM1/g08oB6PU6g1q+xl4x7dP5zGyqayznkdaTTB HCKHASTKhekXPEJ/OCiXlnlRxZC1Vp0qiNQszQVBT4jlSqzeEDawIxf7EOgyjaS7ZVe6 i+uPNtoXKKNWzXAyYFKakmOuyAtF21Q9pjqG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=ut3vJz589A8D+PON1PqVxt07EsgfxQtaSRc9KTCU5QU=; b=a6kMG6B5kBG4xemJ1dA9OvZZ0TX96HEpAwebCz7Mjna3Z6VZJOYUWL5nyI6ZGJflLg 0z2S/ItiXH6WIbzztZDgFaAwzm50Tn69aiwcrb5HP8210Nlh6YSzSUwxwT/GVFMMXqWq B2IwdQauu4y64n86iKMf/WLEXXGyPqXYO3Vonw3xRcubYMQ86zDLWdwYDrHGNLfBP3bU LCxFvZKjN2y+HQSvfwrpcIZrowTOe5FiVyGU6fPP9hsVfurU+tzOEwZUX3NQiuFu1F7J CNN4XHKrvYZDPnXTJWT/G6Lq7DU0GZMrPY35oqvpN92auItNWjf2afAqF66SHUBv7jJH ZVgw== X-Gm-Message-State: ABuFfoh5tnF9xK2y4ZV0EmL/bZa88DWPienJPCIns/S8MCasmzc3Tn5v Iif2/yBUa4XaRWJVOdHYGzYxGPPqgIeTCkz/RK/eUbk3 X-Google-Smtp-Source: ACcGV62rc62CdgDPywr9LqGPO2pD9zNuLgXO9y9ewazftphC5VR+oB9I0Q5X3SYlSq+h8JkFA/pgBLzT54ftz17ckYA= X-Received: by 2002:ab0:31cb:: with SMTP id e11mr22032396uan.62.1540306519516; Tue, 23 Oct 2018 07:55:19 -0700 (PDT) MIME-Version: 1.0 From: Christophe Lyon Date: Tue, 23 Oct 2018 16:55:08 +0200 Message-ID: To: devel@uclibc-ng.org Subject: [uclibc-ng-devel] [ARM][FDPIC]: Add support for Thumb-only processors. X-BeenThere: devel@uclibc-ng.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: uClibc-ng Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devel-bounces@uclibc-ng.org Sender: "devel" Hi, This patch enables to compile uClibc-ng in FDPIC mode with a compiler defaulting to Thumb mode (eg. targeting a cortex-M processor). OK? Thanks, Christophe [ARM][FDPIC]: Add support for Thumb-only processors. * ldso/ldso/arm/aeabi_read_tp.S: Add Thumb version. * ldso/ldso/arm/dl-startup.h: Do not force ARM encoding, adjust for Thumb. * ldso/ldso/arm/resolve.S: Force Thumb encoding on Thumb-only processors. * ldso/ldso/arm/thumb_atomics.S: Disable on FDPIC, seems useless. * libc/sysdeps/linux/arm/crt1.S: Do not force ARM encoding, adjust for Thumb. Signed-off-by: Mickaël Guêné Signed-off-by: Christophe Lyon Signed-off-by: Mickaël Guêné Signed-off-by: Christophe Lyon diff --git a/ldso/ldso/arm/aeabi_read_tp.S b/ldso/ldso/arm/aeabi_read_tp.S index 77e0d6e..5ab5125 100644 --- a/ldso/ldso/arm/aeabi_read_tp.S +++ b/ldso/ldso/arm/aeabi_read_tp.S @@ -53,9 +53,23 @@ #else .hidden __aeabi_read_tp #endif +#if !defined(__ARM_ARCH_ISA_ARM) + .thumb_func + .thumb + .syntax unified + ENTRY (__aeabi_read_tp) + push {r7} + mov r7, #0x0f0000 + orr r7, r7, #6 + svc #0 + pop {r7} + bx lr +#else + .arm ENTRY (__aeabi_read_tp) mov r0, #0xffff0fff sub pc, r0, #31 +#endif END (__aeabi_read_tp) #endif /* __UCLIBC_HAS_THREADS_NATIVE__ */ diff --git a/ldso/ldso/arm/dl-startup.h b/ldso/ldso/arm/dl-startup.h index 06c95cb..cacd461 100644 --- a/ldso/ldso/arm/dl-startup.h +++ b/ldso/ldso/arm/dl-startup.h @@ -11,10 +11,13 @@ #if defined(__FDPIC__) #if !defined(__thumb__) || defined(__thumb2__) __asm__( - " .arm\n" " .text\n" " .globl _start\n" " .type _start,%function\n" +#if defined(__thumb2__) + " .thumb_func\n" +#endif + " .align 2\n" "_start:\n" /* We compute the parameters for __self_reloc: - r0 is a pointer to the loadmap (either from r8 or r7 if rtld is @@ -25,12 +28,17 @@ __asm__( __self_reloc will fix indirect addresses in .rofixup section and will return the relocated GOT value. */ +#if defined(__thumb2__) + " sub r4, pc, #4\n" +#else " sub r4, pc, #8\n" +#endif " ldr r1, .L__ROFIXUP_LIST__\n" " add r1, r1, r4\n" " ldr r2, .L__ROFIXUP_END__\n" " add r2, r2, r4\n" " movs r0, r8\n" + " it eq\n" " moveq r0, r7\n" " push {r7, r8, r9, r10}\n" " bl __self_reloc;\n" diff --git a/ldso/ldso/arm/resolve.S b/ldso/ldso/arm/resolve.S index 039a6b7..8013872 100644 --- a/ldso/ldso/arm/resolve.S +++ b/ldso/ldso/arm/resolve.S @@ -101,7 +101,15 @@ .text .align 4 @ 16 byte boundary and there are 32 bytes below (arm case) #if 1 /*(!defined(__thumb__) || defined __THUMB_INTERWORK__) || defined(__thumb2__)*/ - .arm + /* On Thumb-only processors, force thumb encoding. These + processors support Thumb-2, so the same source code can be + used as in ARM mode. */ +#if !defined(__ARM_ARCH_ISA_ARM) + .thumb + .thumb_func +#else + .arm +#endif .hidden _dl_linux_resolve .globl _dl_linux_resolve .type _dl_linux_resolve,%function diff --git a/ldso/ldso/arm/thumb_atomics.S b/ldso/ldso/arm/thumb_atomics.S index f88da2b..b0bc941 100644 --- a/ldso/ldso/arm/thumb_atomics.S +++ b/ldso/ldso/arm/thumb_atomics.S @@ -34,6 +34,8 @@ #include +/* This code seems useless and doesn't compile for Cortex-M. */ +#ifndef __FDPIC__ #ifdef __UCLIBC_HAS_THREADS_NATIVE__ #include @@ -76,3 +78,4 @@ END (__thumb_cmpxchg) #endif /* __thumb__ */ #endif /* __UCLIBC_HAS_THREADS_NATIVE__ */ +#endif /* __FDPIC__ */ diff --git a/libc/sysdeps/linux/arm/crt1.S b/libc/sysdeps/linux/arm/crt1.S index 5da0fe1..a1d7f0f 100644 --- a/libc/sysdeps/linux/arm/crt1.S +++ b/libc/sysdeps/linux/arm/crt1.S @@ -97,12 +97,17 @@ ARM register quick reference: #if defined(__FDPIC__) .text - .arm .globl _start + .type _start,%function + .align 2 _start: /* Start by self relocation. */ +#if defined(__thumb2__) + sub r4, pc, #4 +#else sub r4, pc, #8 +#endif ldr r1, .L__ROFIXUP_LIST__ add r1, r1, r4 ldr r2, .L__ROFIXUP_END__ @@ -129,6 +134,7 @@ _start: ldr r4, [r9, r4] str r4, [sp, #0] /* sp + 0 GOT fini */ movs r4, r8 /* Test if static binary (r8 is 0 as there is no interpreter). */ + ite ne movne r4, r10 moveq r4, #0 str r4, [sp, #4] /* sp + 4 got rtld_fini */