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Tue, 27 Feb 2024 09:10:41 -0800 From: David Thompson To: Subject: [SRU][J:linux-bluefield][PATCH v1 1/1] UBUNTU: SAUCE: mlxbf_gige: add support to display pause frame counters Date: Tue, 27 Feb 2024 12:10:36 -0500 Message-ID: <713e4faf6de5aa2e665d6dbfe66e3677647b96bf.1709053128.git.davthompson@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E5:EE_|MW3PR12MB4585:EE_ X-MS-Office365-Filtering-Correlation-Id: 0bed8a8e-92fc-4f74-dba4-08dc37b7172f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v44CjzmfsGSRwcsCRrn6uchZzKQM5oOliGHuXcMbMvS7+fKcE7LdBptcWUS5gc/mFFeP9iIo5bOIcXLmRnmpKOkjH+ljqyyRCyDnMq2iNTF+XG6cTjF80Er/lzQYIQ95hUWYCUzf0yR6ncIuHMHoSFtZUw1FOsleaFDUOI6mk3wA5GBAPBsGYfaQJuj7UZBwBeg0TqUqsA8J8AVUrgpM+tLhw5fwd791PF2Hk3fAi3LmQmyKue9CuBfKFXgkNLAR/Uo7eEvbIqF0LIy3z6lFm8MicfAZF89bRn5IBUnod7ixjYvE3CGf3rR86Xgl43hryD7l3yQdvTE6VK81rGEqlXZfOhnM0I5XFYnoRYzq+cW029tNwjChrR4+cU/v1gwXR1olvn767H5fcmk2HSOPOWnJSoVB8AGsxQLeD4VOeF6kuCrJ7c970DZ+AXhNlQNl3i6WqIzjUbVwJZ8GeJ3mysAhYnjIaVcueClQg8PkKuxXc3dAX+ro6s/0vtl64N7QtY3ZUfrlhvqzMNOkeIIAPy6bUPzHnaomdtn0f40l9PQtyd4BO6e6Vdlw9MNLO5IVi0wMD8z7yawzZoPTI52vXTH1bVbyAw8tvisIzLdD6WMq9Qk5VoYYGNftKeLJYCJtsxebEDfFhFr4vXSOddstmdRi0xZ0J7myTK4YaZCiFZFarl/1wrWkQcmoEZbkj0v6wHFXDWNzeyHE1wJP2xZUhEyADzV6MYYApFrYd18MmbWv7LSwe4ziNTML2bMCnDZ056kECnzgEv26Wg+0bq7DG6QOCzUl86vntYkXheeYPQw= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2024 17:11:08.5135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bed8a8e-92fc-4f74-dba4-08dc37b7172f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4585 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: asmaa@nvidia.com, David Thompson Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/2055086 This patch updates the mlxbf_gige driver to support the "get_pause_stats()" callback, which enables display of pause frame counters via "ethtool -I -a ooob_net0". The Linux kernel added support for this callback in 5.9.0. The pause frame counters are only enabled if the "counters_en" bit is asserted in the LLU general config register. If this bit is not asserted, the counters read back random values so a run-time check is made to return counter values of 0 if the counters are not actually enabled. Reviewed-by: Asmaa Mnebhi Signed-off-by: David Thompson --- .../mellanox/mlxbf_gige/mlxbf_gige_ethtool.c | 39 +++++++++++++++++++ .../mellanox/mlxbf_gige/mlxbf_gige_regs.h | 22 +++++++++++ 2 files changed, 61 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c index 602537f62098..c2a376db6ad1 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c @@ -158,6 +158,44 @@ static void mlxbf_gige_get_pauseparam(struct net_device *netdev, pause->tx_pause = 1; } +static bool mlxbf_gige_llu_counters_enabled(struct mlxbf_gige *priv) +{ + u32 data; + + if (priv->hw_version == MLXBF_GIGE_VERSION_BF2) { + data = readl(priv->llu_base + MLXBF_GIGE_BF2_LLU_GENERAL_CONFIG); + if (data & MLXBF_GIGE_BF2_LLU_COUNTERS_EN) + return true; + } else { + data = readl(priv->llu_base + MLXBF_GIGE_BF3_LLU_GENERAL_CONFIG); + if (data & MLXBF_GIGE_BF3_LLU_COUNTERS_EN) + return true; + } + + return false; +} + +static void mlxbf_gige_get_pause_stats(struct net_device *netdev, + struct ethtool_pause_stats *pause_stats) +{ + struct mlxbf_gige *priv = netdev_priv(netdev); + u64 dataLo, dataHi; + + /* Read LLU counters only if they are enabled */ + if (mlxbf_gige_llu_counters_enabled(priv)) { + dataLo = readl(priv->llu_base + MLXBF_GIGE_TX_PAUSE_CNT_LO); + dataHi = readl(priv->llu_base + MLXBF_GIGE_TX_PAUSE_CNT_HI); + pause_stats->tx_pause_frames = (dataHi << 32) | dataLo; + + dataLo = readl(priv->llu_base + MLXBF_GIGE_RX_PAUSE_CNT_LO); + dataHi = readl(priv->llu_base + MLXBF_GIGE_RX_PAUSE_CNT_HI); + pause_stats->rx_pause_frames = (dataHi << 32) | dataLo; + } else { + pause_stats->tx_pause_frames = 0; + pause_stats->rx_pause_frames = 0; + } +} + const struct ethtool_ops mlxbf_gige_ethtool_ops = { .get_link = ethtool_op_get_link, .get_ringparam = mlxbf_gige_get_ringparam, @@ -169,6 +207,7 @@ const struct ethtool_ops mlxbf_gige_ethtool_ops = { .get_ethtool_stats = mlxbf_gige_get_ethtool_stats, .nway_reset = phy_ethtool_nway_reset, .get_pauseparam = mlxbf_gige_get_pauseparam, + .get_pause_stats = mlxbf_gige_get_pause_stats, .get_link_ksettings = phy_ethtool_get_link_ksettings, .set_link_ksettings = phy_ethtool_set_link_ksettings, }; diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h index cd0973229c9b..9702b5be3c85 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h @@ -99,4 +99,26 @@ #define MLXBF_GIGE_100M_IPG_SIZE 119 #define MLXBF_GIGE_10M_IPG_SIZE 1199 +/* Offsets into OOB LLU block for pause frame counters */ +#define MLXBF_GIGE_BF2_TX_PAUSE_CNT_HI 0x33d8 +#define MLXBF_GIGE_BF2_TX_PAUSE_CNT_LO 0x33dc +#define MLXBF_GIGE_BF2_RX_PAUSE_CNT_HI 0x3210 +#define MLXBF_GIGE_BF2_RX_PAUSE_CNT_LO 0x3214 + +#define MLXBF_GIGE_BF3_TX_PAUSE_CNT_HI 0x3a88 +#define MLXBF_GIGE_BF3_TX_PAUSE_CNT_LO 0x3a8c +#define MLXBF_GIGE_BF3_RX_PAUSE_CNT_HI 0x38c0 +#define MLXBF_GIGE_BF3_RX_PAUSE_CNT_LO 0x38c4 + +#define MLXBF_GIGE_TX_PAUSE_CNT_HI ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? MLXBF_GIGE_BF2_TX_PAUSE_CNT_HI : MLXBF_GIGE_BF3_TX_PAUSE_CNT_HI) +#define MLXBF_GIGE_TX_PAUSE_CNT_LO ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? MLXBF_GIGE_BF2_TX_PAUSE_CNT_LO : MLXBF_GIGE_BF3_TX_PAUSE_CNT_LO) +#define MLXBF_GIGE_RX_PAUSE_CNT_HI ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? MLXBF_GIGE_BF2_RX_PAUSE_CNT_HI : MLXBF_GIGE_BF3_RX_PAUSE_CNT_HI) +#define MLXBF_GIGE_RX_PAUSE_CNT_LO ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? MLXBF_GIGE_BF2_RX_PAUSE_CNT_LO : MLXBF_GIGE_BF3_RX_PAUSE_CNT_LO) + +#define MLXBF_GIGE_BF2_LLU_GENERAL_CONFIG 0x2110 +#define MLXBF_GIGE_BF3_LLU_GENERAL_CONFIG 0x2030 + +#define MLXBF_GIGE_BF2_LLU_COUNTERS_EN BIT(0) +#define MLXBF_GIGE_BF3_LLU_COUNTERS_EN BIT(4) + #endif /* !defined(__MLXBF_GIGE_REGS_H__) */