@@ -633,7 +633,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
*/
intel_psr_wait_for_idle_locked(new_crtc_state);
- local_irq_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_disable();
crtc->debug.min_vbl = evade.min;
crtc->debug.max_vbl = evade.max;
@@ -651,7 +652,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
return;
irq_disable:
- local_irq_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_disable();
}
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -798,7 +800,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
!new_crtc_state->vrr.enable))
intel_vrr_send_push(NULL, new_crtc_state);
- local_irq_enable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_enable();
if (intel_parent_vgpu_active(display))
goto out;
@@ -919,13 +919,15 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
*/
intel_psr_wait_for_idle_locked(crtc_state);
- local_irq_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_disable();
intel_vblank_evade(&evade);
drm_crtc_vblank_put(&crtc->base);
} else {
- local_irq_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_disable();
}
if (new_plane_state->uapi.visible) {
@@ -935,7 +937,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
intel_plane_disable_arm(NULL, plane, crtc_state);
}
- local_irq_enable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_enable();
intel_psr_unlock(crtc_state);
@@ -788,11 +788,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
break;
}
- local_irq_enable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_enable();
timeout = schedule_timeout(timeout);
- local_irq_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+ local_irq_disable();
}
finish_wait(wq, &wait);