From patchwork Fri Apr 12 19:23:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuxuan Luo X-Patchwork-Id: 1923235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com (client-ip=185.125.189.65; helo=lists.ubuntu.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=patchwork.ozlabs.org) Received: from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VGRML057Sz1yYs for ; Sat, 13 Apr 2024 05:24:14 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=lists.ubuntu.com) by lists.ubuntu.com with esmtp (Exim 4.86_2) (envelope-from ) id 1rvMVM-0004S0-Jn; Fri, 12 Apr 2024 19:24:08 +0000 Received: from smtp-relay-internal-0.internal ([10.131.114.225] helo=smtp-relay-internal-0.canonical.com) by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1rvMVK-0004Nb-MX for kernel-team@lists.ubuntu.com; Fri, 12 Apr 2024 19:24:06 +0000 Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 4A4183F297 for ; Fri, 12 Apr 2024 19:24:06 +0000 (UTC) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-6966412d4dbso19502306d6.0 for ; Fri, 12 Apr 2024 12:24:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712949844; x=1713554644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KTwkuTIDUBrqhzohHG/0jjiQCo7Nv1e75GvG8Lqm43s=; b=q5tpeznKFXqjKNnuwpxyNNkEAkbLW70EWevum1ycX7fJ39VKAQ9yY8VE+5W0xkaQDy hxvsoZUpl0e1XRqI4Bnmaplq8y8jQpXhdCzla9TQDRzMjGHu9TFJx9n57bHGUDAkR1I6 PiOCMsV5m6OuDppNPUYr8LGgBwRuBWPPTBtc0FDxBvZELdEKx//3PgQzX1t2S3L2P6kO pOecTl1lrafjFMF5L2Hw3oTPpUzyPmJMRo0tyUWCK4Zt9CyhK31+zLwFfV5jWHtzH/IZ aV7VodCqA+OtjR1O3UeRM9RjZoZc9lf7jCaouJ6BMX2CTMctdZtjMBxjoMOtjzyliHX6 LlfA== X-Gm-Message-State: AOJu0YxGBZeIpMUjyCHvTfNAJzlbIGUiRaT6wfYskFb8GPjF5zNnp6yT T7qNUNYc/95JwzpXpi7E883PFbRsijhJ2LtcFaeO5Z8ekILRuPXIYs+1k+V9pNo6c4cym9p9oXn YtgEKLwzkzYhpyGqV+oZL1NXB7SuQqh4nvjK/TnT9FI9/jVzY4uZdDWpuCHZKsCR/QcIGUrLPEk jENrBZgoH7QFay X-Received: by 2002:a0c:e741:0:b0:696:a490:a94f with SMTP id g1-20020a0ce741000000b00696a490a94fmr5549897qvn.30.1712949844066; Fri, 12 Apr 2024 12:24:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IELz1tw8k5Q/vqZeCU07g+//9Zpz5luu3arACIVWC+qTHU4hCj2ttpXl/pC50awXdCWsJKibg== X-Received: by 2002:a0c:e741:0:b0:696:a490:a94f with SMTP id g1-20020a0ce741000000b00696a490a94fmr5549878qvn.30.1712949843767; Fri, 12 Apr 2024 12:24:03 -0700 (PDT) Received: from cache-ubuntu.hsd1.nj.comcast.net ([2001:67c:1562:8007::aac:4795]) by smtp.gmail.com with ESMTPSA id z6-20020a0ce986000000b0069b47a53012sm2654071qvn.140.2024.04.12.12.24.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 12:24:03 -0700 (PDT) From: Yuxuan Luo To: kernel-team@lists.ubuntu.com Subject: [PATCH 07/13] x86/bhi: Define SPEC_CTRL_BHI_DIS_S Date: Fri, 12 Apr 2024 15:23:44 -0400 Message-Id: <20240412192351.89501-8-yuxuan.luo@canonical.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240412192351.89501-1-yuxuan.luo@canonical.com> References: <20240412192351.89501-1-yuxuan.luo@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Daniel Sneddon Newer processors supports a hardware control BHI_DIS_S to mitigate Branch History Injection (BHI). Setting BHI_DIS_S protects the kernel from userspace BHI attacks without having to manually overwrite the branch history. Define MSR_SPEC_CTRL bit BHI_DIS_S and its enumeration CPUID.BHI_CTRL. Mitigation is enabled later. Signed-off-by: Daniel Sneddon Signed-off-by: Pawan Gupta Signed-off-by: Daniel Sneddon Signed-off-by: Thomas Gleixner Reviewed-by: Alexandre Chartre Reviewed-by: Josh Poimboeuf (backported from commit 0f4a837615ff925ba62648d280a861adf1582df7) [yuxuan.luo: manually backported the __feature_translate() by adding another pair of "else if". ] CVE-2024-2201 Signed-off-by: Yuxuan Luo --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 5 ++++- arch/x86/kernel/cpu/scattered.c | 1 + arch/x86/kvm/reverse_cpuid.h | 4 +++- 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7c47e6aa9ea17..8edb74b8e3e61 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -432,6 +432,7 @@ * Reuse free bits when adding new feature flags! */ #define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */ +#define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ /* * BUG word(s) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index dc7fa0aa0a8e9..cee413b8927a3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -53,10 +53,13 @@ #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) +#define SPEC_CTRL_BHI_DIS_S_SHIFT 10 /* Disable Branch History Injection behavior */ +#define SPEC_CTRL_BHI_DIS_S BIT(SPEC_CTRL_BHI_DIS_S_SHIFT) /* A mask for bits which the kernel toggles when controlling mitigations */ #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ - | SPEC_CTRL_RRSBA_DIS_S) + | SPEC_CTRL_RRSBA_DIS_S \ + | SPEC_CTRL_BHI_DIS_S) #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 06bfef1c4175e..0f5211087810c 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, + { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 }, { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index d50b653cb8d09..47c1f2b5b584a 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -42,7 +42,7 @@ enum kvm_only_cpuid_leafs { #define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1) #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) #define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3) -#define X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) +#define KVM_X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) #define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5) struct cpuid_reg { @@ -103,6 +103,8 @@ static __always_inline u32 __feature_translate(int x86_feature) return KVM_X86_FEATURE_SGX2; else if (x86_feature == X86_FEATURE_RRSBA_CTRL) return KVM_X86_FEATURE_RRSBA_CTRL; + else if (x86_feature == X86_FEATURE_BHI_CTRL) + return KVM_X86_FEATURE_BHI_CTRL; return x86_feature; }