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[SRU,jammy:linux] platform/x86/intel/pmc: Alder Lake PCH slp_s0_residency fix

Message ID 20230511192728.157623-1-philip.cox@canonical.com
State New
Headers show
Series [SRU,jammy:linux] platform/x86/intel/pmc: Alder Lake PCH slp_s0_residency fix | expand

Commit Message

Philip Cox May 11, 2023, 7:27 p.m. UTC 
From: Rajvi Jingar <rajvi.jingar@linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/2019250

For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the
slp_s0_residency attribute has been reporting the wrong value. Unlike other
platforms, ADL PCH does not have a counter for the time that the SLP_S0
signal was asserted. Instead, firmware uses the aggregate of the Low Power
Mode (LPM) substate counters as the S0ix value.  Since the LPM counters run
at a different frequency, this lead to misreporting of the S0ix time.

Add a check for Alder Lake PCH and adjust the frequency accordingly when
display slp_s0_residency.

Fixes: bbab31101f44 ("platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver")
Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230320212029.3154407-1-david.e.box@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
(cherry picked from commit fb5755100a0a5aa5957bdb204fd1e249684557fc)
Signed-off-by: Philip Cox <philip.cox@canonical.com>
---
 drivers/platform/x86/intel/pmc/core.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Tim Gardner May 22, 2023, 5:43 p.m. UTC | #1 
On 5/11/23 1:27 PM, Philip Cox wrote:
> From: Rajvi Jingar <rajvi.jingar@linux.intel.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/2019250
> 
> For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the
> slp_s0_residency attribute has been reporting the wrong value. Unlike other
> platforms, ADL PCH does not have a counter for the time that the SLP_S0
> signal was asserted. Instead, firmware uses the aggregate of the Low Power
> Mode (LPM) substate counters as the S0ix value.  Since the LPM counters run
> at a different frequency, this lead to misreporting of the S0ix time.
> 
> Add a check for Alder Lake PCH and adjust the frequency accordingly when
> display slp_s0_residency.
> 
> Fixes: bbab31101f44 ("platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver")
> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Link: https://lore.kernel.org/r/20230320212029.3154407-1-david.e.box@linux.intel.com
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> (cherry picked from commit fb5755100a0a5aa5957bdb204fd1e249684557fc)
> Signed-off-by: Philip Cox <philip.cox@canonical.com>
> ---
>   drivers/platform/x86/intel/pmc/core.c | 13 ++++++++++++-
>   1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index ac19fcc9abbf..b8d67bc4acb0 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -958,7 +958,18 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
>   
>   static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
>   {
> -	return (u64)value * pmcdev->map->slp_s0_res_counter_step;
> +	/*
> +	 * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
> +	 * used as a workaround which uses 30.5 usec tick. All other client
> +	 * programs have the legacy SLP_S0 residency counter that is using the 122
> +	 * usec tick.
> +	 */
> +	const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
> +
> +	if (pmcdev->map == &adl_reg_map)
> +		return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
> +	else
> +		return (u64)value * pmcdev->map->slp_s0_res_counter_step;
>   }
>   
>   static int set_etr3(struct pmc_dev *pmcdev)
Acked-by: Tim Gardner <tim.gardner@canonical.com>
John Cabaj May 24, 2023, 9:12 p.m. UTC | #2 
On 5/11/23 2:27 PM, Philip Cox wrote:
> From: Rajvi Jingar <rajvi.jingar@linux.intel.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/2019250
> 
> For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the
> slp_s0_residency attribute has been reporting the wrong value. Unlike other
> platforms, ADL PCH does not have a counter for the time that the SLP_S0
> signal was asserted. Instead, firmware uses the aggregate of the Low Power
> Mode (LPM) substate counters as the S0ix value.  Since the LPM counters run
> at a different frequency, this lead to misreporting of the S0ix time.
> 
> Add a check for Alder Lake PCH and adjust the frequency accordingly when
> display slp_s0_residency.
> 
> Fixes: bbab31101f44 ("platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver")
> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Link: https://lore.kernel.org/r/20230320212029.3154407-1-david.e.box@linux.intel.com
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> (cherry picked from commit fb5755100a0a5aa5957bdb204fd1e249684557fc)
> Signed-off-by: Philip Cox <philip.cox@canonical.com>
> ---
>  drivers/platform/x86/intel/pmc/core.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index ac19fcc9abbf..b8d67bc4acb0 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -958,7 +958,18 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
>  
>  static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
>  {
> -	return (u64)value * pmcdev->map->slp_s0_res_counter_step;
> +	/*
> +	 * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
> +	 * used as a workaround which uses 30.5 usec tick. All other client
> +	 * programs have the legacy SLP_S0 residency counter that is using the 122
> +	 * usec tick.
> +	 */
> +	const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
> +
> +	if (pmcdev->map == &adl_reg_map)
> +		return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
> +	else
> +		return (u64)value * pmcdev->map->slp_s0_res_counter_step;
>  }
>  
>  static int set_etr3(struct pmc_dev *pmcdev)

Acked-by: John Cabaj <john.cabaj@canonical.com>
Luke Nowakowski-Krijger June 12, 2023, 8:38 p.m. UTC | #3 
Already applied as a jammy v5.15.106 upstream stable update.

Thanks,
- Luke

On Thu, May 11, 2023 at 12:30 PM Philip Cox <philip.cox@canonical.com>
wrote:

> From: Rajvi Jingar <rajvi.jingar@linux.intel.com>
>
> BugLink: https://bugs.launchpad.net/bugs/2019250
>
> For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the
> slp_s0_residency attribute has been reporting the wrong value. Unlike other
> platforms, ADL PCH does not have a counter for the time that the SLP_S0
> signal was asserted. Instead, firmware uses the aggregate of the Low Power
> Mode (LPM) substate counters as the S0ix value.  Since the LPM counters run
> at a different frequency, this lead to misreporting of the S0ix time.
>
> Add a check for Alder Lake PCH and adjust the frequency accordingly when
> display slp_s0_residency.
>
> Fixes: bbab31101f44 ("platform/x86/intel: pmc/core: Add Alderlake support
> to pmc core driver")
> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Link:
> https://lore.kernel.org/r/20230320212029.3154407-1-david.e.box@linux.intel.com
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> (cherry picked from commit fb5755100a0a5aa5957bdb204fd1e249684557fc)
> Signed-off-by: Philip Cox <philip.cox@canonical.com>
> ---
>  drivers/platform/x86/intel/pmc/core.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/platform/x86/intel/pmc/core.c
> b/drivers/platform/x86/intel/pmc/core.c
> index ac19fcc9abbf..b8d67bc4acb0 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -958,7 +958,18 @@ static inline void pmc_core_reg_write(struct pmc_dev
> *pmcdev, int reg_offset,
>
>  static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32
> value)
>  {
> -       return (u64)value * pmcdev->map->slp_s0_res_counter_step;
> +       /*
> +        * ADL PCH does not have the SLP_S0 counter and LPM Residency
> counters are
> +        * used as a workaround which uses 30.5 usec tick. All other client
> +        * programs have the legacy SLP_S0 residency counter that is using
> the 122
> +        * usec tick.
> +        */
> +       const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
> +
> +       if (pmcdev->map == &adl_reg_map)
> +               return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
> +       else
> +               return (u64)value * pmcdev->map->slp_s0_res_counter_step;
>  }
>
>  static int set_etr3(struct pmc_dev *pmcdev)
> --
> 2.34.1
>
>
> --
> kernel-team mailing list
> kernel-team@lists.ubuntu.com
> https://lists.ubuntu.com/mailman/listinfo/kernel-team
>
diff mbox series

Patch

diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index ac19fcc9abbf..b8d67bc4acb0 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -958,7 +958,18 @@  static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
 
 static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
 {
-	return (u64)value * pmcdev->map->slp_s0_res_counter_step;
+	/*
+	 * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
+	 * used as a workaround which uses 30.5 usec tick. All other client
+	 * programs have the legacy SLP_S0 residency counter that is using the 122
+	 * usec tick.
+	 */
+	const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
+
+	if (pmcdev->map == &adl_reg_map)
+		return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
+	else
+		return (u64)value * pmcdev->map->slp_s0_res_counter_step;
 }
 
 static int set_etr3(struct pmc_dev *pmcdev)