| Message ID | 20220815113927.1056127-2-philip.cox@canonical.com |
|---|---|
| State | New |
| Headers | show |
| Series | i915: Enable HuC authentication for EHL, ICL, and ADL-S | expand |
On 8/15/22 05:39, Philip Cox wrote: > From: Raviteja Goud Talla <ravitejax.goud.talla@intel.com> > > BugLink: https://bugs.launchpad.net/bugs/1981971 > > Bspec page says "Reset: BUS", Accordingly moving w/a's: > Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init() > Which will resolve guc enabling error > > v2: > - Previous patch rev2 was created by email client which caused the > Build failure, This v2 is to resolve the previous broken series > > Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com> > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > Link: https://patchwork.freedesktop.org/patch/msgid/20211203145603.4006937-1-ravitejax.goud.talla@intel.com > (cherry picked from commit 67b858dd89932086ae0ee2d0ce4dd070a2c88bb3 upstream) Isn't 'upstream' superfluous ? > Signed-off-by: Philip Cox <philip.cox@canonical.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6b5ab19a2ada..0dda8f6da423 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1049,6 +1049,15 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > GAMT_CHKN_BIT_REG, > GAMT_CHKN_DISABLE_L3_COH_PIPE); > > + /* Wa_1407352427:icl,ehl */ > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > + PSDUNIT_CLKGATE_DIS); > + > + /* Wa_1406680159:icl,ehl */ > + wa_write_or(wal, > + SUBSLICE_UNIT_LEVEL_CLKGATE, > + GWUNIT_CLKGATE_DIS); > + > /* Wa_1607087056:icl,ehl,jsl */ > if (IS_ICELAKE(i915) || > IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0)) > @@ -1745,15 +1754,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); > > - /* Wa_1407352427:icl,ehl */ > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > - PSDUNIT_CLKGATE_DIS); > - > - /* Wa_1406680159:icl,ehl */ > - wa_write_or(wal, > - SUBSLICE_UNIT_LEVEL_CLKGATE, > - GWUNIT_CLKGATE_DIS); > - > /* > * Wa_1408767742:icl[a2..forever],ehl[all] > * Wa_1605460711:icl[a0..c0]
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6b5ab19a2ada..0dda8f6da423 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1049,6 +1049,15 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); + /* Wa_1407352427:icl,ehl */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + PSDUNIT_CLKGATE_DIS); + + /* Wa_1406680159:icl,ehl */ + wa_write_or(wal, + SUBSLICE_UNIT_LEVEL_CLKGATE, + GWUNIT_CLKGATE_DIS); + /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0)) @@ -1745,15 +1754,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); - /* Wa_1407352427:icl,ehl */ - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, - PSDUNIT_CLKGATE_DIS); - - /* Wa_1406680159:icl,ehl */ - wa_write_or(wal, - SUBSLICE_UNIT_LEVEL_CLKGATE, - GWUNIT_CLKGATE_DIS); - /* * Wa_1408767742:icl[a2..forever],ehl[all] * Wa_1605460711:icl[a0..c0]