@@ -21,7 +21,7 @@
#include "mlxbf_gige_regs.h"
#define DRV_NAME "mlxbf_gige"
-#define DRV_VERSION "1.10"
+#define DRV_VERSION "1.9"
static void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv,
unsigned int index, u64 dmac)
@@ -78,6 +78,10 @@
#define MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE 0x98
#define MLXBF_GIGE_GPIO12_BIT 12
+#define MLXBF_GIGE_CAUSE_OR_CAUSE_EVTEN0_MASK BIT(MLXBF_GIGE_GPIO12_BIT)
+#define MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK BIT(MLXBF_GIGE_GPIO12_BIT)
+#define MLXBF_GIGE_CAUSE_FALL_EN_MASK BIT(MLXBF_GIGE_GPIO12_BIT)
+#define MLXBF_GIGE_CAUSE_OR_CLRCAUSE_MASK BIT(MLXBF_GIGE_GPIO12_BIT)
static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add,
int phy_reg, u32 opcode)
@@ -156,7 +160,7 @@ static void mlxbf_gige_mdio_disable_phy_int(struct mlxbf_gige *priv)
spin_lock_irqsave(&priv->gpio_lock, flags);
val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
- val &= ~priv->phy_int_gpio_mask;
+ val &= ~MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK;
writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
spin_unlock_irqrestore(&priv->gpio_lock, flags);
}
@@ -172,13 +176,13 @@ static void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv)
* state goes low.
*/
val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_FALL_EN);
- val |= priv->phy_int_gpio_mask;
+ val |= MLXBF_GIGE_CAUSE_FALL_EN_MASK;
writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_FALL_EN);
/* Enable PHY interrupt by setting the priority level */
val = readl(priv->gpio_io +
MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
- val |= priv->phy_int_gpio_mask;
+ val |= MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK;
writel(val, priv->gpio_io +
MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
spin_unlock_irqrestore(&priv->gpio_lock, flags);
@@ -201,7 +205,7 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id)
*/
val = readl(priv->gpio_io +
MLXBF_GIGE_GPIO_CAUSE_OR_CAUSE_EVTEN0);
- if (!(val & priv->phy_int_gpio_mask))
+ if (!(val & MLXBF_GIGE_CAUSE_OR_CAUSE_EVTEN0_MASK))
return IRQ_NONE;
phy_mac_interrupt(phydev);
@@ -211,7 +215,7 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id)
*/
val = readl(priv->gpio_io +
MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE);
- val |= priv->phy_int_gpio_mask;
+ val |= MLXBF_GIGE_CAUSE_OR_CLRCAUSE_MASK;
writel(val, priv->gpio_io +
MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE);
@@ -230,7 +234,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
{
struct device *dev = &pdev->dev;
struct resource *res;
- u32 phy_int_gpio;
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_MDIO9);
@@ -253,11 +256,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
writel(MLXBF_GIGE_MDIO_CFG_VAL,
priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
- ret = device_property_read_u32(dev, "phy-int-gpio", &phy_int_gpio);
- if (ret < 0)
- phy_int_gpio = MLXBF_GIGE_GPIO12_BIT;
- priv->phy_int_gpio_mask = BIT(phy_int_gpio);
-
mlxbf_gige_mdio_enable_phy_int(priv);
priv->mdiobus = devm_mdiobus_alloc(dev);
BugLink: https://bugs.launchpad.net/bugs/1934923 This reverts commit b418d3395a83a3e9c5c93bb44a07957ed5402904. Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> --- .../mellanox/mlxbf_gige/mlxbf_gige_main.c | 2 +- .../mellanox/mlxbf_gige/mlxbf_gige_mdio.c | 20 +++++++++---------- 2 files changed, 10 insertions(+), 12 deletions(-)