diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
index f89199d562ad..a32e5da07f56 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
@@ -4,7 +4,7 @@
  * - this file contains software data structures and any chip-specific
  *   data structures (e.g. TX WQE format) that are memory resident.
  *
- * Copyright (c) 2020 Mellanox Technologies Ltd.
+ * Copyright (c) 2020, Mellanox Technologies
  */
 
 #ifndef __MLXBF_GIGE_H__
@@ -48,7 +48,7 @@
 #define MLXBF_GIGE_LLU_PLU_INTR_IDX     2
 #define MLXBF_GIGE_PHY_INT_N            3
 
-#define MLXBF_GIGE_MDIO_DEFAULT_PHY_ADDR 0x3
+#define MLXBF_GIGE_DEFAULT_PHY_ADDR	0x3
 
 struct mlxbf_gige_stats {
 	u64 hw_access_errors;
@@ -77,7 +77,6 @@ struct mlxbf_gige {
 	void __iomem *gpio_io;
 	void __iomem *cause_rsh_coalesce0_io;
 	void __iomem *cause_gpio_arm_coalesce0_io;
-	u32 phy_int_gpio_mask;
 	spinlock_t lock;
 	spinlock_t gpio_lock;
 	u16 rx_q_entries;
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
index d074bf9ef5c2..75263fcd542e 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
@@ -2,7 +2,7 @@
 
 /* Gigabit Ethernet driver for Mellanox BlueField SoC
  *
- * Copyright (c) 2020 Mellanox Technologies Ltd.
+ * Copyright (c) 2020, Mellanox Technologies
  */
 
 #include <linux/acpi.h>
@@ -631,8 +631,8 @@ static u16 mlxbf_gige_tx_buffs_avail(struct mlxbf_gige *priv)
 	if (priv->prev_tx_ci == priv->tx_pi)
 		avail = priv->tx_q_entries - 1;
 	else
-		avail = ((priv->tx_q_entries + priv->prev_tx_ci - priv->tx_pi)
-			  % priv->tx_q_entries) - 1;
+		avail = (((priv->tx_q_entries + priv->prev_tx_ci - priv->tx_pi)
+			  % priv->tx_q_entries) - 1);
 
 	spin_unlock_irqrestore(&priv->lock, flags);
 
@@ -665,8 +665,8 @@ static bool mlxbf_gige_handle_tx_complete(struct mlxbf_gige *priv)
 		 * buffer address and the 8 LSB contain information
 		 * about the TX WQE.
 		 */
-		tx_wqe_addr = priv->tx_wqe_base +
-			       (tx_wqe_index * MLXBF_GIGE_TX_WQE_SZ_QWORDS);
+		tx_wqe_addr = (priv->tx_wqe_base +
+			       (tx_wqe_index * MLXBF_GIGE_TX_WQE_SZ_QWORDS));
 
 		stats->tx_packets++;
 		stats->tx_bytes += MLXBF_GIGE_TX_WQE_PKT_LEN(tx_wqe_addr);
@@ -934,12 +934,6 @@ static netdev_tx_t mlxbf_gige_start_xmit(struct sk_buff *skb,
 		/* TX ring is full, inform stack but do not free SKB */
 		netif_stop_queue(netdev);
 		netdev->stats.tx_dropped++;
-		/* Since there is no separate "TX complete" interrupt, need
-		 * to explicitly schedule NAPI poll.  This will trigger logic
-		 * which processes TX completions, and will hopefully drain
-		 * the TX ring allowing the TX queue to be awakened.
-		 */
-		napi_schedule(&priv->napi);
 		return NETDEV_TX_BUSY;
 	}
 
@@ -980,9 +974,6 @@ static netdev_tx_t mlxbf_gige_start_xmit(struct sk_buff *skb,
 
 	priv->tx_pi++;
 
-	/* Create memory barrier before write to TX PI */
-	wmb();
-
 	writeq(priv->tx_pi, priv->base + MLXBF_GIGE_TX_PRODUCER_INDEX);
 
 	/* Free incoming skb, contents already copied to HW */
@@ -1017,8 +1008,8 @@ static void mlxbf_gige_set_rx_mode(struct net_device *netdev)
 			mlxbf_gige_enable_promisc(priv);
 		else
 			mlxbf_gige_disable_promisc(priv);
-		}
 	}
+}
 
 static const struct net_device_ops mlxbf_gige_netdev_ops = {
 	.ndo_open		= mlxbf_gige_open,
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
index 7a225036ab59..200a221deb3e 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
@@ -1,11 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0-only OR Linux-OpenIB
 /*  MDIO support for Mellanox GigE driver
  *
- *  Copyright (c) 2020 Mellanox Technologies Ltd.
+ *  Copyright (C) 2020 Mellanox Technologies, Ltd.
  */
 
 #include <linux/acpi.h>
-#include <linux/bitfield.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -21,38 +20,45 @@
 
 #include "mlxbf_gige.h"
 
-#define MLXBF_GIGE_MDIO_POLL_BUSY_TIMEOUT	100 /* ms */
-#define MLXBF_GIGE_MDIO_POLL_DELAY_USEC		100 /* us */
+#define MLXBF_GIGE_POLL_BUSY_TIMEOUT	100 /* ms */
+#define MLXBF_GIGE_POLL_DELAY_USEC	100 /* microsec */
 
 #define MLXBF_GIGE_MDIO_GW_OFFSET	0x0
 #define MLXBF_GIGE_MDIO_CFG_OFFSET	0x4
 
 /* Support clause 22 */
-#define MLXBF_GIGE_MDIO_CL22_ST1	0x1
-#define MLXBF_GIGE_MDIO_CL22_WRITE	0x1
-#define MLXBF_GIGE_MDIO_CL22_READ	0x2
+#define MLXBF_GIGE_CL22_ST1	        0x1
+#define MLXBF_GIGE_CL22_MDIO_WRITE	0x1
+#define MLXBF_GIGE_CL22_MDIO_READ	0x2
 
 /* Busy bit is set by software and cleared by hardware */
-#define MLXBF_GIGE_MDIO_SET_BUSY	0x1
+#define MLXBF_GIGE_SET_MDIO_BUSY	0x1
 /* Lock bit should be set/cleared by software */
-#define MLXBF_GIGE_MDIO_SET_LOCK	0x1
+#define MLXBF_GIGE_SET_MDIO_LOCK	0x1
 
 /* MDIO GW register bits */
-#define MLXBF_GIGE_MDIO_GW_AD_MASK	GENMASK(15, 0)
-#define MLXBF_GIGE_MDIO_GW_DEVAD_MASK	GENMASK(20, 16)
-#define MLXBF_GIGE_MDIO_GW_PARTAD_MASK	GENMASK(25, 21)
-#define MLXBF_GIGE_MDIO_GW_OPCODE_MASK	GENMASK(27, 26)
-#define MLXBF_GIGE_MDIO_GW_ST1_MASK	GENMASK(28, 28)
-#define MLXBF_GIGE_MDIO_GW_BUSY_MASK	GENMASK(30, 30)
-#define MLXBF_GIGE_MDIO_GW_LOCK_MASK	GENMASK(31, 31)
+#define MLXBF_GIGE_MDIO_GW_AD_SHIFT		0
+#define MLXBF_GIGE_MDIO_GW_AD_MASK		GENMASK(15, 0)
+#define MLXBF_GIGE_MDIO_GW_DEVAD_SHIFT		16
+#define MLXBF_GIGE_MDIO_GW_DEVAD_MASK		GENMASK(20, 16)
+#define MLXBF_GIGE_MDIO_GW_PARTAD_SHIFT		21
+#define MLXBF_GIGE_MDIO_GW_PARTAD_MASK		GENMASK(25, 21)
+#define MLXBF_GIGE_MDIO_GW_OPCODE_SHIFT		26
+#define MLXBF_GIGE_MDIO_GW_OPCODE_MASK		GENMASK(27, 26)
+#define MLXBF_GIGE_MDIO_GW_ST1_SHIFT		28
+#define MLXBF_GIGE_MDIO_GW_ST1_MASK		GENMASK(28, 28)
+#define MLXBF_GIGE_MDIO_GW_BUSY_SHIFT		30
+#define MLXBF_GIGE_MDIO_GW_BUSY_MASK		GENMASK(30, 30)
+#define MLXBF_GIGE_MDIO_GW_LOCK_SHIFT		31
+#define MLXBF_GIGE_MDIO_GW_LOCK_MASK		GENMASK(31, 31)
 
 /* MDIO config register bits */
-#define MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK		GENMASK(1, 0)
-#define MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK		GENMASK(2, 2)
-#define MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK	GENMASK(4, 4)
-#define MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK		GENMASK(15, 8)
-#define MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK		GENMASK(23, 16)
-#define MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK		GENMASK(31, 24)
+#define MLXBF_GIGE_MDIO_CFG_MDIO_MODE_SHIFT		0
+#define MLXBF_GIGE_MDIO_CFG_MDIO3_3_SHIFT		2
+#define MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_SHIFT	4
+#define MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_SHIFT		8
+#define MLXBF_GIGE_MDIO_CFG_MASTER_IN_SAMP_SHIFT	16
+#define MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_SHIFT		24
 
 /* Formula for encoding the MDIO period. The encoded value is
  * passed to the MDIO config register.
@@ -66,22 +72,26 @@
 #define MLXBF_GIGE_I1CLK_MHZ		430
 #define MLXBF_GIGE_MDC_CLK_NS		400
 
-#define MLXBF_GIGE_MDIO_PERIOD	(((MLXBF_GIGE_MDC_CLK_NS * MLXBF_GIGE_I1CLK_MHZ / 1000) / 2) - 1)
+#define MLXBF_GIGE_MDIO_PERIOD_VAL	(((MLXBF_GIGE_MDC_CLK_NS * MLXBF_GIGE_I1CLK_MHZ / 1000) / 2) - 1)
+#define MLXBF_GIGE_MDIO_PERIOD		(MLXBF_GIGE_MDIO_PERIOD_VAL << MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_SHIFT)
 
 /* PHY should operate in master mode only */
-#define MLXBF_GIGE_MDIO_MODE_MASTER	1
-
+#define MLXBF_GIGE_MDIO_MODE_MASTER	(0x1 << MLXBF_GIGE_MDIO_CFG_MDIO_MODE_SHIFT)
 /* PHY input voltage has to be 3.3V */
-#define MLXBF_GIGE_MDIO3_3		1
-
+#define MLXBF_GIGE_MDIO3_3		(0x1 << MLXBF_GIGE_MDIO_CFG_MDIO3_3_SHIFT)
 /* Operate in full drive mode */
-#define MLXBF_GIGE_MDIO_FULL_DRIVE	1
-
+#define MLXBF_GIGE_MDIO_FULL_DRIVE	(0x1 << MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_SHIFT)
 /* 6 cycles before the i1clk (core clock) rising edge that triggers the mdc */
-#define	MLXBF_GIGE_MDIO_IN_SAMP 	6
-
+#define	MLXBF_GIGE_MDIO_MASTER_IN_SAMP	(6 << MLXBF_GIGE_MDIO_CFG_MASTER_IN_SAMP_SHIFT)
 /* 13 cycles after the i1clk (core clock) rising edge that triggers the mdc */
-#define MLXBF_GIGE_MDIO_OUT_SAMP 	13
+#define MLXBF_GIGE_MDIO_MDIO_OUT_SAMP	(13 << MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_SHIFT)
+
+#define MLXBF_GIGE_MDIO_CFG_VAL (MLXBF_GIGE_MDIO_MODE_MASTER | \
+				 MLXBF_GIGE_MDIO3_3 | \
+				 MLXBF_GIGE_MDIO_FULL_DRIVE | \
+				 MLXBF_GIGE_MDIO_PERIOD | \
+				 MLXBF_GIGE_MDIO_MASTER_IN_SAMP | \
+				 MLXBF_GIGE_MDIO_MDIO_OUT_SAMP)
 
 /* The PHY interrupt line is shared with other interrupt lines such
  * as GPIO and SMBus. So use YU registers to determine whether the
@@ -99,26 +109,34 @@
 #define MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE	0x98
 
 #define MLXBF_GIGE_GPIO12_BIT			12
+#define MLXBF_GIGE_CAUSE_OR_CAUSE_EVTEN0_MASK	BIT(MLXBF_GIGE_GPIO12_BIT)
+#define MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK		BIT(MLXBF_GIGE_GPIO12_BIT)
+#define MLXBF_GIGE_CAUSE_FALL_EN_MASK		BIT(MLXBF_GIGE_GPIO12_BIT)
+#define MLXBF_GIGE_CAUSE_OR_CLRCAUSE_MASK	BIT(MLXBF_GIGE_GPIO12_BIT)
 
 static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add,
 				      int phy_reg, u32 opcode)
 {
 	u32 gw_reg = 0;
 
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_AD_MASK, data);
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg);
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_PARTAD_MASK, phy_add);
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_OPCODE_MASK, opcode);
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_ST1_MASK,
-			     MLXBF_GIGE_MDIO_CL22_ST1);
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_BUSY_MASK,
-			     MLXBF_GIGE_MDIO_SET_BUSY);
+	gw_reg |= (data << MLXBF_GIGE_MDIO_GW_AD_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_AD_MASK;
+	gw_reg |= ((phy_reg << MLXBF_GIGE_MDIO_GW_DEVAD_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_DEVAD_MASK);
+	gw_reg |= ((phy_add << MLXBF_GIGE_MDIO_GW_PARTAD_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_PARTAD_MASK);
+	gw_reg |= ((opcode << MLXBF_GIGE_MDIO_GW_OPCODE_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_OPCODE_MASK);
+	gw_reg |= ((MLXBF_GIGE_CL22_ST1 << MLXBF_GIGE_MDIO_GW_ST1_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_ST1_MASK);
+	gw_reg |= ((MLXBF_GIGE_SET_MDIO_BUSY << MLXBF_GIGE_MDIO_GW_BUSY_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_BUSY_MASK);
 
 	/* Hold the lock until the read/write is completed so that no other
 	 * program accesses the mdio bus.
 	 */
-	gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_LOCK_MASK,
-			     MLXBF_GIGE_MDIO_SET_LOCK);
+	gw_reg |= ((MLXBF_GIGE_SET_MDIO_LOCK << MLXBF_GIGE_MDIO_GW_LOCK_SHIFT) &
+			MLXBF_GIGE_MDIO_GW_LOCK_MASK);
 
 	return gw_reg;
 }
@@ -128,12 +146,12 @@ static int mlxbf_gige_mdio_poll_bit(struct mlxbf_gige *priv, u32 bit_mask)
 	unsigned long timeout;
 	u32 val;
 
-	timeout = jiffies + msecs_to_jiffies(MLXBF_GIGE_MDIO_POLL_BUSY_TIMEOUT);
+	timeout = jiffies + msecs_to_jiffies(MLXBF_GIGE_POLL_BUSY_TIMEOUT);
 	do {
 		val = readl(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
 		if (!(val & bit_mask))
 			return 0;
-		udelay(MLXBF_GIGE_MDIO_POLL_DELAY_USEC);
+		udelay(MLXBF_GIGE_POLL_DELAY_USEC);
 	} while (time_before(jiffies, timeout));
 
 	return -ETIME;
@@ -153,7 +171,7 @@ static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
 		return -EBUSY;
 
 	/* Send mdio read request */
-	cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_MDIO_CL22_READ);
+	cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_CL22_MDIO_READ);
 
 	writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
 
@@ -192,7 +210,7 @@ static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
 
 	/* Send mdio write request */
 	cmd = mlxbf_gige_mdio_create_cmd(val, phy_add, phy_reg,
-					 MLXBF_GIGE_MDIO_CL22_WRITE);
+					 MLXBF_GIGE_CL22_MDIO_WRITE);
 	writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
 
 	/* If the poll timed out, drop the request */
@@ -207,19 +225,19 @@ static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
 	return ret;
 }
 
-static void mlxbf_gige_mdio_disable_phy_int(struct mlxbf_gige *priv)
+static void mlxbf_gige_mdio_disable_gpio12_irq(struct mlxbf_gige *priv)
 {
 	unsigned long flags;
 	u32 val;
 
 	spin_lock_irqsave(&priv->gpio_lock, flags);
 	val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
-	val &= ~priv->phy_int_gpio_mask;
+	val &= ~MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK;
 	writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
 	spin_unlock_irqrestore(&priv->gpio_lock, flags);
 }
 
-static void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv)
+static void mlxbf_gige_mdio_enable_gpio12_irq(struct mlxbf_gige *priv)
 {
 	unsigned long flags;
 	u32 val;
@@ -230,13 +248,13 @@ static void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv)
 	 * state goes low.
 	 */
 	val = readl(priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_FALL_EN);
-	val |= priv->phy_int_gpio_mask;
+	val |= MLXBF_GIGE_CAUSE_FALL_EN_MASK;
 	writel(val, priv->gpio_io + MLXBF_GIGE_GPIO_CAUSE_FALL_EN);
 
-	/* Enable PHY interrupt by setting the priority level */
+	/* Enable GPIO 12 interrupt by setting the priority level */
 	val = readl(priv->gpio_io +
 			MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
-	val |= priv->phy_int_gpio_mask;
+	val |= MLXBF_GIGE_CAUSE_OR_EVTEN0_MASK;
 	writel(val, priv->gpio_io +
 			MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0);
 	spin_unlock_irqrestore(&priv->gpio_lock, flags);
@@ -264,84 +282,36 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(struct mlxbf_gige *priv)
 	if (!(val & MLXBF_GIGE_GPIO_BLOCK0_MASK))
 		return IRQ_NONE;
 
-	/* Finally check if this interrupt is from PHY device.
+	/* Finally check if this interrupt is for gpio pin 12.
 	 * Return if it is not.
 	 */
 	val = readl(priv->gpio_io +
 			MLXBF_GIGE_GPIO_CAUSE_OR_CAUSE_EVTEN0);
-	if (!(val & priv->phy_int_gpio_mask))
+	if (!(val & MLXBF_GIGE_CAUSE_OR_CAUSE_EVTEN0_MASK))
 		return IRQ_NONE;
 
 	/* Clear interrupt when done, otherwise, no further interrupt
 	 * will be triggered.
-	 * Writing 0x1 to the clear cause register also clears the
+	 * Writing 0x1 to the clrcause register also clears the
 	 * following registers:
 	 * cause_gpio_arm_coalesce0
 	 * cause_rsh_coalesce0
 	 */
 	val = readl(priv->gpio_io +
 			MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE);
-	val |= priv->phy_int_gpio_mask;
+	val |= MLXBF_GIGE_CAUSE_OR_CLRCAUSE_MASK;
 	writel(val, priv->gpio_io +
 			MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE);
 
 	return IRQ_HANDLED;
 }
 
-static void mlxbf_gige_mdio_init_config(struct mlxbf_gige *priv)
-{
-	struct device *dev = priv->dev;
-	u32 mdio_full_drive;
-	u32 mdio_out_sample;
-	u32 mdio_in_sample;
-	u32 mdio_voltage;
-	u32 mdc_period;
-	u32 mdio_mode;
-	u32 mdio_cfg;
-	int ret;
-
-	ret = device_property_read_u32(dev, "mdio-mode", &mdio_mode);
-	if (ret < 0)
-		mdio_mode = MLXBF_GIGE_MDIO_MODE_MASTER;
-
-	ret = device_property_read_u32(dev, "mdio-voltage", &mdio_voltage);
-	if (ret < 0)
-		mdio_voltage = MLXBF_GIGE_MDIO3_3;
-
-	ret = device_property_read_u32(dev, "mdio-full-drive", &mdio_full_drive);
-	if (ret < 0)
-		mdio_full_drive = MLXBF_GIGE_MDIO_FULL_DRIVE;
-
-	ret = device_property_read_u32(dev, "mdc-period", &mdc_period);
-	if (ret < 0)
-		mdc_period = MLXBF_GIGE_MDIO_PERIOD;
-
-	ret = device_property_read_u32(dev, "mdio-in-sample", &mdio_in_sample);
-	if (ret < 0)
-		mdio_in_sample = MLXBF_GIGE_MDIO_IN_SAMP;
-
-	ret = device_property_read_u32(dev, "mdio-out-sample", &mdio_out_sample);
-	if (ret < 0)
-		mdio_out_sample = MLXBF_GIGE_MDIO_OUT_SAMP;
-
-	mdio_cfg = FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK, mdio_mode) |
-		   FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK, mdio_voltage) |
-		   FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, mdio_full_drive) |
-		   FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdc_period) |
-		   FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, mdio_in_sample) |
-		   FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, mdio_out_sample);
-
-	writel(mdio_cfg, priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
-}
-
 int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
 {
 	struct device *dev = &pdev->dev;
 	struct resource *res;
-	u32 phy_int_gpio;
 	u32 phy_addr;
 	int ret;
-	int irq;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_MDIO9);
 	if (!res)
@@ -379,14 +349,11 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
 	if (!priv->cause_gpio_arm_coalesce0_io)
 		return -ENOMEM;
 
-	mlxbf_gige_mdio_init_config(priv);
-
-	ret = device_property_read_u32(dev, "phy-int-gpio", &phy_int_gpio);
-	if (ret < 0)
-		phy_int_gpio = MLXBF_GIGE_GPIO12_BIT;
-	priv->phy_int_gpio_mask = BIT(phy_int_gpio);
+	/* Configure mdio parameters */
+	writel(MLXBF_GIGE_MDIO_CFG_VAL,
+	       priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
 
-	mlxbf_gige_mdio_enable_phy_int(priv);
+	mlxbf_gige_mdio_enable_gpio12_irq(priv);
 
 	priv->mdiobus = devm_mdiobus_alloc(dev);
 	if (!priv->mdiobus) {
@@ -404,13 +371,8 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
 
 	ret = device_property_read_u32(dev, "phy-addr", &phy_addr);
 	if (ret < 0)
-		phy_addr = MLXBF_GIGE_MDIO_DEFAULT_PHY_ADDR;
+		phy_addr = MLXBF_GIGE_DEFAULT_PHY_ADDR;
 
-	irq = platform_get_irq(pdev, MLXBF_GIGE_PHY_INT_N);
-	if (irq < 0) {
-		dev_err(dev, "Failed to retrieve irq 0x%x\n", irq);
-		return -ENODEV;
-	}
 	priv->mdiobus->irq[phy_addr] = PHY_POLL;
 
 	/* Auto probe PHY at the corresponding address */
@@ -424,6 +386,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
 
 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv)
 {
-	mlxbf_gige_mdio_disable_phy_int(priv);
+	mlxbf_gige_mdio_disable_gpio12_irq(priv);
 	mdiobus_unregister(priv->mdiobus);
 }
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h
index 9c7af820c197..ff490c70fff1 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h
@@ -2,7 +2,7 @@
 
 /* Header file for Mellanox BlueField GigE register defines
  *
- * Copyright (c) 2020 Mellanox Technologies Ltd.
+ * Copyright (c) 2020, Mellanox Technologies
  */
 
 #ifndef __MLXBF_GIGE_REGS_H__
