From patchwork Wed Jul 7 13:22:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1501732 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKg856vSrz9srX; Wed, 7 Jul 2021 23:22:29 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1m17VR-00083Y-Qv; Wed, 07 Jul 2021 13:22:25 +0000 Received: from mail-pf1-f174.google.com ([209.85.210.174]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1m17VQ-000833-Ca for kernel-team@lists.ubuntu.com; Wed, 07 Jul 2021 13:22:24 +0000 Received: by mail-pf1-f174.google.com with SMTP id q10so2087493pfj.12 for ; Wed, 07 Jul 2021 06:22:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rZhs/VmnfIP8qJcjwyB3JZuBdwTG3jRvkBAJsrPCA/w=; b=loOD96/p0qfN7foTOPVuyFTNhUmKSVjT/ryR8K5Za7k9cPpmoeMg2Z+PKw/SEgTFeA FKXvdteAaKVoV/6iiKtpFqocfcYhT6a66+Y3J7Q3mD4y0YuQg1f2pTVacpkBlIyMV7l/ 3ZRnAAmg8wdNNjO1CdN+prfws2WVkg1fXJNVtF61qS4p6uwTfBIyjZsWbFD9fFCACxTN LL6KZuZ2MoCyxNk4df+xGJQ3/XoR2Uj3CtWAtuDwRbxmsQuNzGZVSxglzHDeZB/zPGLi xqd4HsiaJFS+Xtu5mcVTBwUm7sP1ZeEAKC8+JlWPINEIYvFhMsR1zPgdDweWXeKnuvdO EKvw== X-Gm-Message-State: AOAM533RluittLcpo35NGdshYdTtaSNMJeE30v9ml1hopzYGlzYfuT75 FGDXGQPPCIinJJl2Dh5bqQXZpNPOsIE+Vw== X-Google-Smtp-Source: ABdhPJxZvbqBqDyB2sK2CxvxXh74CFRQTWZMOzB7jK1LcJtjWNu5i3B3GYn0+RQBOuH0Z4dgiDjWZA== X-Received: by 2002:a62:3344:0:b029:25e:a0a8:1c51 with SMTP id z65-20020a6233440000b029025ea0a81c51mr25675080pfz.58.1625664142422; Wed, 07 Jul 2021 06:22:22 -0700 (PDT) Received: from localhost ([159.117.79.148]) by smtp.gmail.com with ESMTPSA id q3sm2967209pfb.184.2021.07.07.06.22.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jul 2021 06:22:22 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 2/4][SRU][U/OEM-5.13] UBUNTU: SAUCE: platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR) support to Alder Lake Date: Wed, 7 Jul 2021 21:22:15 +0800 Message-Id: <20210707132217.311805-3-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210707132217.311805-1-vicamo.yang@canonical.com> References: <20210707132217.311805-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.174; envelope-from=vicamo@gmail.com; helo=mail-pf1-f174.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Gayatri Kammela BugLink: https://bugs.launchpad.net/bugs/1934660 Add support to show the Latency Tolerance Reporting for the IPs on the Alder Lake PCH as reported by the PMC. This LTR support on Alder Lake is slightly different from the Cannon lake PCH that is being reused by all platforms till Tiger Lake. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Signed-off-by: Gayatri Kammela (cherry picked from https://patchwork.kernel.org/project/platform-driver-x86/patch/0b1409212c2f84aa807e5315955c8e74903d031a.1625191274.git.gayatri.kammela@intel.com/) Signed-off-by: You-Sheng Yang --- drivers/platform/x86/intel_pmc_core.c | 39 +++++++++++++++++++++++++++ drivers/platform/x86/intel_pmc_core.h | 2 ++ 2 files changed, 41 insertions(+) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 441018e3ce96..611019bfe685 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -699,10 +699,48 @@ static const struct pmc_bit_map *ext_adl_pfear_map[] = { NULL }; +static const struct pmc_bit_map adl_ltr_show_map[] = { + {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, + {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, + {"SATA", CNP_PMC_LTR_SATA}, + {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, + {"XHCI", CNP_PMC_LTR_XHCI}, + {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, + {"ME", CNP_PMC_LTR_ME}, + /* EVA is Enterprise Value Add, doesn't really exist on PCH */ + {"SATA1", CNP_PMC_LTR_EVA}, + {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, + {"HD_AUDIO", CNP_PMC_LTR_AZ}, + {"CNV", CNP_PMC_LTR_CNV}, + {"LPSS", CNP_PMC_LTR_LPSS}, + {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, + {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, + {"SATA2", CNP_PMC_LTR_CAM}, + {"ESPI", CNP_PMC_LTR_ESPI}, + {"SCC", CNP_PMC_LTR_SCC}, + {"ISH", CNP_PMC_LTR_ISH}, + {"UFSX2", CNP_PMC_LTR_UFSX2}, + {"EMMC", CNP_PMC_LTR_EMMC}, + /* + * Check intel_pmc_core_ids[] users of cnp_reg_map for + * a list of core SoCs using this. + */ + {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0", TGL_PMC_LTR_THC0}, + {"THC1", TGL_PMC_LTR_THC1}, + {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED}, + + /* Below two cannot be used for LTR_IGNORE */ + {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, + {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, + {} +}; + static const struct pmc_reg_map adl_reg_map = { .pfear_sts = ext_adl_pfear_map, .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, + .ltr_show_sts = adl_ltr_show_map, .msr_sts = msr_map, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .regmap_length = CNP_PMC_MMIO_REG_LEN, @@ -710,6 +748,7 @@ static const struct pmc_reg_map adl_reg_map = { .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index c0ca20b32c6b..45b352ece6db 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -197,6 +197,8 @@ enum ppfear_regs { #define TGL_NUM_IP_IGN_ALLOWED 23 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ +#define ADL_PMC_LTR_SPF 0x1C00 +#define ADL_NUM_IP_IGN_ALLOWED 23 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 /*