diff mbox series

[SRU,Groovy] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo

Message ID 20210415121130.9830-1-ioanna-maria.alifieraki@canonical.com
State New
Headers show
Series [SRU,Groovy] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo | expand

Commit Message

Ioanna Alifieraki April 15, 2021, 12:11 p.m. UTC
From: Bhupesh Sharma <bhsharma@redhat.com>

https://bugs.launchpad.net/bugs/1919275

TCR_EL1.TxSZ, which controls the VA space size, is configured by a
single kernel image to support either 48-bit or 52-bit VA space.

If the ARMv8.2-LVA optional feature is present and we are running
with a 64KB page size, then it is possible to use 52-bits of address
space for both userspace and kernel addresses. However, any kernel
binary that supports 52-bit must also be able to fall back to 48-bit
at early boot time if the hardware feature is not present.

Since TCR_EL1.T1SZ indicates the size of the memory region addressed by
TTBR1_EL1, export the same in vmcoreinfo. User-space utilities like
makedumpfile and crash-utility need to read this value from vmcoreinfo
for determining if a virtual address lies in the linear map range.

While at it also add documentation for TCR_EL1.T1SZ variable being
added to vmcoreinfo.

It indicates the size offset of the memory region addressed by
TTBR1_EL1.

Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
Tested-by: John Donnelly <john.p.donnelly@oracle.com>
Tested-by: Kamlakant Patel <kamlakantp@marvell.com>
Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Dave Anderson <anderson@redhat.com>
Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: kexec@lists.infradead.org
Link: https://lore.kernel.org/r/1589395957-24628-3-git-send-email-bhsharma@redhat.com
[catalin.marinas@arm.com: removed vabits_actual from the commit log]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit bbdbc11804ff0b4130e7550113b452e96a74d16e)
Signed-off-by: Ioanna Alifieraki <ioanna-maria.alifieraki@canonical.com>
---
 Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++
 arch/arm64/include/asm/pgtable-hwdef.h         |  1 +
 arch/arm64/kernel/crash_core.c                 | 10 ++++++++++
 3 files changed, 22 insertions(+)

Comments

Tim Gardner April 15, 2021, 1:29 p.m. UTC | #1
Acked-by: Tim Gardner <tim.gardner@canonical.com>

On 4/15/21 6:11 AM, Ioanna Alifieraki wrote:
> From: Bhupesh Sharma <bhsharma@redhat.com>
> 
> https://bugs.launchpad.net/bugs/1919275
> 
> TCR_EL1.TxSZ, which controls the VA space size, is configured by a
> single kernel image to support either 48-bit or 52-bit VA space.
> 
> If the ARMv8.2-LVA optional feature is present and we are running
> with a 64KB page size, then it is possible to use 52-bits of address
> space for both userspace and kernel addresses. However, any kernel
> binary that supports 52-bit must also be able to fall back to 48-bit
> at early boot time if the hardware feature is not present.
> 
> Since TCR_EL1.T1SZ indicates the size of the memory region addressed by
> TTBR1_EL1, export the same in vmcoreinfo. User-space utilities like
> makedumpfile and crash-utility need to read this value from vmcoreinfo
> for determining if a virtual address lies in the linear map range.
> 
> While at it also add documentation for TCR_EL1.T1SZ variable being
> added to vmcoreinfo.
> 
> It indicates the size offset of the memory region addressed by
> TTBR1_EL1.
> 
> Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
> Tested-by: John Donnelly <john.p.donnelly@oracle.com>
> Tested-by: Kamlakant Patel <kamlakantp@marvell.com>
> Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> Reviewed-by: James Morse <james.morse@arm.com>
> Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Steve Capper <steve.capper@arm.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Dave Anderson <anderson@redhat.com>
> Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: kexec@lists.infradead.org
> Link: https://lore.kernel.org/r/1589395957-24628-3-git-send-email-bhsharma@redhat.com
> [catalin.marinas@arm.com: removed vabits_actual from the commit log]
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> (cherry picked from commit bbdbc11804ff0b4130e7550113b452e96a74d16e)
> Signed-off-by: Ioanna Alifieraki <ioanna-maria.alifieraki@canonical.com>
> ---
>   Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++
>   arch/arm64/include/asm/pgtable-hwdef.h         |  1 +
>   arch/arm64/kernel/crash_core.c                 | 10 ++++++++++
>   3 files changed, 22 insertions(+)
> 
> diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst
> index e4ee8b2db604..a0c62f1c0c02 100644
> --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst
> +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst
> @@ -399,6 +399,17 @@ KERNELPACMASK
>   The mask to extract the Pointer Authentication Code from a kernel virtual
>   address.
>   
> +TCR_EL1.T1SZ
> +------------
> +
> +Indicates the size offset of the memory region addressed by TTBR1_EL1.
> +The region size is 2^(64-T1SZ) bytes.
> +
> +TTBR1_EL1 is the table base address register specified by ARMv8-A
> +architecture which is used to lookup the page-tables for the Virtual
> +addresses in the higher VA range (refer to ARMv8 ARM document for
> +more details).
> +
>   arm
>   ===
>   
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index 9c91a8f93a0e..9a757d724974 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -216,6 +216,7 @@
>   #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
>   #define TCR_TxSZ_WIDTH		6
>   #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
> +#define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
>   
>   #define TCR_EPD0_SHIFT		7
>   #define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
> diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c
> index 1f646b07e3e9..314391a156ee 100644
> --- a/arch/arm64/kernel/crash_core.c
> +++ b/arch/arm64/kernel/crash_core.c
> @@ -7,6 +7,14 @@
>   #include <linux/crash_core.h>
>   #include <asm/cpufeature.h>
>   #include <asm/memory.h>
> +#include <asm/pgtable-hwdef.h>
> +
> +static inline u64 get_tcr_el1_t1sz(void);
> +
> +static inline u64 get_tcr_el1_t1sz(void)
> +{
> +	return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
> +}
>   
>   void arch_crash_save_vmcoreinfo(void)
>   {
> @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void)
>   						kimage_voffset);
>   	vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n",
>   						PHYS_OFFSET);
> +	vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n",
> +						get_tcr_el1_t1sz());
>   	vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
>   	vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n",
>   						system_supports_address_auth() ?
>
Guilherme Piccoli April 15, 2021, 2:34 p.m. UTC | #2
On 15/04/2021 09:11, Ioanna Alifieraki wrote:
> From: Bhupesh Sharma <bhsharma@redhat.com>
> 
> https://bugs.launchpad.net/bugs/1919275
> 
> TCR_EL1.TxSZ, which controls the VA space size, is configured by a
> single kernel image to support either 48-bit or 52-bit VA space.
> 
> If the ARMv8.2-LVA optional feature is present and we are running
> with a 64KB page size, then it is possible to use 52-bits of address
> space for both userspace and kernel addresses. However, any kernel
> binary that supports 52-bit must also be able to fall back to 48-bit
> at early boot time if the hardware feature is not present.
> 
> Since TCR_EL1.T1SZ indicates the size of the memory region addressed by
> TTBR1_EL1, export the same in vmcoreinfo. User-space utilities like
> makedumpfile and crash-utility need to read this value from vmcoreinfo
> for determining if a virtual address lies in the linear map range.
> 
> While at it also add documentation for TCR_EL1.T1SZ variable being
> added to vmcoreinfo.
> 
> It indicates the size offset of the memory region addressed by
> TTBR1_EL1.
> 
> Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
> Tested-by: John Donnelly <john.p.donnelly@oracle.com>
> Tested-by: Kamlakant Patel <kamlakantp@marvell.com>
> Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> Reviewed-by: James Morse <james.morse@arm.com>
> Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Steve Capper <steve.capper@arm.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Dave Anderson <anderson@redhat.com>
> Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: kexec@lists.infradead.org
> Link: https://lore.kernel.org/r/1589395957-24628-3-git-send-email-bhsharma@redhat.com
> [catalin.marinas@arm.com: removed vabits_actual from the commit log]
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> (cherry picked from commit bbdbc11804ff0b4130e7550113b452e96a74d16e)
> Signed-off-by: Ioanna Alifieraki <ioanna-maria.alifieraki@canonical.com>

Thanks Jo, LGTM:
Acked-by: Guilherme G. Piccoli <gpiccoli@canonical.com>
Stefan Bader April 23, 2021, 9:07 a.m. UTC | #3
On 15.04.21 14:11, Ioanna Alifieraki wrote:
> From: Bhupesh Sharma <bhsharma@redhat.com>
> 
> https://bugs.launchpad.net/bugs/1919275
> 
> TCR_EL1.TxSZ, which controls the VA space size, is configured by a
> single kernel image to support either 48-bit or 52-bit VA space.
> 
> If the ARMv8.2-LVA optional feature is present and we are running
> with a 64KB page size, then it is possible to use 52-bits of address
> space for both userspace and kernel addresses. However, any kernel
> binary that supports 52-bit must also be able to fall back to 48-bit
> at early boot time if the hardware feature is not present.
> 
> Since TCR_EL1.T1SZ indicates the size of the memory region addressed by
> TTBR1_EL1, export the same in vmcoreinfo. User-space utilities like
> makedumpfile and crash-utility need to read this value from vmcoreinfo
> for determining if a virtual address lies in the linear map range.
> 
> While at it also add documentation for TCR_EL1.T1SZ variable being
> added to vmcoreinfo.
> 
> It indicates the size offset of the memory region addressed by
> TTBR1_EL1.
> 
> Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
> Tested-by: John Donnelly <john.p.donnelly@oracle.com>
> Tested-by: Kamlakant Patel <kamlakantp@marvell.com>
> Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> Reviewed-by: James Morse <james.morse@arm.com>
> Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Steve Capper <steve.capper@arm.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Dave Anderson <anderson@redhat.com>
> Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: kexec@lists.infradead.org
> Link: https://lore.kernel.org/r/1589395957-24628-3-git-send-email-bhsharma@redhat.com
> [catalin.marinas@arm.com: removed vabits_actual from the commit log]
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> (cherry picked from commit bbdbc11804ff0b4130e7550113b452e96a74d16e)
> Signed-off-by: Ioanna Alifieraki <ioanna-maria.alifieraki@canonical.com>
> ---

Applied to groovy:linux/master-next. Thanks.

-Stefan

>   Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++
>   arch/arm64/include/asm/pgtable-hwdef.h         |  1 +
>   arch/arm64/kernel/crash_core.c                 | 10 ++++++++++
>   3 files changed, 22 insertions(+)
> 
> diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst
> index e4ee8b2db604..a0c62f1c0c02 100644
> --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst
> +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst
> @@ -399,6 +399,17 @@ KERNELPACMASK
>   The mask to extract the Pointer Authentication Code from a kernel virtual
>   address.
>   
> +TCR_EL1.T1SZ
> +------------
> +
> +Indicates the size offset of the memory region addressed by TTBR1_EL1.
> +The region size is 2^(64-T1SZ) bytes.
> +
> +TTBR1_EL1 is the table base address register specified by ARMv8-A
> +architecture which is used to lookup the page-tables for the Virtual
> +addresses in the higher VA range (refer to ARMv8 ARM document for
> +more details).
> +
>   arm
>   ===
>   
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index 9c91a8f93a0e..9a757d724974 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -216,6 +216,7 @@
>   #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
>   #define TCR_TxSZ_WIDTH		6
>   #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
> +#define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
>   
>   #define TCR_EPD0_SHIFT		7
>   #define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
> diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c
> index 1f646b07e3e9..314391a156ee 100644
> --- a/arch/arm64/kernel/crash_core.c
> +++ b/arch/arm64/kernel/crash_core.c
> @@ -7,6 +7,14 @@
>   #include <linux/crash_core.h>
>   #include <asm/cpufeature.h>
>   #include <asm/memory.h>
> +#include <asm/pgtable-hwdef.h>
> +
> +static inline u64 get_tcr_el1_t1sz(void);
> +
> +static inline u64 get_tcr_el1_t1sz(void)
> +{
> +	return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
> +}
>   
>   void arch_crash_save_vmcoreinfo(void)
>   {
> @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void)
>   						kimage_voffset);
>   	vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n",
>   						PHYS_OFFSET);
> +	vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n",
> +						get_tcr_el1_t1sz());
>   	vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
>   	vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n",
>   						system_supports_address_auth() ?
>
diff mbox series

Patch

diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst
index e4ee8b2db604..a0c62f1c0c02 100644
--- a/Documentation/admin-guide/kdump/vmcoreinfo.rst
+++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst
@@ -399,6 +399,17 @@  KERNELPACMASK
 The mask to extract the Pointer Authentication Code from a kernel virtual
 address.
 
+TCR_EL1.T1SZ
+------------
+
+Indicates the size offset of the memory region addressed by TTBR1_EL1.
+The region size is 2^(64-T1SZ) bytes.
+
+TTBR1_EL1 is the table base address register specified by ARMv8-A
+architecture which is used to lookup the page-tables for the Virtual
+addresses in the higher VA range (refer to ARMv8 ARM document for
+more details).
+
 arm
 ===
 
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 9c91a8f93a0e..9a757d724974 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -216,6 +216,7 @@ 
 #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
 #define TCR_TxSZ_WIDTH		6
 #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
+#define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
 
 #define TCR_EPD0_SHIFT		7
 #define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c
index 1f646b07e3e9..314391a156ee 100644
--- a/arch/arm64/kernel/crash_core.c
+++ b/arch/arm64/kernel/crash_core.c
@@ -7,6 +7,14 @@ 
 #include <linux/crash_core.h>
 #include <asm/cpufeature.h>
 #include <asm/memory.h>
+#include <asm/pgtable-hwdef.h>
+
+static inline u64 get_tcr_el1_t1sz(void);
+
+static inline u64 get_tcr_el1_t1sz(void)
+{
+	return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
+}
 
 void arch_crash_save_vmcoreinfo(void)
 {
@@ -16,6 +24,8 @@  void arch_crash_save_vmcoreinfo(void)
 						kimage_voffset);
 	vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n",
 						PHYS_OFFSET);
+	vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n",
+						get_tcr_el1_t1sz());
 	vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
 	vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n",
 						system_supports_address_auth() ?