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[6/8] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC

Message ID 20210401115457.22318-7-xnox@ubuntu.com
State New
Headers show
Series [1/8] Revert "RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740" | expand

Commit Message

Dimitri John Ledkov April 1, 2021, 11:54 a.m. UTC 
From: Yash Shah <yash.shah@sifive.com>

Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
(cherry picked from commit 75e6d7248efccc2b13d0f3811b29d3e5cb04bcad)
Signed-off-by: Dimitri John Ledkov <xnox@ubuntu.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0b16e4..eb6843f69f7c 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@  properties:
       - items:
           - enum:
               - sifive,rocket0
+              - sifive,bullet0
               - sifive,e5
+              - sifive,e7
               - sifive,e51
+              - sifive,e71
               - sifive,u54-mc
+              - sifive,u74-mc
               - sifive,u54
+              - sifive,u74
               - sifive,u5
+              - sifive,u7
           - const: riscv
       - const: riscv    # Simulator only
     description: